fec_mxc.c 26 KB

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  1. /*
  2. * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
  3. * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
  4. * (C) Copyright 2008 Armadeus Systems nc
  5. * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  6. * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #include <common.h>
  11. #include <malloc.h>
  12. #include <net.h>
  13. #include <miiphy.h>
  14. #include "fec_mxc.h"
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/imx-regs.h>
  17. #include <asm/io.h>
  18. #include <asm/errno.h>
  19. #include <linux/compiler.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. /*
  22. * Timeout the transfer after 5 mS. This is usually a bit more, since
  23. * the code in the tightloops this timeout is used in adds some overhead.
  24. */
  25. #define FEC_XFER_TIMEOUT 5000
  26. #ifndef CONFIG_MII
  27. #error "CONFIG_MII has to be defined!"
  28. #endif
  29. #ifndef CONFIG_FEC_XCV_TYPE
  30. #define CONFIG_FEC_XCV_TYPE MII100
  31. #endif
  32. /*
  33. * The i.MX28 operates with packets in big endian. We need to swap them before
  34. * sending and after receiving.
  35. */
  36. #ifdef CONFIG_MX28
  37. #define CONFIG_FEC_MXC_SWAP_PACKET
  38. #endif
  39. #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
  40. /* Check various alignment issues at compile time */
  41. #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
  42. #error "ARCH_DMA_MINALIGN must be multiple of 16!"
  43. #endif
  44. #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
  45. (PKTALIGN % ARCH_DMA_MINALIGN != 0))
  46. #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
  47. #endif
  48. #undef DEBUG
  49. struct nbuf {
  50. uint8_t data[1500]; /**< actual data */
  51. int length; /**< actual length */
  52. int used; /**< buffer in use or not */
  53. uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
  54. };
  55. #ifdef CONFIG_FEC_MXC_SWAP_PACKET
  56. static void swap_packet(uint32_t *packet, int length)
  57. {
  58. int i;
  59. for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
  60. packet[i] = __swab32(packet[i]);
  61. }
  62. #endif
  63. /*
  64. * MII-interface related functions
  65. */
  66. static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
  67. uint8_t regAddr)
  68. {
  69. uint32_t reg; /* convenient holder for the PHY register */
  70. uint32_t phy; /* convenient holder for the PHY */
  71. uint32_t start;
  72. int val;
  73. /*
  74. * reading from any PHY's register is done by properly
  75. * programming the FEC's MII data register.
  76. */
  77. writel(FEC_IEVENT_MII, &eth->ievent);
  78. reg = regAddr << FEC_MII_DATA_RA_SHIFT;
  79. phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
  80. writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
  81. phy | reg, &eth->mii_data);
  82. /*
  83. * wait for the related interrupt
  84. */
  85. start = get_timer(0);
  86. while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
  87. if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
  88. printf("Read MDIO failed...\n");
  89. return -1;
  90. }
  91. }
  92. /*
  93. * clear mii interrupt bit
  94. */
  95. writel(FEC_IEVENT_MII, &eth->ievent);
  96. /*
  97. * it's now safe to read the PHY's register
  98. */
  99. val = (unsigned short)readl(&eth->mii_data);
  100. debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
  101. regAddr, val);
  102. return val;
  103. }
  104. static void fec_mii_setspeed(struct ethernet_regs *eth)
  105. {
  106. /*
  107. * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
  108. * and do not drop the Preamble.
  109. */
  110. writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
  111. &eth->mii_speed);
  112. debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed));
  113. }
  114. static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
  115. uint8_t regAddr, uint16_t data)
  116. {
  117. uint32_t reg; /* convenient holder for the PHY register */
  118. uint32_t phy; /* convenient holder for the PHY */
  119. uint32_t start;
  120. reg = regAddr << FEC_MII_DATA_RA_SHIFT;
  121. phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
  122. writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
  123. FEC_MII_DATA_TA | phy | reg | data, &eth->mii_data);
  124. /*
  125. * wait for the MII interrupt
  126. */
  127. start = get_timer(0);
  128. while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
  129. if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
  130. printf("Write MDIO failed...\n");
  131. return -1;
  132. }
  133. }
  134. /*
  135. * clear MII interrupt bit
  136. */
  137. writel(FEC_IEVENT_MII, &eth->ievent);
  138. debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
  139. regAddr, data);
  140. return 0;
  141. }
  142. int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr)
  143. {
  144. return fec_mdio_read(bus->priv, phyAddr, regAddr);
  145. }
  146. int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr,
  147. u16 data)
  148. {
  149. return fec_mdio_write(bus->priv, phyAddr, regAddr, data);
  150. }
  151. #ifndef CONFIG_PHYLIB
  152. static int miiphy_restart_aneg(struct eth_device *dev)
  153. {
  154. int ret = 0;
  155. #if !defined(CONFIG_FEC_MXC_NO_ANEG)
  156. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  157. struct ethernet_regs *eth = fec->bus->priv;
  158. /*
  159. * Wake up from sleep if necessary
  160. * Reset PHY, then delay 300ns
  161. */
  162. #ifdef CONFIG_MX27
  163. fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
  164. #endif
  165. fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
  166. udelay(1000);
  167. /*
  168. * Set the auto-negotiation advertisement register bits
  169. */
  170. fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
  171. LPA_100FULL | LPA_100HALF | LPA_10FULL |
  172. LPA_10HALF | PHY_ANLPAR_PSB_802_3);
  173. fec_mdio_write(eth, fec->phy_id, MII_BMCR,
  174. BMCR_ANENABLE | BMCR_ANRESTART);
  175. if (fec->mii_postcall)
  176. ret = fec->mii_postcall(fec->phy_id);
  177. #endif
  178. return ret;
  179. }
  180. static int miiphy_wait_aneg(struct eth_device *dev)
  181. {
  182. uint32_t start;
  183. int status;
  184. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  185. struct ethernet_regs *eth = fec->bus->priv;
  186. /*
  187. * Wait for AN completion
  188. */
  189. start = get_timer(0);
  190. do {
  191. if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
  192. printf("%s: Autonegotiation timeout\n", dev->name);
  193. return -1;
  194. }
  195. status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
  196. if (status < 0) {
  197. printf("%s: Autonegotiation failed. status: %d\n",
  198. dev->name, status);
  199. return -1;
  200. }
  201. } while (!(status & BMSR_LSTATUS));
  202. return 0;
  203. }
  204. #endif
  205. static int fec_rx_task_enable(struct fec_priv *fec)
  206. {
  207. writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
  208. return 0;
  209. }
  210. static int fec_rx_task_disable(struct fec_priv *fec)
  211. {
  212. return 0;
  213. }
  214. static int fec_tx_task_enable(struct fec_priv *fec)
  215. {
  216. writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
  217. return 0;
  218. }
  219. static int fec_tx_task_disable(struct fec_priv *fec)
  220. {
  221. return 0;
  222. }
  223. /**
  224. * Initialize receive task's buffer descriptors
  225. * @param[in] fec all we know about the device yet
  226. * @param[in] count receive buffer count to be allocated
  227. * @param[in] dsize desired size of each receive buffer
  228. * @return 0 on success
  229. *
  230. * For this task we need additional memory for the data buffers. And each
  231. * data buffer requires some alignment. Thy must be aligned to a specific
  232. * boundary each.
  233. */
  234. static int fec_rbd_init(struct fec_priv *fec, int count, int dsize)
  235. {
  236. uint32_t size;
  237. int i;
  238. /*
  239. * Allocate memory for the buffers. This allocation respects the
  240. * alignment
  241. */
  242. size = roundup(dsize, ARCH_DMA_MINALIGN);
  243. for (i = 0; i < count; i++) {
  244. uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
  245. if (data_ptr == 0) {
  246. uint8_t *data = memalign(ARCH_DMA_MINALIGN,
  247. size);
  248. if (!data) {
  249. printf("%s: error allocating rxbuf %d\n",
  250. __func__, i);
  251. goto err;
  252. }
  253. writel((uint32_t)data, &fec->rbd_base[i].data_pointer);
  254. } /* needs allocation */
  255. writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status);
  256. writew(0, &fec->rbd_base[i].data_length);
  257. }
  258. /* Mark the last RBD to close the ring. */
  259. writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status);
  260. fec->rbd_index = 0;
  261. return 0;
  262. err:
  263. for (; i >= 0; i--) {
  264. uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
  265. free((void *)data_ptr);
  266. }
  267. return -ENOMEM;
  268. }
  269. /**
  270. * Initialize transmit task's buffer descriptors
  271. * @param[in] fec all we know about the device yet
  272. *
  273. * Transmit buffers are created externally. We only have to init the BDs here.\n
  274. * Note: There is a race condition in the hardware. When only one BD is in
  275. * use it must be marked with the WRAP bit to use it for every transmitt.
  276. * This bit in combination with the READY bit results into double transmit
  277. * of each data buffer. It seems the state machine checks READY earlier then
  278. * resetting it after the first transfer.
  279. * Using two BDs solves this issue.
  280. */
  281. static void fec_tbd_init(struct fec_priv *fec)
  282. {
  283. unsigned addr = (unsigned)fec->tbd_base;
  284. unsigned size = roundup(2 * sizeof(struct fec_bd),
  285. ARCH_DMA_MINALIGN);
  286. writew(0x0000, &fec->tbd_base[0].status);
  287. writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
  288. fec->tbd_index = 0;
  289. flush_dcache_range(addr, addr+size);
  290. }
  291. /**
  292. * Mark the given read buffer descriptor as free
  293. * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
  294. * @param[in] pRbd buffer descriptor to mark free again
  295. */
  296. static void fec_rbd_clean(int last, struct fec_bd *pRbd)
  297. {
  298. unsigned short flags = FEC_RBD_EMPTY;
  299. if (last)
  300. flags |= FEC_RBD_WRAP;
  301. writew(flags, &pRbd->status);
  302. writew(0, &pRbd->data_length);
  303. }
  304. static int fec_get_hwaddr(struct eth_device *dev, int dev_id,
  305. unsigned char *mac)
  306. {
  307. imx_get_mac_from_fuse(dev_id, mac);
  308. return !is_valid_ether_addr(mac);
  309. }
  310. static int fec_set_hwaddr(struct eth_device *dev)
  311. {
  312. uchar *mac = dev->enetaddr;
  313. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  314. writel(0, &fec->eth->iaddr1);
  315. writel(0, &fec->eth->iaddr2);
  316. writel(0, &fec->eth->gaddr1);
  317. writel(0, &fec->eth->gaddr2);
  318. /*
  319. * Set physical address
  320. */
  321. writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
  322. &fec->eth->paddr1);
  323. writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
  324. return 0;
  325. }
  326. /*
  327. * Do initial configuration of the FEC registers
  328. */
  329. static void fec_reg_setup(struct fec_priv *fec)
  330. {
  331. uint32_t rcntrl;
  332. /*
  333. * Set interrupt mask register
  334. */
  335. writel(0x00000000, &fec->eth->imask);
  336. /*
  337. * Clear FEC-Lite interrupt event register(IEVENT)
  338. */
  339. writel(0xffffffff, &fec->eth->ievent);
  340. /*
  341. * Set FEC-Lite receive control register(R_CNTRL):
  342. */
  343. /* Start with frame length = 1518, common for all modes. */
  344. rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
  345. if (fec->xcv_type != SEVENWIRE) /* xMII modes */
  346. rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
  347. if (fec->xcv_type == RGMII)
  348. rcntrl |= FEC_RCNTRL_RGMII;
  349. else if (fec->xcv_type == RMII)
  350. rcntrl |= FEC_RCNTRL_RMII;
  351. writel(rcntrl, &fec->eth->r_cntrl);
  352. }
  353. /**
  354. * Start the FEC engine
  355. * @param[in] dev Our device to handle
  356. */
  357. static int fec_open(struct eth_device *edev)
  358. {
  359. struct fec_priv *fec = (struct fec_priv *)edev->priv;
  360. int speed;
  361. uint32_t addr, size;
  362. int i;
  363. debug("fec_open: fec_open(dev)\n");
  364. /* full-duplex, heartbeat disabled */
  365. writel(1 << 2, &fec->eth->x_cntrl);
  366. fec->rbd_index = 0;
  367. /* Invalidate all descriptors */
  368. for (i = 0; i < FEC_RBD_NUM - 1; i++)
  369. fec_rbd_clean(0, &fec->rbd_base[i]);
  370. fec_rbd_clean(1, &fec->rbd_base[i]);
  371. /* Flush the descriptors into RAM */
  372. size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
  373. ARCH_DMA_MINALIGN);
  374. addr = (uint32_t)fec->rbd_base;
  375. flush_dcache_range(addr, addr + size);
  376. #ifdef FEC_QUIRK_ENET_MAC
  377. /* Enable ENET HW endian SWAP */
  378. writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
  379. &fec->eth->ecntrl);
  380. /* Enable ENET store and forward mode */
  381. writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
  382. &fec->eth->x_wmrk);
  383. #endif
  384. /*
  385. * Enable FEC-Lite controller
  386. */
  387. writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
  388. &fec->eth->ecntrl);
  389. #if defined(CONFIG_MX25) || defined(CONFIG_MX53)
  390. udelay(100);
  391. /*
  392. * setup the MII gasket for RMII mode
  393. */
  394. /* disable the gasket */
  395. writew(0, &fec->eth->miigsk_enr);
  396. /* wait for the gasket to be disabled */
  397. while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
  398. udelay(2);
  399. /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
  400. writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
  401. /* re-enable the gasket */
  402. writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
  403. /* wait until MII gasket is ready */
  404. int max_loops = 10;
  405. while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
  406. if (--max_loops <= 0) {
  407. printf("WAIT for MII Gasket ready timed out\n");
  408. break;
  409. }
  410. }
  411. #endif
  412. #ifdef CONFIG_PHYLIB
  413. {
  414. /* Start up the PHY */
  415. int ret = phy_startup(fec->phydev);
  416. if (ret) {
  417. printf("Could not initialize PHY %s\n",
  418. fec->phydev->dev->name);
  419. return ret;
  420. }
  421. speed = fec->phydev->speed;
  422. }
  423. #else
  424. miiphy_wait_aneg(edev);
  425. speed = miiphy_speed(edev->name, fec->phy_id);
  426. miiphy_duplex(edev->name, fec->phy_id);
  427. #endif
  428. #ifdef FEC_QUIRK_ENET_MAC
  429. {
  430. u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
  431. u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
  432. if (speed == _1000BASET)
  433. ecr |= FEC_ECNTRL_SPEED;
  434. else if (speed != _100BASET)
  435. rcr |= FEC_RCNTRL_RMII_10T;
  436. writel(ecr, &fec->eth->ecntrl);
  437. writel(rcr, &fec->eth->r_cntrl);
  438. }
  439. #endif
  440. debug("%s:Speed=%i\n", __func__, speed);
  441. /*
  442. * Enable SmartDMA receive task
  443. */
  444. fec_rx_task_enable(fec);
  445. udelay(100000);
  446. return 0;
  447. }
  448. static int fec_init(struct eth_device *dev, bd_t* bd)
  449. {
  450. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  451. uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
  452. uint32_t size;
  453. int i, ret;
  454. /* Initialize MAC address */
  455. fec_set_hwaddr(dev);
  456. /*
  457. * Allocate transmit descriptors, there are two in total. This
  458. * allocation respects cache alignment.
  459. */
  460. if (!fec->tbd_base) {
  461. size = roundup(2 * sizeof(struct fec_bd),
  462. ARCH_DMA_MINALIGN);
  463. fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
  464. if (!fec->tbd_base) {
  465. ret = -ENOMEM;
  466. goto err1;
  467. }
  468. memset(fec->tbd_base, 0, size);
  469. fec_tbd_init(fec);
  470. }
  471. /*
  472. * Allocate receive descriptors. This allocation respects cache
  473. * alignment.
  474. */
  475. if (!fec->rbd_base) {
  476. size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
  477. ARCH_DMA_MINALIGN);
  478. fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
  479. if (!fec->rbd_base) {
  480. ret = -ENOMEM;
  481. goto err2;
  482. }
  483. memset(fec->rbd_base, 0, size);
  484. /*
  485. * Initialize RxBD ring
  486. */
  487. if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
  488. ret = -ENOMEM;
  489. goto err3;
  490. }
  491. flush_dcache_range((unsigned)fec->rbd_base,
  492. (unsigned)fec->rbd_base + size);
  493. }
  494. fec_reg_setup(fec);
  495. if (fec->xcv_type != SEVENWIRE)
  496. fec_mii_setspeed(fec->bus->priv);
  497. /*
  498. * Set Opcode/Pause Duration Register
  499. */
  500. writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
  501. writel(0x2, &fec->eth->x_wmrk);
  502. /*
  503. * Set multicast address filter
  504. */
  505. writel(0x00000000, &fec->eth->gaddr1);
  506. writel(0x00000000, &fec->eth->gaddr2);
  507. /* clear MIB RAM */
  508. for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
  509. writel(0, i);
  510. /* FIFO receive start register */
  511. writel(0x520, &fec->eth->r_fstart);
  512. /* size and address of each buffer */
  513. writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
  514. writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
  515. writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
  516. #ifndef CONFIG_PHYLIB
  517. if (fec->xcv_type != SEVENWIRE)
  518. miiphy_restart_aneg(dev);
  519. #endif
  520. fec_open(dev);
  521. return 0;
  522. err3:
  523. free(fec->rbd_base);
  524. err2:
  525. free(fec->tbd_base);
  526. err1:
  527. return ret;
  528. }
  529. /**
  530. * Halt the FEC engine
  531. * @param[in] dev Our device to handle
  532. */
  533. static void fec_halt(struct eth_device *dev)
  534. {
  535. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  536. int counter = 0xffff;
  537. /*
  538. * issue graceful stop command to the FEC transmitter if necessary
  539. */
  540. writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
  541. &fec->eth->x_cntrl);
  542. debug("eth_halt: wait for stop regs\n");
  543. /*
  544. * wait for graceful stop to register
  545. */
  546. while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
  547. udelay(1);
  548. /*
  549. * Disable SmartDMA tasks
  550. */
  551. fec_tx_task_disable(fec);
  552. fec_rx_task_disable(fec);
  553. /*
  554. * Disable the Ethernet Controller
  555. * Note: this will also reset the BD index counter!
  556. */
  557. writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
  558. &fec->eth->ecntrl);
  559. fec->rbd_index = 0;
  560. fec->tbd_index = 0;
  561. debug("eth_halt: done\n");
  562. }
  563. /**
  564. * Transmit one frame
  565. * @param[in] dev Our ethernet device to handle
  566. * @param[in] packet Pointer to the data to be transmitted
  567. * @param[in] length Data count in bytes
  568. * @return 0 on success
  569. */
  570. static int fec_send(struct eth_device *dev, void *packet, int length)
  571. {
  572. unsigned int status;
  573. uint32_t size, end;
  574. uint32_t addr;
  575. int timeout = FEC_XFER_TIMEOUT;
  576. int ret = 0;
  577. /*
  578. * This routine transmits one frame. This routine only accepts
  579. * 6-byte Ethernet addresses.
  580. */
  581. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  582. /*
  583. * Check for valid length of data.
  584. */
  585. if ((length > 1500) || (length <= 0)) {
  586. printf("Payload (%d) too large\n", length);
  587. return -1;
  588. }
  589. /*
  590. * Setup the transmit buffer. We are always using the first buffer for
  591. * transmission, the second will be empty and only used to stop the DMA
  592. * engine. We also flush the packet to RAM here to avoid cache trouble.
  593. */
  594. #ifdef CONFIG_FEC_MXC_SWAP_PACKET
  595. swap_packet((uint32_t *)packet, length);
  596. #endif
  597. addr = (uint32_t)packet;
  598. end = roundup(addr + length, ARCH_DMA_MINALIGN);
  599. addr &= ~(ARCH_DMA_MINALIGN - 1);
  600. flush_dcache_range(addr, end);
  601. writew(length, &fec->tbd_base[fec->tbd_index].data_length);
  602. writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer);
  603. /*
  604. * update BD's status now
  605. * This block:
  606. * - is always the last in a chain (means no chain)
  607. * - should transmitt the CRC
  608. * - might be the last BD in the list, so the address counter should
  609. * wrap (-> keep the WRAP flag)
  610. */
  611. status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
  612. status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
  613. writew(status, &fec->tbd_base[fec->tbd_index].status);
  614. /*
  615. * Flush data cache. This code flushes both TX descriptors to RAM.
  616. * After this code, the descriptors will be safely in RAM and we
  617. * can start DMA.
  618. */
  619. size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
  620. addr = (uint32_t)fec->tbd_base;
  621. flush_dcache_range(addr, addr + size);
  622. /*
  623. * Below we read the DMA descriptor's last four bytes back from the
  624. * DRAM. This is important in order to make sure that all WRITE
  625. * operations on the bus that were triggered by previous cache FLUSH
  626. * have completed.
  627. *
  628. * Otherwise, on MX28, it is possible to observe a corruption of the
  629. * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
  630. * for the bus structure of MX28. The scenario is as follows:
  631. *
  632. * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
  633. * to DRAM due to flush_dcache_range()
  634. * 2) ARM core writes the FEC registers via AHB_ARB2
  635. * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
  636. *
  637. * Note that 2) does sometimes finish before 1) due to reordering of
  638. * WRITE accesses on the AHB bus, therefore triggering 3) before the
  639. * DMA descriptor is fully written into DRAM. This results in occasional
  640. * corruption of the DMA descriptor.
  641. */
  642. readl(addr + size - 4);
  643. /*
  644. * Enable SmartDMA transmit task
  645. */
  646. fec_tx_task_enable(fec);
  647. /*
  648. * Wait until frame is sent. On each turn of the wait cycle, we must
  649. * invalidate data cache to see what's really in RAM. Also, we need
  650. * barrier here.
  651. */
  652. while (--timeout) {
  653. if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
  654. break;
  655. }
  656. if (!timeout)
  657. ret = -EINVAL;
  658. invalidate_dcache_range(addr, addr + size);
  659. if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY)
  660. ret = -EINVAL;
  661. debug("fec_send: status 0x%x index %d ret %i\n",
  662. readw(&fec->tbd_base[fec->tbd_index].status),
  663. fec->tbd_index, ret);
  664. /* for next transmission use the other buffer */
  665. if (fec->tbd_index)
  666. fec->tbd_index = 0;
  667. else
  668. fec->tbd_index = 1;
  669. return ret;
  670. }
  671. /**
  672. * Pull one frame from the card
  673. * @param[in] dev Our ethernet device to handle
  674. * @return Length of packet read
  675. */
  676. static int fec_recv(struct eth_device *dev)
  677. {
  678. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  679. struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
  680. unsigned long ievent;
  681. int frame_length, len = 0;
  682. struct nbuf *frame;
  683. uint16_t bd_status;
  684. uint32_t addr, size, end;
  685. int i;
  686. uchar buff[FEC_MAX_PKT_SIZE] __aligned(ARCH_DMA_MINALIGN);
  687. /*
  688. * Check if any critical events have happened
  689. */
  690. ievent = readl(&fec->eth->ievent);
  691. writel(ievent, &fec->eth->ievent);
  692. debug("fec_recv: ievent 0x%lx\n", ievent);
  693. if (ievent & FEC_IEVENT_BABR) {
  694. fec_halt(dev);
  695. fec_init(dev, fec->bd);
  696. printf("some error: 0x%08lx\n", ievent);
  697. return 0;
  698. }
  699. if (ievent & FEC_IEVENT_HBERR) {
  700. /* Heartbeat error */
  701. writel(0x00000001 | readl(&fec->eth->x_cntrl),
  702. &fec->eth->x_cntrl);
  703. }
  704. if (ievent & FEC_IEVENT_GRA) {
  705. /* Graceful stop complete */
  706. if (readl(&fec->eth->x_cntrl) & 0x00000001) {
  707. fec_halt(dev);
  708. writel(~0x00000001 & readl(&fec->eth->x_cntrl),
  709. &fec->eth->x_cntrl);
  710. fec_init(dev, fec->bd);
  711. }
  712. }
  713. /*
  714. * Read the buffer status. Before the status can be read, the data cache
  715. * must be invalidated, because the data in RAM might have been changed
  716. * by DMA. The descriptors are properly aligned to cachelines so there's
  717. * no need to worry they'd overlap.
  718. *
  719. * WARNING: By invalidating the descriptor here, we also invalidate
  720. * the descriptors surrounding this one. Therefore we can NOT change the
  721. * contents of this descriptor nor the surrounding ones. The problem is
  722. * that in order to mark the descriptor as processed, we need to change
  723. * the descriptor. The solution is to mark the whole cache line when all
  724. * descriptors in the cache line are processed.
  725. */
  726. addr = (uint32_t)rbd;
  727. addr &= ~(ARCH_DMA_MINALIGN - 1);
  728. size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
  729. invalidate_dcache_range(addr, addr + size);
  730. bd_status = readw(&rbd->status);
  731. debug("fec_recv: status 0x%x\n", bd_status);
  732. if (!(bd_status & FEC_RBD_EMPTY)) {
  733. if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
  734. ((readw(&rbd->data_length) - 4) > 14)) {
  735. /*
  736. * Get buffer address and size
  737. */
  738. frame = (struct nbuf *)readl(&rbd->data_pointer);
  739. frame_length = readw(&rbd->data_length) - 4;
  740. /*
  741. * Invalidate data cache over the buffer
  742. */
  743. addr = (uint32_t)frame;
  744. end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
  745. addr &= ~(ARCH_DMA_MINALIGN - 1);
  746. invalidate_dcache_range(addr, end);
  747. /*
  748. * Fill the buffer and pass it to upper layers
  749. */
  750. #ifdef CONFIG_FEC_MXC_SWAP_PACKET
  751. swap_packet((uint32_t *)frame->data, frame_length);
  752. #endif
  753. memcpy(buff, frame->data, frame_length);
  754. NetReceive(buff, frame_length);
  755. len = frame_length;
  756. } else {
  757. if (bd_status & FEC_RBD_ERR)
  758. printf("error frame: 0x%08lx 0x%08x\n",
  759. (ulong)rbd->data_pointer,
  760. bd_status);
  761. }
  762. /*
  763. * Free the current buffer, restart the engine and move forward
  764. * to the next buffer. Here we check if the whole cacheline of
  765. * descriptors was already processed and if so, we mark it free
  766. * as whole.
  767. */
  768. size = RXDESC_PER_CACHELINE - 1;
  769. if ((fec->rbd_index & size) == size) {
  770. i = fec->rbd_index - size;
  771. addr = (uint32_t)&fec->rbd_base[i];
  772. for (; i <= fec->rbd_index ; i++) {
  773. fec_rbd_clean(i == (FEC_RBD_NUM - 1),
  774. &fec->rbd_base[i]);
  775. }
  776. flush_dcache_range(addr,
  777. addr + ARCH_DMA_MINALIGN);
  778. }
  779. fec_rx_task_enable(fec);
  780. fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
  781. }
  782. debug("fec_recv: stop\n");
  783. return len;
  784. }
  785. static void fec_set_dev_name(char *dest, int dev_id)
  786. {
  787. sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
  788. }
  789. #ifdef CONFIG_PHYLIB
  790. int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
  791. struct mii_dev *bus, struct phy_device *phydev)
  792. #else
  793. static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
  794. struct mii_dev *bus, int phy_id)
  795. #endif
  796. {
  797. struct eth_device *edev;
  798. struct fec_priv *fec;
  799. unsigned char ethaddr[6];
  800. uint32_t start;
  801. int ret = 0;
  802. /* create and fill edev struct */
  803. edev = (struct eth_device *)malloc(sizeof(struct eth_device));
  804. if (!edev) {
  805. puts("fec_mxc: not enough malloc memory for eth_device\n");
  806. ret = -ENOMEM;
  807. goto err1;
  808. }
  809. fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
  810. if (!fec) {
  811. puts("fec_mxc: not enough malloc memory for fec_priv\n");
  812. ret = -ENOMEM;
  813. goto err2;
  814. }
  815. memset(edev, 0, sizeof(*edev));
  816. memset(fec, 0, sizeof(*fec));
  817. edev->priv = fec;
  818. edev->init = fec_init;
  819. edev->send = fec_send;
  820. edev->recv = fec_recv;
  821. edev->halt = fec_halt;
  822. edev->write_hwaddr = fec_set_hwaddr;
  823. fec->eth = (struct ethernet_regs *)base_addr;
  824. fec->bd = bd;
  825. fec->xcv_type = CONFIG_FEC_XCV_TYPE;
  826. /* Reset chip. */
  827. writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
  828. start = get_timer(0);
  829. while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
  830. if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
  831. printf("FEC MXC: Timeout reseting chip\n");
  832. goto err3;
  833. }
  834. udelay(10);
  835. }
  836. fec_reg_setup(fec);
  837. fec_set_dev_name(edev->name, dev_id);
  838. fec->dev_id = (dev_id == -1) ? 0 : dev_id;
  839. fec->bus = bus;
  840. fec_mii_setspeed(bus->priv);
  841. #ifdef CONFIG_PHYLIB
  842. fec->phydev = phydev;
  843. phy_connect_dev(phydev, edev);
  844. /* Configure phy */
  845. phy_config(phydev);
  846. #else
  847. fec->phy_id = phy_id;
  848. #endif
  849. eth_register(edev);
  850. if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
  851. debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
  852. memcpy(edev->enetaddr, ethaddr, 6);
  853. if (!getenv("ethaddr"))
  854. eth_setenv_enetaddr("ethaddr", ethaddr);
  855. }
  856. return ret;
  857. err3:
  858. free(fec);
  859. err2:
  860. free(edev);
  861. err1:
  862. return ret;
  863. }
  864. struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
  865. {
  866. struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
  867. struct mii_dev *bus;
  868. int ret;
  869. bus = mdio_alloc();
  870. if (!bus) {
  871. printf("mdio_alloc failed\n");
  872. return NULL;
  873. }
  874. bus->read = fec_phy_read;
  875. bus->write = fec_phy_write;
  876. bus->priv = eth;
  877. fec_set_dev_name(bus->name, dev_id);
  878. ret = mdio_register(bus);
  879. if (ret) {
  880. printf("mdio_register failed\n");
  881. free(bus);
  882. return NULL;
  883. }
  884. fec_mii_setspeed(eth);
  885. return bus;
  886. }
  887. int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
  888. {
  889. uint32_t base_mii;
  890. struct mii_dev *bus = NULL;
  891. #ifdef CONFIG_PHYLIB
  892. struct phy_device *phydev = NULL;
  893. #endif
  894. int ret;
  895. #ifdef CONFIG_MX28
  896. /*
  897. * The i.MX28 has two ethernet interfaces, but they are not equal.
  898. * Only the first one can access the MDIO bus.
  899. */
  900. base_mii = MXS_ENET0_BASE;
  901. #else
  902. base_mii = addr;
  903. #endif
  904. debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
  905. bus = fec_get_miibus(base_mii, dev_id);
  906. if (!bus)
  907. return -ENOMEM;
  908. #ifdef CONFIG_PHYLIB
  909. phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
  910. if (!phydev) {
  911. free(bus);
  912. return -ENOMEM;
  913. }
  914. ret = fec_probe(bd, dev_id, addr, bus, phydev);
  915. #else
  916. ret = fec_probe(bd, dev_id, addr, bus, phy_id);
  917. #endif
  918. if (ret) {
  919. #ifdef CONFIG_PHYLIB
  920. free(phydev);
  921. #endif
  922. free(bus);
  923. }
  924. return ret;
  925. }
  926. #ifdef CONFIG_FEC_MXC_PHYADDR
  927. int fecmxc_initialize(bd_t *bd)
  928. {
  929. return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
  930. IMX_FEC_BASE);
  931. }
  932. #endif
  933. #ifndef CONFIG_PHYLIB
  934. int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
  935. {
  936. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  937. fec->mii_postcall = cb;
  938. return 0;
  939. }
  940. #endif