mxsmmc.c 11 KB

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  1. /*
  2. * Freescale i.MX28 SSP MMC driver
  3. *
  4. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  5. * on behalf of DENX Software Engineering GmbH
  6. *
  7. * Based on code from LTIB:
  8. * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  9. * Terry Lv
  10. *
  11. * Copyright 2007, Freescale Semiconductor, Inc
  12. * Andy Fleming
  13. *
  14. * Based vaguely on the pxa mmc code:
  15. * (C) Copyright 2003
  16. * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  17. *
  18. * SPDX-License-Identifier: GPL-2.0+
  19. */
  20. #include <common.h>
  21. #include <malloc.h>
  22. #include <mmc.h>
  23. #include <asm/errno.h>
  24. #include <asm/io.h>
  25. #include <asm/arch/clock.h>
  26. #include <asm/arch/imx-regs.h>
  27. #include <asm/arch/sys_proto.h>
  28. #include <asm/imx-common/dma.h>
  29. #include <bouncebuf.h>
  30. struct mxsmmc_priv {
  31. int id;
  32. struct mxs_ssp_regs *regs;
  33. uint32_t buswidth;
  34. int (*mmc_is_wp)(int);
  35. int (*mmc_cd)(int);
  36. struct mxs_dma_desc *desc;
  37. };
  38. #define MXSMMC_MAX_TIMEOUT 10000
  39. #define MXSMMC_SMALL_TRANSFER 512
  40. static int mxsmmc_cd(struct mxsmmc_priv *priv)
  41. {
  42. struct mxs_ssp_regs *ssp_regs = priv->regs;
  43. if (priv->mmc_cd)
  44. return priv->mmc_cd(priv->id);
  45. return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
  46. }
  47. static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
  48. {
  49. struct mxs_ssp_regs *ssp_regs = priv->regs;
  50. uint32_t *data_ptr;
  51. int timeout = MXSMMC_MAX_TIMEOUT;
  52. uint32_t reg;
  53. uint32_t data_count = data->blocksize * data->blocks;
  54. if (data->flags & MMC_DATA_READ) {
  55. data_ptr = (uint32_t *)data->dest;
  56. while (data_count && --timeout) {
  57. reg = readl(&ssp_regs->hw_ssp_status);
  58. if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
  59. *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
  60. data_count -= 4;
  61. timeout = MXSMMC_MAX_TIMEOUT;
  62. } else
  63. udelay(1000);
  64. }
  65. } else {
  66. data_ptr = (uint32_t *)data->src;
  67. timeout *= 100;
  68. while (data_count && --timeout) {
  69. reg = readl(&ssp_regs->hw_ssp_status);
  70. if (!(reg & SSP_STATUS_FIFO_FULL)) {
  71. writel(*data_ptr++, &ssp_regs->hw_ssp_data);
  72. data_count -= 4;
  73. timeout = MXSMMC_MAX_TIMEOUT;
  74. } else
  75. udelay(1000);
  76. }
  77. }
  78. return timeout ? 0 : COMM_ERR;
  79. }
  80. static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
  81. {
  82. uint32_t data_count = data->blocksize * data->blocks;
  83. int dmach;
  84. struct mxs_dma_desc *desc = priv->desc;
  85. void *addr;
  86. unsigned int flags;
  87. struct bounce_buffer bbstate;
  88. memset(desc, 0, sizeof(struct mxs_dma_desc));
  89. desc->address = (dma_addr_t)desc;
  90. if (data->flags & MMC_DATA_READ) {
  91. priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
  92. addr = data->dest;
  93. flags = GEN_BB_WRITE;
  94. } else {
  95. priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
  96. addr = (void *)data->src;
  97. flags = GEN_BB_READ;
  98. }
  99. bounce_buffer_start(&bbstate, addr, data_count, flags);
  100. priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
  101. priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
  102. (data_count << MXS_DMA_DESC_BYTES_OFFSET);
  103. dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
  104. mxs_dma_desc_append(dmach, priv->desc);
  105. if (mxs_dma_go(dmach)) {
  106. bounce_buffer_stop(&bbstate);
  107. return COMM_ERR;
  108. }
  109. bounce_buffer_stop(&bbstate);
  110. return 0;
  111. }
  112. /*
  113. * Sends a command out on the bus. Takes the mmc pointer,
  114. * a command pointer, and an optional data pointer.
  115. */
  116. static int
  117. mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
  118. {
  119. struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
  120. struct mxs_ssp_regs *ssp_regs = priv->regs;
  121. uint32_t reg;
  122. int timeout;
  123. uint32_t ctrl0;
  124. int ret;
  125. debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
  126. /* Check bus busy */
  127. timeout = MXSMMC_MAX_TIMEOUT;
  128. while (--timeout) {
  129. udelay(1000);
  130. reg = readl(&ssp_regs->hw_ssp_status);
  131. if (!(reg &
  132. (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
  133. SSP_STATUS_CMD_BUSY))) {
  134. break;
  135. }
  136. }
  137. if (!timeout) {
  138. printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
  139. return TIMEOUT;
  140. }
  141. /* See if card is present */
  142. if (!mxsmmc_cd(priv)) {
  143. printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
  144. return NO_CARD_ERR;
  145. }
  146. /* Start building CTRL0 contents */
  147. ctrl0 = priv->buswidth;
  148. /* Set up command */
  149. if (!(cmd->resp_type & MMC_RSP_CRC))
  150. ctrl0 |= SSP_CTRL0_IGNORE_CRC;
  151. if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
  152. ctrl0 |= SSP_CTRL0_GET_RESP;
  153. if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
  154. ctrl0 |= SSP_CTRL0_LONG_RESP;
  155. if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
  156. writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
  157. else
  158. writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
  159. /* Command index */
  160. reg = readl(&ssp_regs->hw_ssp_cmd0);
  161. reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
  162. reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
  163. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  164. reg |= SSP_CMD0_APPEND_8CYC;
  165. writel(reg, &ssp_regs->hw_ssp_cmd0);
  166. /* Command argument */
  167. writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
  168. /* Set up data */
  169. if (data) {
  170. /* READ or WRITE */
  171. if (data->flags & MMC_DATA_READ) {
  172. ctrl0 |= SSP_CTRL0_READ;
  173. } else if (priv->mmc_is_wp &&
  174. priv->mmc_is_wp(mmc->block_dev.dev)) {
  175. printf("MMC%d: Can not write a locked card!\n",
  176. mmc->block_dev.dev);
  177. return UNUSABLE_ERR;
  178. }
  179. ctrl0 |= SSP_CTRL0_DATA_XFER;
  180. reg = data->blocksize * data->blocks;
  181. #if defined(CONFIG_MX23)
  182. ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
  183. clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
  184. SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
  185. ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
  186. ((ffs(data->blocksize) - 1) <<
  187. SSP_CMD0_BLOCK_SIZE_OFFSET));
  188. #elif defined(CONFIG_MX28)
  189. writel(reg, &ssp_regs->hw_ssp_xfer_size);
  190. reg = ((data->blocks - 1) <<
  191. SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
  192. ((ffs(data->blocksize) - 1) <<
  193. SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
  194. writel(reg, &ssp_regs->hw_ssp_block_size);
  195. #endif
  196. }
  197. /* Kick off the command */
  198. ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
  199. writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
  200. /* Wait for the command to complete */
  201. timeout = MXSMMC_MAX_TIMEOUT;
  202. while (--timeout) {
  203. udelay(1000);
  204. reg = readl(&ssp_regs->hw_ssp_status);
  205. if (!(reg & SSP_STATUS_CMD_BUSY))
  206. break;
  207. }
  208. if (!timeout) {
  209. printf("MMC%d: Command %d busy\n",
  210. mmc->block_dev.dev, cmd->cmdidx);
  211. return TIMEOUT;
  212. }
  213. /* Check command timeout */
  214. if (reg & SSP_STATUS_RESP_TIMEOUT) {
  215. printf("MMC%d: Command %d timeout (status 0x%08x)\n",
  216. mmc->block_dev.dev, cmd->cmdidx, reg);
  217. return TIMEOUT;
  218. }
  219. /* Check command errors */
  220. if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
  221. printf("MMC%d: Command %d error (status 0x%08x)!\n",
  222. mmc->block_dev.dev, cmd->cmdidx, reg);
  223. return COMM_ERR;
  224. }
  225. /* Copy response to response buffer */
  226. if (cmd->resp_type & MMC_RSP_136) {
  227. cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
  228. cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
  229. cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
  230. cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
  231. } else
  232. cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
  233. /* Return if no data to process */
  234. if (!data)
  235. return 0;
  236. if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
  237. ret = mxsmmc_send_cmd_pio(priv, data);
  238. if (ret) {
  239. printf("MMC%d: Data timeout with command %d "
  240. "(status 0x%08x)!\n",
  241. mmc->block_dev.dev, cmd->cmdidx, reg);
  242. return ret;
  243. }
  244. } else {
  245. ret = mxsmmc_send_cmd_dma(priv, data);
  246. if (ret) {
  247. printf("MMC%d: DMA transfer failed\n",
  248. mmc->block_dev.dev);
  249. return ret;
  250. }
  251. }
  252. /* Check data errors */
  253. reg = readl(&ssp_regs->hw_ssp_status);
  254. if (reg &
  255. (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
  256. SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
  257. printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
  258. mmc->block_dev.dev, cmd->cmdidx, reg);
  259. return COMM_ERR;
  260. }
  261. return 0;
  262. }
  263. static void mxsmmc_set_ios(struct mmc *mmc)
  264. {
  265. struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
  266. struct mxs_ssp_regs *ssp_regs = priv->regs;
  267. /* Set the clock speed */
  268. if (mmc->clock)
  269. mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
  270. switch (mmc->bus_width) {
  271. case 1:
  272. priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
  273. break;
  274. case 4:
  275. priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
  276. break;
  277. case 8:
  278. priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
  279. break;
  280. }
  281. /* Set the bus width */
  282. clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
  283. SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
  284. debug("MMC%d: Set %d bits bus width\n",
  285. mmc->block_dev.dev, mmc->bus_width);
  286. }
  287. static int mxsmmc_init(struct mmc *mmc)
  288. {
  289. struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
  290. struct mxs_ssp_regs *ssp_regs = priv->regs;
  291. /* Reset SSP */
  292. mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
  293. /* Reconfigure the SSP block for MMC operation */
  294. writel(SSP_CTRL1_SSP_MODE_SD_MMC |
  295. SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
  296. SSP_CTRL1_DMA_ENABLE |
  297. SSP_CTRL1_POLARITY |
  298. SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
  299. SSP_CTRL1_DATA_CRC_IRQ_EN |
  300. SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
  301. SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
  302. SSP_CTRL1_RESP_ERR_IRQ_EN,
  303. &ssp_regs->hw_ssp_ctrl1_set);
  304. /* Set initial bit clock 400 KHz */
  305. mxs_set_ssp_busclock(priv->id, 400);
  306. /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
  307. writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
  308. udelay(200);
  309. writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
  310. return 0;
  311. }
  312. int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
  313. {
  314. struct mmc *mmc = NULL;
  315. struct mxsmmc_priv *priv = NULL;
  316. int ret;
  317. const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);
  318. if (!mxs_ssp_bus_id_valid(id))
  319. return -ENODEV;
  320. mmc = malloc(sizeof(struct mmc));
  321. if (!mmc)
  322. return -ENOMEM;
  323. priv = malloc(sizeof(struct mxsmmc_priv));
  324. if (!priv) {
  325. free(mmc);
  326. return -ENOMEM;
  327. }
  328. priv->desc = mxs_dma_desc_alloc();
  329. if (!priv->desc) {
  330. free(priv);
  331. free(mmc);
  332. return -ENOMEM;
  333. }
  334. ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
  335. if (ret)
  336. return ret;
  337. priv->mmc_is_wp = wp;
  338. priv->mmc_cd = cd;
  339. priv->id = id;
  340. priv->regs = mxs_ssp_regs_by_bus(id);
  341. sprintf(mmc->name, "MXS MMC");
  342. mmc->send_cmd = mxsmmc_send_cmd;
  343. mmc->set_ios = mxsmmc_set_ios;
  344. mmc->init = mxsmmc_init;
  345. mmc->getcd = NULL;
  346. mmc->getwp = NULL;
  347. mmc->priv = priv;
  348. mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  349. mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
  350. MMC_MODE_HS_52MHz | MMC_MODE_HS |
  351. MMC_MODE_HC;
  352. /*
  353. * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
  354. * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
  355. * CLOCK_DIVIDE has to be an even value from 2 to 254, and
  356. * CLOCK_RATE could be any integer from 0 to 255.
  357. */
  358. mmc->f_min = 400000;
  359. mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;
  360. mmc->b_max = 0x20;
  361. mmc_register(mmc);
  362. return 0;
  363. }