at91_gpio.c 8.3 KB

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  1. /*
  2. * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
  3. *
  4. * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
  5. *
  6. * Copyright (C) 2005 HP Labs
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #include <config.h>
  11. #include <common.h>
  12. #include <asm/io.h>
  13. #include <asm/sizes.h>
  14. #include <asm/arch/hardware.h>
  15. #include <asm/arch/at91_pio.h>
  16. static struct at91_port *at91_pio_get_port(unsigned port)
  17. {
  18. switch (port) {
  19. case AT91_PIO_PORTA:
  20. return (struct at91_port *)ATMEL_BASE_PIOA;
  21. case AT91_PIO_PORTB:
  22. return (struct at91_port *)ATMEL_BASE_PIOB;
  23. case AT91_PIO_PORTC:
  24. return (struct at91_port *)ATMEL_BASE_PIOC;
  25. #if (ATMEL_PIO_PORTS > 3)
  26. case AT91_PIO_PORTD:
  27. return (struct at91_port *)ATMEL_BASE_PIOD;
  28. #if (ATMEL_PIO_PORTS > 4)
  29. case AT91_PIO_PORTE:
  30. return (struct at91_port *)ATMEL_BASE_PIOE;
  31. #endif
  32. #endif
  33. default:
  34. return NULL;
  35. }
  36. }
  37. int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
  38. {
  39. struct at91_port *at91_port = at91_pio_get_port(port);
  40. u32 mask;
  41. if (at91_port && (pin < 32)) {
  42. mask = 1 << pin;
  43. if (use_pullup)
  44. writel(1 << pin, &at91_port->puer);
  45. else
  46. writel(1 << pin, &at91_port->pudr);
  47. writel(mask, &at91_port->per);
  48. }
  49. return 0;
  50. }
  51. /*
  52. * mux the pin to the "GPIO" peripheral role.
  53. */
  54. int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup)
  55. {
  56. struct at91_port *at91_port = at91_pio_get_port(port);
  57. u32 mask;
  58. if (at91_port && (pin < 32)) {
  59. mask = 1 << pin;
  60. writel(mask, &at91_port->idr);
  61. at91_set_pio_pullup(port, pin, use_pullup);
  62. writel(mask, &at91_port->per);
  63. }
  64. return 0;
  65. }
  66. /*
  67. * mux the pin to the "A" internal peripheral role.
  68. */
  69. int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup)
  70. {
  71. struct at91_port *at91_port = at91_pio_get_port(port);
  72. u32 mask;
  73. if (at91_port && (pin < 32)) {
  74. mask = 1 << pin;
  75. writel(mask, &at91_port->idr);
  76. at91_set_pio_pullup(port, pin, use_pullup);
  77. #if defined(CPU_HAS_PIO3)
  78. writel(readl(&at91_port->abcdsr1) & ~mask,
  79. &at91_port->abcdsr1);
  80. writel(readl(&at91_port->abcdsr2) & ~mask,
  81. &at91_port->abcdsr2);
  82. #else
  83. writel(mask, &at91_port->asr);
  84. #endif
  85. writel(mask, &at91_port->pdr);
  86. }
  87. return 0;
  88. }
  89. /*
  90. * mux the pin to the "B" internal peripheral role.
  91. */
  92. int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup)
  93. {
  94. struct at91_port *at91_port = at91_pio_get_port(port);
  95. u32 mask;
  96. if (at91_port && (pin < 32)) {
  97. mask = 1 << pin;
  98. writel(mask, &at91_port->idr);
  99. at91_set_pio_pullup(port, pin, use_pullup);
  100. #if defined(CPU_HAS_PIO3)
  101. writel(readl(&at91_port->abcdsr1) | mask,
  102. &at91_port->abcdsr1);
  103. writel(readl(&at91_port->abcdsr2) & ~mask,
  104. &at91_port->abcdsr2);
  105. #else
  106. writel(mask, &at91_port->bsr);
  107. #endif
  108. writel(mask, &at91_port->pdr);
  109. }
  110. return 0;
  111. }
  112. #if defined(CPU_HAS_PIO3)
  113. /*
  114. * mux the pin to the "C" internal peripheral role.
  115. */
  116. int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup)
  117. {
  118. struct at91_port *at91_port = at91_pio_get_port(port);
  119. u32 mask;
  120. if (at91_port && (pin < 32)) {
  121. mask = 1 << pin;
  122. writel(mask, &at91_port->idr);
  123. at91_set_pio_pullup(port, pin, use_pullup);
  124. writel(readl(&at91_port->abcdsr1) & ~mask,
  125. &at91_port->abcdsr1);
  126. writel(readl(&at91_port->abcdsr2) | mask,
  127. &at91_port->abcdsr2);
  128. writel(mask, &at91_port->pdr);
  129. }
  130. return 0;
  131. }
  132. /*
  133. * mux the pin to the "D" internal peripheral role.
  134. */
  135. int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup)
  136. {
  137. struct at91_port *at91_port = at91_pio_get_port(port);
  138. u32 mask;
  139. if (at91_port && (pin < 32)) {
  140. mask = 1 << pin;
  141. writel(mask, &at91_port->idr);
  142. at91_set_pio_pullup(port, pin, use_pullup);
  143. writel(readl(&at91_port->abcdsr1) | mask,
  144. &at91_port->abcdsr1);
  145. writel(readl(&at91_port->abcdsr2) | mask,
  146. &at91_port->abcdsr2);
  147. writel(mask, &at91_port->pdr);
  148. }
  149. return 0;
  150. }
  151. #endif
  152. /*
  153. * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
  154. * configure it for an input.
  155. */
  156. int at91_set_pio_input(unsigned port, u32 pin, int use_pullup)
  157. {
  158. struct at91_port *at91_port = at91_pio_get_port(port);
  159. u32 mask;
  160. if (at91_port && (pin < 32)) {
  161. mask = 1 << pin;
  162. writel(mask, &at91_port->idr);
  163. at91_set_pio_pullup(port, pin, use_pullup);
  164. writel(mask, &at91_port->odr);
  165. writel(mask, &at91_port->per);
  166. }
  167. return 0;
  168. }
  169. /*
  170. * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
  171. * and configure it for an output.
  172. */
  173. int at91_set_pio_output(unsigned port, u32 pin, int value)
  174. {
  175. struct at91_port *at91_port = at91_pio_get_port(port);
  176. u32 mask;
  177. if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
  178. mask = 1 << pin;
  179. writel(mask, &at91_port->idr);
  180. writel(mask, &at91_port->pudr);
  181. if (value)
  182. writel(mask, &at91_port->sodr);
  183. else
  184. writel(mask, &at91_port->codr);
  185. writel(mask, &at91_port->oer);
  186. writel(mask, &at91_port->per);
  187. }
  188. return 0;
  189. }
  190. /*
  191. * enable/disable the glitch filter. mostly used with IRQ handling.
  192. */
  193. int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
  194. {
  195. struct at91_port *at91_port = at91_pio_get_port(port);
  196. u32 mask;
  197. if (at91_port && (pin < 32)) {
  198. mask = 1 << pin;
  199. if (is_on) {
  200. #if defined(CPU_HAS_PIO3)
  201. writel(mask, &at91_port->ifscdr);
  202. #endif
  203. writel(mask, &at91_port->ifer);
  204. } else {
  205. writel(mask, &at91_port->ifdr);
  206. }
  207. }
  208. return 0;
  209. }
  210. #if defined(CPU_HAS_PIO3)
  211. /*
  212. * enable/disable the debounce filter.
  213. */
  214. int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
  215. {
  216. struct at91_port *at91_port = at91_pio_get_port(port);
  217. u32 mask;
  218. if (at91_port && (pin < 32)) {
  219. mask = 1 << pin;
  220. if (is_on) {
  221. writel(mask, &at91_port->ifscer);
  222. writel(div & PIO_SCDR_DIV, &at91_port->scdr);
  223. writel(mask, &at91_port->ifer);
  224. } else {
  225. writel(mask, &at91_port->ifdr);
  226. }
  227. }
  228. return 0;
  229. }
  230. /*
  231. * enable/disable the pull-down.
  232. * If pull-up already enabled while calling the function, we disable it.
  233. */
  234. int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
  235. {
  236. struct at91_port *at91_port = at91_pio_get_port(port);
  237. u32 mask;
  238. if (at91_port && (pin < 32)) {
  239. mask = 1 << pin;
  240. writel(mask, &at91_port->pudr);
  241. if (is_on)
  242. writel(mask, &at91_port->ppder);
  243. else
  244. writel(mask, &at91_port->ppddr);
  245. }
  246. return 0;
  247. }
  248. /*
  249. * disable Schmitt trigger
  250. */
  251. int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin)
  252. {
  253. struct at91_port *at91_port = at91_pio_get_port(port);
  254. u32 mask;
  255. if (at91_port && (pin < 32)) {
  256. mask = 1 << pin;
  257. writel(readl(&at91_port->schmitt) | mask,
  258. &at91_port->schmitt);
  259. }
  260. return 0;
  261. }
  262. #endif
  263. /*
  264. * enable/disable the multi-driver. This is only valid for output and
  265. * allows the output pin to run as an open collector output.
  266. */
  267. int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on)
  268. {
  269. struct at91_port *at91_port = at91_pio_get_port(port);
  270. u32 mask;
  271. if (at91_port && (pin < 32)) {
  272. mask = 1 << pin;
  273. if (is_on)
  274. writel(mask, &at91_port->mder);
  275. else
  276. writel(mask, &at91_port->mddr);
  277. }
  278. return 0;
  279. }
  280. /*
  281. * assuming the pin is muxed as a gpio output, set its value.
  282. */
  283. int at91_set_pio_value(unsigned port, unsigned pin, int value)
  284. {
  285. struct at91_port *at91_port = at91_pio_get_port(port);
  286. u32 mask;
  287. if (at91_port && (pin < 32)) {
  288. mask = 1 << pin;
  289. if (value)
  290. writel(mask, &at91_port->sodr);
  291. else
  292. writel(mask, &at91_port->codr);
  293. }
  294. return 0;
  295. }
  296. /*
  297. * read the pin's value (works even if it's not muxed as a gpio).
  298. */
  299. int at91_get_pio_value(unsigned port, unsigned pin)
  300. {
  301. struct at91_port *at91_port = at91_pio_get_port(port);
  302. u32 pdsr = 0, mask;
  303. if (at91_port && (pin < 32)) {
  304. mask = 1 << pin;
  305. pdsr = readl(&at91_port->pdsr) & mask;
  306. }
  307. return pdsr != 0;
  308. }
  309. /* Common GPIO API */
  310. #define at91_gpio_to_port(gpio) (gpio / 32)
  311. #define at91_gpio_to_pin(gpio) (gpio % 32)
  312. int gpio_request(unsigned gpio, const char *label)
  313. {
  314. return 0;
  315. }
  316. int gpio_free(unsigned gpio)
  317. {
  318. return 0;
  319. }
  320. int gpio_direction_input(unsigned gpio)
  321. {
  322. at91_set_pio_input(at91_gpio_to_port(gpio),
  323. at91_gpio_to_pin(gpio), 0);
  324. return 0;
  325. }
  326. int gpio_direction_output(unsigned gpio, int value)
  327. {
  328. at91_set_pio_output(at91_gpio_to_port(gpio),
  329. at91_gpio_to_pin(gpio), value);
  330. return 0;
  331. }
  332. int gpio_get_value(unsigned gpio)
  333. {
  334. return at91_get_pio_value(at91_gpio_to_port(gpio),
  335. at91_gpio_to_pin(gpio));
  336. }
  337. int gpio_set_value(unsigned gpio, int value)
  338. {
  339. at91_set_pio_value(at91_gpio_to_port(gpio),
  340. at91_gpio_to_pin(gpio), value);
  341. return 0;
  342. }