board.c 2.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123
  1. /*
  2. * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <netdev.h>
  8. #include <zynqpl.h>
  9. #include <asm/arch/hardware.h>
  10. #include <asm/arch/sys_proto.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. #ifdef CONFIG_FPGA
  13. Xilinx_desc fpga;
  14. /* It can be done differently */
  15. Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
  16. Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
  17. Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
  18. Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
  19. Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
  20. #endif
  21. int board_init(void)
  22. {
  23. #ifdef CONFIG_FPGA
  24. u32 idcode;
  25. idcode = zynq_slcr_get_idcode();
  26. switch (idcode) {
  27. case XILINX_ZYNQ_7010:
  28. fpga = fpga010;
  29. break;
  30. case XILINX_ZYNQ_7020:
  31. fpga = fpga020;
  32. break;
  33. case XILINX_ZYNQ_7030:
  34. fpga = fpga030;
  35. break;
  36. case XILINX_ZYNQ_7045:
  37. fpga = fpga045;
  38. break;
  39. case XILINX_ZYNQ_7100:
  40. fpga = fpga100;
  41. break;
  42. }
  43. #endif
  44. icache_enable();
  45. #ifdef CONFIG_FPGA
  46. fpga_init();
  47. fpga_add(fpga_xilinx, &fpga);
  48. #endif
  49. return 0;
  50. }
  51. #ifdef CONFIG_CMD_NET
  52. int board_eth_init(bd_t *bis)
  53. {
  54. u32 ret = 0;
  55. #ifdef CONFIG_XILINX_AXIEMAC
  56. ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
  57. XILINX_AXIDMA_BASEADDR);
  58. #endif
  59. #ifdef CONFIG_XILINX_EMACLITE
  60. u32 txpp = 0;
  61. u32 rxpp = 0;
  62. # ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
  63. txpp = 1;
  64. # endif
  65. # ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
  66. rxpp = 1;
  67. # endif
  68. ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
  69. txpp, rxpp);
  70. #endif
  71. #if defined(CONFIG_ZYNQ_GEM)
  72. # if defined(CONFIG_ZYNQ_GEM0)
  73. ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
  74. CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
  75. # endif
  76. # if defined(CONFIG_ZYNQ_GEM1)
  77. ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
  78. CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
  79. # endif
  80. #endif
  81. return ret;
  82. }
  83. #endif
  84. #ifdef CONFIG_CMD_MMC
  85. int board_mmc_init(bd_t *bd)
  86. {
  87. int ret = 0;
  88. #if defined(CONFIG_ZYNQ_SDHCI)
  89. # if defined(CONFIG_ZYNQ_SDHCI0)
  90. ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
  91. # endif
  92. # if defined(CONFIG_ZYNQ_SDHCI1)
  93. ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
  94. # endif
  95. #endif
  96. return ret;
  97. }
  98. #endif
  99. int dram_init(void)
  100. {
  101. gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  102. zynq_ddrc_init();
  103. return 0;
  104. }