board.c 8.9 KB

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  1. /*
  2. * Board functions for TI AM335X based rut board
  3. * (C) Copyright 2013 Siemens Schweiz AG
  4. * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
  5. *
  6. * Based on:
  7. * u-boot:/board/ti/am335x/board.c
  8. *
  9. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  10. *
  11. * SPDX-License-Identifier: GPL-2.0+
  12. */
  13. #include <common.h>
  14. #include <errno.h>
  15. #include <spi.h>
  16. #include <spl.h>
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/hardware.h>
  19. #include <asm/arch/omap.h>
  20. #include <asm/arch/ddr_defs.h>
  21. #include <asm/arch/clock.h>
  22. #include <asm/arch/gpio.h>
  23. #include <asm/arch/mmc_host_def.h>
  24. #include <asm/arch/sys_proto.h>
  25. #include <asm/io.h>
  26. #include <asm/emif.h>
  27. #include <asm/gpio.h>
  28. #include <i2c.h>
  29. #include <miiphy.h>
  30. #include <cpsw.h>
  31. #include <video.h>
  32. #include <watchdog.h>
  33. #include "board.h"
  34. #include "../common/factoryset.h"
  35. #include "../../../drivers/video/da8xx-fb.h"
  36. DECLARE_GLOBAL_DATA_PTR;
  37. /*
  38. * Read header information from EEPROM into global structure.
  39. */
  40. static int read_eeprom(void)
  41. {
  42. return 0;
  43. }
  44. #ifdef CONFIG_SPL_BUILD
  45. static void board_init_ddr(void)
  46. {
  47. struct emif_regs rut_ddr3_emif_reg_data = {
  48. .sdram_config = 0x61C04AB2,
  49. .sdram_tim1 = 0x0888A39B,
  50. .sdram_tim2 = 0x26337FDA,
  51. .sdram_tim3 = 0x501F830F,
  52. .emif_ddr_phy_ctlr_1 = 0x6,
  53. .zq_config = 0x50074BE4,
  54. .ref_ctrl = 0x93B,
  55. };
  56. struct ddr_data rut_ddr3_data = {
  57. .datardsratio0 = 0x3b,
  58. .datawdsratio0 = 0x85,
  59. .datafwsratio0 = 0x100,
  60. .datawrsratio0 = 0xc1,
  61. .datauserank0delay = 1,
  62. .datadldiff0 = PHY_DLL_LOCK_DIFF,
  63. };
  64. struct cmd_control rut_ddr3_cmd_ctrl_data = {
  65. .cmd0csratio = 0x40,
  66. .cmd0dldiff = 0,
  67. .cmd0iclkout = 1,
  68. .cmd1csratio = 0x40,
  69. .cmd1dldiff = 0,
  70. .cmd1iclkout = 1,
  71. .cmd2csratio = 0x40,
  72. .cmd2dldiff = 0,
  73. .cmd2iclkout = 1,
  74. };
  75. config_ddr(DDR_PLL_FREQ, RUT_IOCTRL_VAL, &rut_ddr3_data,
  76. &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
  77. }
  78. static void spl_siemens_board_init(void)
  79. {
  80. return;
  81. }
  82. #endif /* if def CONFIG_SPL_BUILD */
  83. #if defined(CONFIG_DRIVER_TI_CPSW)
  84. static void cpsw_control(int enabled)
  85. {
  86. /* VTP can be added here */
  87. return;
  88. }
  89. static struct cpsw_slave_data cpsw_slaves[] = {
  90. {
  91. .slave_reg_ofs = 0x208,
  92. .sliver_reg_ofs = 0xd80,
  93. .phy_id = 1,
  94. .phy_if = PHY_INTERFACE_MODE_RMII,
  95. },
  96. {
  97. .slave_reg_ofs = 0x308,
  98. .sliver_reg_ofs = 0xdc0,
  99. .phy_id = 0,
  100. .phy_if = PHY_INTERFACE_MODE_RMII,
  101. },
  102. };
  103. static struct cpsw_platform_data cpsw_data = {
  104. .mdio_base = CPSW_MDIO_BASE,
  105. .cpsw_base = CPSW_BASE,
  106. .mdio_div = 0xff,
  107. .channels = 8,
  108. .cpdma_reg_ofs = 0x800,
  109. .slaves = 1,
  110. .slave_data = cpsw_slaves,
  111. .ale_reg_ofs = 0xd00,
  112. .ale_entries = 1024,
  113. .host_port_reg_ofs = 0x108,
  114. .hw_stats_reg_ofs = 0x900,
  115. .bd_ram_ofs = 0x2000,
  116. .mac_control = (1 << 5),
  117. .control = cpsw_control,
  118. .host_port_num = 0,
  119. .version = CPSW_CTRL_VERSION_2,
  120. };
  121. #if defined(CONFIG_DRIVER_TI_CPSW) || \
  122. (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
  123. int board_eth_init(bd_t *bis)
  124. {
  125. struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  126. int n = 0;
  127. int rv;
  128. #ifndef CONFIG_SPL_BUILD
  129. factoryset_setenv();
  130. #endif
  131. /* Set rgmii mode and enable rmii clock to be sourced from chip */
  132. writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
  133. rv = cpsw_register(&cpsw_data);
  134. if (rv < 0)
  135. printf("Error %d registering CPSW switch\n", rv);
  136. else
  137. n += rv;
  138. return n;
  139. }
  140. #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
  141. #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
  142. #if defined(CONFIG_HW_WATCHDOG)
  143. static bool hw_watchdog_init_done;
  144. static int hw_watchdog_trigger_level;
  145. void hw_watchdog_reset(void)
  146. {
  147. if (!hw_watchdog_init_done)
  148. return;
  149. hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1;
  150. gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
  151. }
  152. void hw_watchdog_init(void)
  153. {
  154. gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger");
  155. gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
  156. hw_watchdog_reset();
  157. hw_watchdog_init_done = 1;
  158. }
  159. #endif /* defined(CONFIG_HW_WATCHDOG) */
  160. #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
  161. static struct da8xx_panel lcd_panels[] = {
  162. /* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */
  163. [0] = {
  164. .name = "KWH043MC17-F01",
  165. .width = 480,
  166. .height = 800,
  167. .hfp = 50, /* no spec, "don't care" values */
  168. .hbp = 50,
  169. .hsw = 50,
  170. .vfp = 50,
  171. .vbp = 50,
  172. .vsw = 50,
  173. .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
  174. .invert_pxl_clk = 1,
  175. },
  176. /* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */
  177. [1] = {
  178. .name = "KWH043ST20-F01",
  179. .width = 480,
  180. .height = 800,
  181. .hfp = 50, /* no spec, "don't care" values */
  182. .hbp = 50,
  183. .hsw = 50,
  184. .vfp = 50,
  185. .vbp = 50,
  186. .vsw = 50,
  187. .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
  188. .invert_pxl_clk = 1,
  189. },
  190. /* Multi-Inno, 4.3", 480x800, MI0430VT-1 */
  191. [2] = {
  192. .name = "MI0430VT-1",
  193. .width = 480,
  194. .height = 800,
  195. .hfp = 50, /* no spec, "don't care" values */
  196. .hbp = 50,
  197. .hsw = 50,
  198. .vfp = 50,
  199. .vbp = 50,
  200. .vsw = 50,
  201. .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
  202. .invert_pxl_clk = 1,
  203. },
  204. };
  205. static const struct display_panel disp_panels[] = {
  206. [0] = {
  207. WVGA,
  208. 16, /* RGB 888 */
  209. 16,
  210. COLOR_ACTIVE,
  211. },
  212. [1] = {
  213. WVGA,
  214. 16, /* RGB 888 */
  215. 16,
  216. COLOR_ACTIVE,
  217. },
  218. [2] = {
  219. WVGA,
  220. 24, /* RGB 888 */
  221. 16,
  222. COLOR_ACTIVE,
  223. },
  224. };
  225. static const struct lcd_ctrl_config lcd_cfgs[] = {
  226. [0] = {
  227. &disp_panels[0],
  228. .ac_bias = 255,
  229. .ac_bias_intrpt = 0,
  230. .dma_burst_sz = 16,
  231. .bpp = 16,
  232. .fdd = 0x80,
  233. .tft_alt_mode = 0,
  234. .stn_565_mode = 0,
  235. .mono_8bit_mode = 0,
  236. .invert_line_clock = 1,
  237. .invert_frm_clock = 1,
  238. .sync_edge = 0,
  239. .sync_ctrl = 1,
  240. .raster_order = 0,
  241. },
  242. [1] = {
  243. &disp_panels[1],
  244. .ac_bias = 255,
  245. .ac_bias_intrpt = 0,
  246. .dma_burst_sz = 16,
  247. .bpp = 16,
  248. .fdd = 0x80,
  249. .tft_alt_mode = 0,
  250. .stn_565_mode = 0,
  251. .mono_8bit_mode = 0,
  252. .invert_line_clock = 1,
  253. .invert_frm_clock = 1,
  254. .sync_edge = 0,
  255. .sync_ctrl = 1,
  256. .raster_order = 0,
  257. },
  258. [2] = {
  259. &disp_panels[2],
  260. .ac_bias = 255,
  261. .ac_bias_intrpt = 0,
  262. .dma_burst_sz = 16,
  263. .bpp = 24,
  264. .fdd = 0x80,
  265. .tft_alt_mode = 0,
  266. .stn_565_mode = 0,
  267. .mono_8bit_mode = 0,
  268. .invert_line_clock = 1,
  269. .invert_frm_clock = 1,
  270. .sync_edge = 0,
  271. .sync_ctrl = 1,
  272. .raster_order = 0,
  273. },
  274. };
  275. /* no console on this board */
  276. int board_cfb_skip(void)
  277. {
  278. return 1;
  279. }
  280. #define PLL_GET_M(v) ((v >> 8) & 0x7ff)
  281. #define PLL_GET_N(v) (v & 0x7f)
  282. static struct dpll_regs dpll_lcd_regs = {
  283. .cm_clkmode_dpll = CM_WKUP + 0x98,
  284. .cm_idlest_dpll = CM_WKUP + 0x48,
  285. .cm_clksel_dpll = CM_WKUP + 0x54,
  286. };
  287. static int get_clk(struct dpll_regs *dpll_regs)
  288. {
  289. unsigned int val;
  290. unsigned int m, n;
  291. int f = 0;
  292. val = readl(dpll_regs->cm_clksel_dpll);
  293. m = PLL_GET_M(val);
  294. n = PLL_GET_N(val);
  295. f = (m * V_OSCK) / n;
  296. return f;
  297. };
  298. int clk_get(int clk)
  299. {
  300. return get_clk(&dpll_lcd_regs);
  301. };
  302. static int conf_disp_pll(int m, int n)
  303. {
  304. struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
  305. struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
  306. struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
  307. #if defined(DISPL_PLL_SPREAD_SPECTRUM)
  308. struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
  309. #endif
  310. u32 *const clk_domains[] = {
  311. &cmper->lcdclkctrl,
  312. 0
  313. };
  314. u32 *const clk_modules_explicit_en[] = {
  315. &cmper->lcdclkctrl,
  316. &cmper->lcdcclkstctrl,
  317. &cmper->spi1clkctrl,
  318. 0
  319. };
  320. do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
  321. /* 0x44e0_0500 write lcdc pixel clock mux Linux hat hier 0 */
  322. writel(0x0, &cmdpll->clklcdcpixelclk);
  323. do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
  324. #if defined(DISPL_PLL_SPREAD_SPECTRUM)
  325. writel(0x64, &cmwkup->resv6[3]); /* 0x50 */
  326. writel(0x800, &cmwkup->resv6[2]); /* 0x4c */
  327. writel(readl(&cmwkup->clkmoddplldisp) | (1 << 12),
  328. &cmwkup->clkmoddplldisp); /* 0x98 */
  329. #endif
  330. return 0;
  331. }
  332. static int set_gpio(int gpio, int state)
  333. {
  334. gpio_request(gpio, "temp");
  335. gpio_direction_output(gpio, state);
  336. gpio_set_value(gpio, state);
  337. gpio_free(gpio);
  338. return 0;
  339. }
  340. static int enable_lcd(void)
  341. {
  342. unsigned char buf[1];
  343. set_gpio(BOARD_LCD_RESET, 1);
  344. /* spi lcd init */
  345. kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_3);
  346. /* backlight on */
  347. buf[0] = 0xf;
  348. i2c_write(0x24, 0x7, 1, buf, 1);
  349. buf[0] = 0x3f;
  350. i2c_write(0x24, 0x8, 1, buf, 1);
  351. return 0;
  352. }
  353. int arch_early_init_r(void)
  354. {
  355. enable_lcd();
  356. return 0;
  357. }
  358. static int board_video_init(void)
  359. {
  360. int i;
  361. int anzdisp = ARRAY_SIZE(lcd_panels);
  362. int display = 1;
  363. for (i = 0; i < anzdisp; i++) {
  364. if (strncmp((const char *)factory_dat.disp_name,
  365. lcd_panels[i].name,
  366. strlen((const char *)factory_dat.disp_name)) == 0) {
  367. printf("DISPLAY: %s\n", factory_dat.disp_name);
  368. break;
  369. }
  370. }
  371. if (i == anzdisp) {
  372. i = 1;
  373. printf("%s: %s not found, using default %s\n", __func__,
  374. factory_dat.disp_name, lcd_panels[i].name);
  375. }
  376. conf_disp_pll(25, 2);
  377. da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display],
  378. lcd_cfgs[display].bpp);
  379. return 0;
  380. }
  381. #endif /* ifdef CONFIG_VIDEO */
  382. #include "../common/board.c"