board.c 9.0 KB

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  1. /*
  2. * Board functions for TI AM335X based pxm2 board
  3. * (C) Copyright 2013 Siemens Schweiz AG
  4. * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
  5. *
  6. * Based on:
  7. * u-boot:/board/ti/am335x/board.c
  8. *
  9. * Board functions for TI AM335X based boards
  10. *
  11. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  12. *
  13. * SPDX-License-Identifier: GPL-2.0+
  14. */
  15. #include <common.h>
  16. #include <errno.h>
  17. #include <spl.h>
  18. #include <asm/arch/cpu.h>
  19. #include <asm/arch/hardware.h>
  20. #include <asm/arch/omap.h>
  21. #include <asm/arch/ddr_defs.h>
  22. #include <asm/arch/clock.h>
  23. #include <asm/arch/gpio.h>
  24. #include <asm/arch/mmc_host_def.h>
  25. #include <asm/arch/sys_proto.h>
  26. #include "../../../drivers/video/da8xx-fb.h"
  27. #include <asm/io.h>
  28. #include <asm/emif.h>
  29. #include <asm/gpio.h>
  30. #include <i2c.h>
  31. #include <miiphy.h>
  32. #include <cpsw.h>
  33. #include <watchdog.h>
  34. #include "board.h"
  35. #include "../common/factoryset.h"
  36. #include "pmic.h"
  37. #include <nand.h>
  38. #include <bmp_layout.h>
  39. DECLARE_GLOBAL_DATA_PTR;
  40. #ifdef CONFIG_SPL_BUILD
  41. static void board_init_ddr(void)
  42. {
  43. struct emif_regs pxm2_ddr3_emif_reg_data = {
  44. .sdram_config = 0x41805332,
  45. .sdram_tim1 = 0x666b3c9,
  46. .sdram_tim2 = 0x243631ca,
  47. .sdram_tim3 = 0x33f,
  48. .emif_ddr_phy_ctlr_1 = 0x100005,
  49. .zq_config = 0,
  50. .ref_ctrl = 0x81a,
  51. };
  52. struct ddr_data pxm2_ddr3_data = {
  53. .datardsratio0 = 0x81204812,
  54. .datawdsratio0 = 0,
  55. .datafwsratio0 = 0x8020080,
  56. .datawrsratio0 = 0x4010040,
  57. .datauserank0delay = 1,
  58. .datadldiff0 = PHY_DLL_LOCK_DIFF,
  59. };
  60. struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
  61. .cmd0csratio = 0x80,
  62. .cmd0dldiff = 0,
  63. .cmd0iclkout = 0,
  64. .cmd1csratio = 0x80,
  65. .cmd1dldiff = 0,
  66. .cmd1iclkout = 0,
  67. .cmd2csratio = 0x80,
  68. .cmd2dldiff = 0,
  69. .cmd2iclkout = 0,
  70. };
  71. config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &pxm2_ddr3_data,
  72. &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
  73. }
  74. /*
  75. * voltage switching for MPU frequency switching.
  76. * @module = mpu - 0, core - 1
  77. * @vddx_op_vol_sel = vdd voltage to set
  78. */
  79. #define MPU 0
  80. #define CORE 1
  81. int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
  82. {
  83. uchar buf[4];
  84. unsigned int reg_offset;
  85. if (module == MPU)
  86. reg_offset = PMIC_VDD1_OP_REG;
  87. else
  88. reg_offset = PMIC_VDD2_OP_REG;
  89. /* Select VDDx OP */
  90. if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
  91. return 1;
  92. buf[0] &= ~PMIC_OP_REG_CMD_MASK;
  93. if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
  94. return 1;
  95. /* Configure VDDx OP Voltage */
  96. if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
  97. return 1;
  98. buf[0] &= ~PMIC_OP_REG_SEL_MASK;
  99. buf[0] |= vddx_op_vol_sel;
  100. if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
  101. return 1;
  102. if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
  103. return 1;
  104. if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel)
  105. return 1;
  106. return 0;
  107. }
  108. #define OSC (V_OSCK/1000000)
  109. const struct dpll_params dpll_mpu_pxm2 = {
  110. 720, OSC-1, 1, -1, -1, -1, -1};
  111. void spl_siemens_board_init(void)
  112. {
  113. uchar buf[4];
  114. /*
  115. * pxm2 PMIC code. All boards currently want an MPU voltage
  116. * of 1.2625V and CORE voltage of 1.1375V to operate at
  117. * 720MHz.
  118. */
  119. if (i2c_probe(PMIC_CTRL_I2C_ADDR))
  120. return;
  121. /* VDD1/2 voltage selection register access by control i/f */
  122. if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
  123. return;
  124. buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
  125. if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
  126. return;
  127. /* Frequency switching for OPP 120 */
  128. if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) ||
  129. voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) {
  130. printf("voltage update failed\n");
  131. }
  132. }
  133. #endif /* if def CONFIG_SPL_BUILD */
  134. int read_eeprom(void)
  135. {
  136. /* nothing ToDo here for this board */
  137. return 0;
  138. }
  139. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  140. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  141. static void cpsw_control(int enabled)
  142. {
  143. /* VTP can be added here */
  144. return;
  145. }
  146. static struct cpsw_slave_data cpsw_slaves[] = {
  147. {
  148. .slave_reg_ofs = 0x208,
  149. .sliver_reg_ofs = 0xd80,
  150. .phy_id = 0,
  151. .phy_if = PHY_INTERFACE_MODE_RMII,
  152. },
  153. {
  154. .slave_reg_ofs = 0x308,
  155. .sliver_reg_ofs = 0xdc0,
  156. .phy_id = 1,
  157. .phy_if = PHY_INTERFACE_MODE_RMII,
  158. },
  159. };
  160. static struct cpsw_platform_data cpsw_data = {
  161. .mdio_base = CPSW_MDIO_BASE,
  162. .cpsw_base = CPSW_BASE,
  163. .mdio_div = 0xff,
  164. .channels = 4,
  165. .cpdma_reg_ofs = 0x800,
  166. .slaves = 1,
  167. .slave_data = cpsw_slaves,
  168. .ale_reg_ofs = 0xd00,
  169. .ale_entries = 1024,
  170. .host_port_reg_ofs = 0x108,
  171. .hw_stats_reg_ofs = 0x900,
  172. .bd_ram_ofs = 0x2000,
  173. .mac_control = (1 << 5),
  174. .control = cpsw_control,
  175. .host_port_num = 0,
  176. .version = CPSW_CTRL_VERSION_2,
  177. };
  178. #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
  179. #if defined(CONFIG_DRIVER_TI_CPSW) || \
  180. (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
  181. int board_eth_init(bd_t *bis)
  182. {
  183. int n = 0;
  184. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  185. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  186. struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  187. #ifdef CONFIG_FACTORYSET
  188. int rv;
  189. if (!is_valid_ether_addr(factory_dat.mac))
  190. printf("Error: no valid mac address\n");
  191. else
  192. eth_setenv_enetaddr("ethaddr", factory_dat.mac);
  193. #endif /* #ifdef CONFIG_FACTORYSET */
  194. /* Set rgmii mode and enable rmii clock to be sourced from chip */
  195. writel(RGMII_MODE_ENABLE , &cdev->miisel);
  196. rv = cpsw_register(&cpsw_data);
  197. if (rv < 0)
  198. printf("Error %d registering CPSW switch\n", rv);
  199. else
  200. n += rv;
  201. #endif
  202. return n;
  203. }
  204. #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
  205. #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
  206. static struct da8xx_panel lcd_panels[] = {
  207. /* AUO G156XW01 V1 */
  208. [0] = {
  209. .name = "AUO_G156XW01_V1",
  210. .width = 1376,
  211. .height = 768,
  212. .hfp = 14,
  213. .hbp = 64,
  214. .hsw = 56,
  215. .vfp = 1,
  216. .vbp = 28,
  217. .vsw = 3,
  218. .pxl_clk = 60000000,
  219. .invert_pxl_clk = 0,
  220. },
  221. /* AUO B101EVN06 V0 */
  222. [1] = {
  223. .name = "AUO_B101EVN06_V0",
  224. .width = 1280,
  225. .height = 800,
  226. .hfp = 52,
  227. .hbp = 84,
  228. .hsw = 36,
  229. .vfp = 3,
  230. .vbp = 14,
  231. .vsw = 6,
  232. .pxl_clk = 60000000,
  233. .invert_pxl_clk = 0,
  234. },
  235. /*
  236. * Settings from factoryset
  237. * stored in EEPROM
  238. */
  239. [2] = {
  240. .name = "factoryset",
  241. .width = 0,
  242. .height = 0,
  243. .hfp = 0,
  244. .hbp = 0,
  245. .hsw = 0,
  246. .vfp = 0,
  247. .vbp = 0,
  248. .vsw = 0,
  249. .pxl_clk = 60000000,
  250. .invert_pxl_clk = 0,
  251. },
  252. };
  253. static const struct display_panel disp_panel = {
  254. WVGA,
  255. 32,
  256. 16,
  257. COLOR_ACTIVE,
  258. };
  259. static const struct lcd_ctrl_config lcd_cfg = {
  260. &disp_panel,
  261. .ac_bias = 255,
  262. .ac_bias_intrpt = 0,
  263. .dma_burst_sz = 16,
  264. .bpp = 32,
  265. .fdd = 0x80,
  266. .tft_alt_mode = 0,
  267. .stn_565_mode = 0,
  268. .mono_8bit_mode = 0,
  269. .invert_line_clock = 1,
  270. .invert_frm_clock = 1,
  271. .sync_edge = 0,
  272. .sync_ctrl = 1,
  273. .raster_order = 0,
  274. };
  275. static int set_gpio(int gpio, int state)
  276. {
  277. gpio_request(gpio, "temp");
  278. gpio_direction_output(gpio, state);
  279. gpio_set_value(gpio, state);
  280. gpio_free(gpio);
  281. return 0;
  282. }
  283. static int enable_backlight(void)
  284. {
  285. set_gpio(BOARD_LCD_POWER, 1);
  286. set_gpio(BOARD_BACK_LIGHT, 1);
  287. set_gpio(BOARD_TOUCH_POWER, 1);
  288. return 0;
  289. }
  290. static int enable_pwm(void)
  291. {
  292. struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE;
  293. struct pwmss_ecap_regs *ecap;
  294. int ticks = PWM_TICKS;
  295. int duty = PWM_DUTY;
  296. ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE;
  297. /* enable clock */
  298. setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN);
  299. /* TimeStam Counter register */
  300. writel(0xdb9, &ecap->tsctr);
  301. /* config period */
  302. writel(ticks - 1, &ecap->cap3);
  303. writel(ticks - 1, &ecap->cap1);
  304. setbits_le16(&ecap->ecctl2,
  305. (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0));
  306. /* config duty */
  307. writel(duty, &ecap->cap2);
  308. writel(duty, &ecap->cap4);
  309. /* start */
  310. setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN);
  311. return 0;
  312. }
  313. static struct dpll_regs dpll_lcd_regs = {
  314. .cm_clkmode_dpll = CM_WKUP + 0x98,
  315. .cm_idlest_dpll = CM_WKUP + 0x48,
  316. .cm_clksel_dpll = CM_WKUP + 0x54,
  317. };
  318. /* no console on this board */
  319. int board_cfb_skip(void)
  320. {
  321. return 1;
  322. }
  323. #define PLL_GET_M(v) ((v >> 8) & 0x7ff)
  324. #define PLL_GET_N(v) (v & 0x7f)
  325. static int get_clk(struct dpll_regs *dpll_regs)
  326. {
  327. unsigned int val;
  328. unsigned int m, n;
  329. int f = 0;
  330. val = readl(dpll_regs->cm_clksel_dpll);
  331. m = PLL_GET_M(val);
  332. n = PLL_GET_N(val);
  333. f = (m * V_OSCK) / n;
  334. return f;
  335. };
  336. int clk_get(int clk)
  337. {
  338. return get_clk(&dpll_lcd_regs);
  339. };
  340. static int conf_disp_pll(int m, int n)
  341. {
  342. struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
  343. struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
  344. struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
  345. u32 *const clk_domains[] = {
  346. &cmper->lcdclkctrl,
  347. 0
  348. };
  349. u32 *const clk_modules_explicit_en[] = {
  350. &cmper->lcdclkctrl,
  351. &cmper->lcdcclkstctrl,
  352. &cmper->epwmss0clkctrl,
  353. 0
  354. };
  355. do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
  356. writel(0x0, &cmdpll->clklcdcpixelclk);
  357. do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
  358. return 0;
  359. }
  360. static int board_video_init(void)
  361. {
  362. /* set 300 MHz */
  363. conf_disp_pll(25, 2);
  364. if (factory_dat.pxm50)
  365. da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp);
  366. else
  367. da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp);
  368. enable_pwm();
  369. enable_backlight();
  370. return 0;
  371. }
  372. #endif
  373. #include "../common/board.c"