nitrogen6x.c 22 KB

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  1. /*
  2. * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
  3. * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <malloc.h>
  14. #include <asm/arch/mx6-pins.h>
  15. #include <asm/errno.h>
  16. #include <asm/gpio.h>
  17. #include <asm/imx-common/iomux-v3.h>
  18. #include <asm/imx-common/mxc_i2c.h>
  19. #include <asm/imx-common/boot_mode.h>
  20. #include <mmc.h>
  21. #include <fsl_esdhc.h>
  22. #include <micrel.h>
  23. #include <miiphy.h>
  24. #include <netdev.h>
  25. #include <linux/fb.h>
  26. #include <ipu_pixfmt.h>
  27. #include <asm/arch/crm_regs.h>
  28. #include <asm/arch/mxc_hdmi.h>
  29. #include <i2c.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  32. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  33. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  34. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  35. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  36. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  37. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  38. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  39. #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  40. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  41. #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  42. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  43. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  44. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  45. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  46. #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
  47. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  48. PAD_CTL_SRE_SLOW)
  49. #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
  50. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  51. PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  52. #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  53. int dram_init(void)
  54. {
  55. gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
  56. return 0;
  57. }
  58. iomux_v3_cfg_t const uart1_pads[] = {
  59. MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  60. MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  61. };
  62. iomux_v3_cfg_t const uart2_pads[] = {
  63. MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  64. MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  65. };
  66. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  67. /* I2C1, SGTL5000 */
  68. struct i2c_pads_info i2c_pad_info0 = {
  69. .scl = {
  70. .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
  71. .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC,
  72. .gp = IMX_GPIO_NR(3, 21)
  73. },
  74. .sda = {
  75. .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
  76. .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC,
  77. .gp = IMX_GPIO_NR(3, 28)
  78. }
  79. };
  80. /* I2C2 Camera, MIPI */
  81. struct i2c_pads_info i2c_pad_info1 = {
  82. .scl = {
  83. .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
  84. .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC,
  85. .gp = IMX_GPIO_NR(4, 12)
  86. },
  87. .sda = {
  88. .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
  89. .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
  90. .gp = IMX_GPIO_NR(4, 13)
  91. }
  92. };
  93. /* I2C3, J15 - RGB connector */
  94. struct i2c_pads_info i2c_pad_info2 = {
  95. .scl = {
  96. .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
  97. .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC,
  98. .gp = IMX_GPIO_NR(1, 5)
  99. },
  100. .sda = {
  101. .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
  102. .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
  103. .gp = IMX_GPIO_NR(7, 11)
  104. }
  105. };
  106. iomux_v3_cfg_t const usdhc3_pads[] = {
  107. MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  108. MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  109. MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  110. MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  111. MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  112. MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  113. MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  114. };
  115. iomux_v3_cfg_t const usdhc4_pads[] = {
  116. MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  117. MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  118. MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  119. MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  120. MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  121. MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  122. MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  123. };
  124. iomux_v3_cfg_t const enet_pads1[] = {
  125. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  126. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  127. MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  128. MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  129. MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  130. MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  131. MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  132. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  133. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  134. /* pin 35 - 1 (PHY_AD2) on reset */
  135. MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL),
  136. /* pin 32 - 1 - (MODE0) all */
  137. MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
  138. /* pin 31 - 1 - (MODE1) all */
  139. MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
  140. /* pin 28 - 1 - (MODE2) all */
  141. MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  142. /* pin 27 - 1 - (MODE3) all */
  143. MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  144. /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
  145. MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
  146. /* pin 42 PHY nRST */
  147. MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
  148. MX6_PAD_ENET_RXD0__GPIO_1_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
  149. };
  150. iomux_v3_cfg_t const enet_pads2[] = {
  151. MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  152. MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  153. MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  154. MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  155. MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  156. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  157. };
  158. /* wl1271 pads on nitrogen6x */
  159. iomux_v3_cfg_t const wl12xx_pads[] = {
  160. (MX6_PAD_NANDF_CS1__GPIO_6_14 & ~MUX_PAD_CTRL_MASK)
  161. | MUX_PAD_CTRL(WEAK_PULLDOWN),
  162. (MX6_PAD_NANDF_CS2__GPIO_6_15 & ~MUX_PAD_CTRL_MASK)
  163. | MUX_PAD_CTRL(OUTPUT_40OHM),
  164. (MX6_PAD_NANDF_CS3__GPIO_6_16 & ~MUX_PAD_CTRL_MASK)
  165. | MUX_PAD_CTRL(OUTPUT_40OHM),
  166. };
  167. #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
  168. #define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15)
  169. #define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16)
  170. /* Button assignments for J14 */
  171. static iomux_v3_cfg_t const button_pads[] = {
  172. /* Menu */
  173. MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  174. /* Back */
  175. MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  176. /* Labelled Search (mapped to Power under Android) */
  177. MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  178. /* Home */
  179. MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  180. /* Volume Down */
  181. MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  182. /* Volume Up */
  183. MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  184. };
  185. static void setup_iomux_enet(void)
  186. {
  187. gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
  188. gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
  189. gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
  190. gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
  191. gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
  192. gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
  193. gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
  194. imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
  195. gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
  196. /* Need delay 10ms according to KSZ9021 spec */
  197. udelay(1000 * 10);
  198. gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
  199. gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
  200. imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
  201. }
  202. iomux_v3_cfg_t const usb_pads[] = {
  203. MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
  204. };
  205. static void setup_iomux_uart(void)
  206. {
  207. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  208. imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  209. }
  210. #ifdef CONFIG_USB_EHCI_MX6
  211. int board_ehci_hcd_init(int port)
  212. {
  213. imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
  214. /* Reset USB hub */
  215. gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
  216. mdelay(2);
  217. gpio_set_value(IMX_GPIO_NR(7, 12), 1);
  218. return 0;
  219. }
  220. #endif
  221. #ifdef CONFIG_FSL_ESDHC
  222. struct fsl_esdhc_cfg usdhc_cfg[2] = {
  223. {USDHC3_BASE_ADDR},
  224. {USDHC4_BASE_ADDR},
  225. };
  226. int board_mmc_getcd(struct mmc *mmc)
  227. {
  228. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  229. int ret;
  230. if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
  231. gpio_direction_input(IMX_GPIO_NR(7, 0));
  232. ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
  233. } else {
  234. gpio_direction_input(IMX_GPIO_NR(2, 6));
  235. ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
  236. }
  237. return ret;
  238. }
  239. int board_mmc_init(bd_t *bis)
  240. {
  241. s32 status = 0;
  242. u32 index = 0;
  243. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  244. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  245. usdhc_cfg[0].max_bus_width = 4;
  246. usdhc_cfg[1].max_bus_width = 4;
  247. for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
  248. switch (index) {
  249. case 0:
  250. imx_iomux_v3_setup_multiple_pads(
  251. usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  252. break;
  253. case 1:
  254. imx_iomux_v3_setup_multiple_pads(
  255. usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  256. break;
  257. default:
  258. printf("Warning: you configured more USDHC controllers"
  259. "(%d) then supported by the board (%d)\n",
  260. index + 1, CONFIG_SYS_FSL_USDHC_NUM);
  261. return status;
  262. }
  263. status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  264. }
  265. return status;
  266. }
  267. #endif
  268. #ifdef CONFIG_MXC_SPI
  269. iomux_v3_cfg_t const ecspi1_pads[] = {
  270. /* SS1 */
  271. MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
  272. MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  273. MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  274. MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  275. };
  276. void setup_spi(void)
  277. {
  278. imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
  279. ARRAY_SIZE(ecspi1_pads));
  280. }
  281. #endif
  282. int board_phy_config(struct phy_device *phydev)
  283. {
  284. /* min rx data delay */
  285. ksz9021_phy_extended_write(phydev,
  286. MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
  287. /* min tx data delay */
  288. ksz9021_phy_extended_write(phydev,
  289. MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
  290. /* max rx/tx clock delay, min rx/tx control */
  291. ksz9021_phy_extended_write(phydev,
  292. MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
  293. if (phydev->drv->config)
  294. phydev->drv->config(phydev);
  295. return 0;
  296. }
  297. int board_eth_init(bd_t *bis)
  298. {
  299. uint32_t base = IMX_FEC_BASE;
  300. struct mii_dev *bus = NULL;
  301. struct phy_device *phydev = NULL;
  302. int ret;
  303. setup_iomux_enet();
  304. #ifdef CONFIG_FEC_MXC
  305. bus = fec_get_miibus(base, -1);
  306. if (!bus)
  307. return 0;
  308. /* scan phy 4,5,6,7 */
  309. phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
  310. if (!phydev) {
  311. free(bus);
  312. return 0;
  313. }
  314. printf("using phy at %d\n", phydev->addr);
  315. ret = fec_probe(bis, -1, base, bus, phydev);
  316. if (ret) {
  317. printf("FEC MXC: %s:failed\n", __func__);
  318. free(phydev);
  319. free(bus);
  320. }
  321. #endif
  322. return 0;
  323. }
  324. static void setup_buttons(void)
  325. {
  326. imx_iomux_v3_setup_multiple_pads(button_pads,
  327. ARRAY_SIZE(button_pads));
  328. }
  329. #ifdef CONFIG_CMD_SATA
  330. int setup_sata(void)
  331. {
  332. struct iomuxc_base_regs *const iomuxc_regs
  333. = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
  334. int ret = enable_sata_clock();
  335. if (ret)
  336. return ret;
  337. clrsetbits_le32(&iomuxc_regs->gpr[13],
  338. IOMUXC_GPR13_SATA_MASK,
  339. IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
  340. |IOMUXC_GPR13_SATA_PHY_7_SATA2M
  341. |IOMUXC_GPR13_SATA_SPEED_3G
  342. |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
  343. |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
  344. |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
  345. |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
  346. |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
  347. |IOMUXC_GPR13_SATA_PHY_1_SLOW);
  348. return 0;
  349. }
  350. #endif
  351. #if defined(CONFIG_VIDEO_IPUV3)
  352. static iomux_v3_cfg_t const backlight_pads[] = {
  353. /* Backlight on RGB connector: J15 */
  354. MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
  355. #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
  356. /* Backlight on LVDS connector: J6 */
  357. MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
  358. #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
  359. };
  360. static iomux_v3_cfg_t const rgb_pads[] = {
  361. MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
  362. MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
  363. MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
  364. MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
  365. MX6_PAD_DI0_PIN4__GPIO_4_20,
  366. MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
  367. MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
  368. MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
  369. MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
  370. MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
  371. MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
  372. MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
  373. MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
  374. MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
  375. MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
  376. MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
  377. MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
  378. MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
  379. MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
  380. MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
  381. MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
  382. MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
  383. MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
  384. MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
  385. MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
  386. MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
  387. MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
  388. MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
  389. MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
  390. };
  391. struct display_info_t {
  392. int bus;
  393. int addr;
  394. int pixfmt;
  395. int (*detect)(struct display_info_t const *dev);
  396. void (*enable)(struct display_info_t const *dev);
  397. struct fb_videomode mode;
  398. };
  399. static int detect_hdmi(struct display_info_t const *dev)
  400. {
  401. struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
  402. return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
  403. }
  404. static void do_enable_hdmi(struct display_info_t const *dev)
  405. {
  406. imx_enable_hdmi_phy();
  407. }
  408. static int detect_i2c(struct display_info_t const *dev)
  409. {
  410. return ((0 == i2c_set_bus_num(dev->bus))
  411. &&
  412. (0 == i2c_probe(dev->addr)));
  413. }
  414. static void enable_lvds(struct display_info_t const *dev)
  415. {
  416. struct iomuxc *iomux = (struct iomuxc *)
  417. IOMUXC_BASE_ADDR;
  418. u32 reg = readl(&iomux->gpr[2]);
  419. reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
  420. writel(reg, &iomux->gpr[2]);
  421. gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
  422. }
  423. static void enable_rgb(struct display_info_t const *dev)
  424. {
  425. imx_iomux_v3_setup_multiple_pads(
  426. rgb_pads,
  427. ARRAY_SIZE(rgb_pads));
  428. gpio_direction_output(RGB_BACKLIGHT_GP, 1);
  429. }
  430. static struct display_info_t const displays[] = {{
  431. .bus = -1,
  432. .addr = 0,
  433. .pixfmt = IPU_PIX_FMT_RGB24,
  434. .detect = detect_hdmi,
  435. .enable = do_enable_hdmi,
  436. .mode = {
  437. .name = "HDMI",
  438. .refresh = 60,
  439. .xres = 1024,
  440. .yres = 768,
  441. .pixclock = 15385,
  442. .left_margin = 220,
  443. .right_margin = 40,
  444. .upper_margin = 21,
  445. .lower_margin = 7,
  446. .hsync_len = 60,
  447. .vsync_len = 10,
  448. .sync = FB_SYNC_EXT,
  449. .vmode = FB_VMODE_NONINTERLACED
  450. } }, {
  451. .bus = 2,
  452. .addr = 0x4,
  453. .pixfmt = IPU_PIX_FMT_LVDS666,
  454. .detect = detect_i2c,
  455. .enable = enable_lvds,
  456. .mode = {
  457. .name = "Hannstar-XGA",
  458. .refresh = 60,
  459. .xres = 1024,
  460. .yres = 768,
  461. .pixclock = 15385,
  462. .left_margin = 220,
  463. .right_margin = 40,
  464. .upper_margin = 21,
  465. .lower_margin = 7,
  466. .hsync_len = 60,
  467. .vsync_len = 10,
  468. .sync = FB_SYNC_EXT,
  469. .vmode = FB_VMODE_NONINTERLACED
  470. } }, {
  471. .bus = 2,
  472. .addr = 0x38,
  473. .pixfmt = IPU_PIX_FMT_LVDS666,
  474. .detect = detect_i2c,
  475. .enable = enable_lvds,
  476. .mode = {
  477. .name = "wsvga-lvds",
  478. .refresh = 60,
  479. .xres = 1024,
  480. .yres = 600,
  481. .pixclock = 15385,
  482. .left_margin = 220,
  483. .right_margin = 40,
  484. .upper_margin = 21,
  485. .lower_margin = 7,
  486. .hsync_len = 60,
  487. .vsync_len = 10,
  488. .sync = FB_SYNC_EXT,
  489. .vmode = FB_VMODE_NONINTERLACED
  490. } }, {
  491. .bus = 2,
  492. .addr = 0x48,
  493. .pixfmt = IPU_PIX_FMT_RGB666,
  494. .detect = detect_i2c,
  495. .enable = enable_rgb,
  496. .mode = {
  497. .name = "wvga-rgb",
  498. .refresh = 57,
  499. .xres = 800,
  500. .yres = 480,
  501. .pixclock = 37037,
  502. .left_margin = 40,
  503. .right_margin = 60,
  504. .upper_margin = 10,
  505. .lower_margin = 10,
  506. .hsync_len = 20,
  507. .vsync_len = 10,
  508. .sync = 0,
  509. .vmode = FB_VMODE_NONINTERLACED
  510. } } };
  511. int board_video_skip(void)
  512. {
  513. int i;
  514. int ret;
  515. char const *panel = getenv("panel");
  516. if (!panel) {
  517. for (i = 0; i < ARRAY_SIZE(displays); i++) {
  518. struct display_info_t const *dev = displays+i;
  519. if (dev->detect(dev)) {
  520. panel = dev->mode.name;
  521. printf("auto-detected panel %s\n", panel);
  522. break;
  523. }
  524. }
  525. if (!panel) {
  526. panel = displays[0].mode.name;
  527. printf("No panel detected: default to %s\n", panel);
  528. }
  529. } else {
  530. for (i = 0; i < ARRAY_SIZE(displays); i++) {
  531. if (!strcmp(panel, displays[i].mode.name))
  532. break;
  533. }
  534. }
  535. if (i < ARRAY_SIZE(displays)) {
  536. ret = ipuv3_fb_init(&displays[i].mode, 0,
  537. displays[i].pixfmt);
  538. if (!ret) {
  539. displays[i].enable(displays+i);
  540. printf("Display: %s (%ux%u)\n",
  541. displays[i].mode.name,
  542. displays[i].mode.xres,
  543. displays[i].mode.yres);
  544. } else
  545. printf("LCD %s cannot be configured: %d\n",
  546. displays[i].mode.name, ret);
  547. } else {
  548. printf("unsupported panel %s\n", panel);
  549. ret = -EINVAL;
  550. }
  551. return (0 != ret);
  552. }
  553. static void setup_display(void)
  554. {
  555. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  556. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  557. int reg;
  558. enable_ipu_clock();
  559. imx_setup_hdmi();
  560. /* Turn on LDB0,IPU,IPU DI0 clocks */
  561. reg = __raw_readl(&mxc_ccm->CCGR3);
  562. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
  563. writel(reg, &mxc_ccm->CCGR3);
  564. /* set LDB0, LDB1 clk select to 011/011 */
  565. reg = readl(&mxc_ccm->cs2cdr);
  566. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  567. |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  568. reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  569. |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  570. writel(reg, &mxc_ccm->cs2cdr);
  571. reg = readl(&mxc_ccm->cscmr2);
  572. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  573. writel(reg, &mxc_ccm->cscmr2);
  574. reg = readl(&mxc_ccm->chsccdr);
  575. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  576. <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  577. writel(reg, &mxc_ccm->chsccdr);
  578. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  579. |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  580. |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  581. |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  582. |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  583. |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  584. |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  585. |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  586. |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  587. writel(reg, &iomux->gpr[2]);
  588. reg = readl(&iomux->gpr[3]);
  589. reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
  590. |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
  591. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  592. <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  593. writel(reg, &iomux->gpr[3]);
  594. /* backlights off until needed */
  595. imx_iomux_v3_setup_multiple_pads(backlight_pads,
  596. ARRAY_SIZE(backlight_pads));
  597. gpio_direction_input(LVDS_BACKLIGHT_GP);
  598. gpio_direction_input(RGB_BACKLIGHT_GP);
  599. }
  600. #endif
  601. int board_early_init_f(void)
  602. {
  603. setup_iomux_uart();
  604. /* Disable wl1271 For Nitrogen6w */
  605. gpio_direction_input(WL12XX_WL_IRQ_GP);
  606. gpio_direction_output(WL12XX_WL_ENABLE_GP, 0);
  607. gpio_direction_output(WL12XX_BT_ENABLE_GP, 0);
  608. imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
  609. setup_buttons();
  610. #if defined(CONFIG_VIDEO_IPUV3)
  611. setup_display();
  612. #endif
  613. return 0;
  614. }
  615. /*
  616. * Do not overwrite the console
  617. * Use always serial for U-Boot console
  618. */
  619. int overwrite_console(void)
  620. {
  621. return 1;
  622. }
  623. int board_init(void)
  624. {
  625. /* address of boot parameters */
  626. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  627. #ifdef CONFIG_MXC_SPI
  628. setup_spi();
  629. #endif
  630. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
  631. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  632. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  633. #ifdef CONFIG_CMD_SATA
  634. setup_sata();
  635. #endif
  636. return 0;
  637. }
  638. int checkboard(void)
  639. {
  640. if (gpio_get_value(WL12XX_WL_IRQ_GP))
  641. puts("Board: Nitrogen6X\n");
  642. else
  643. puts("Board: SABRE Lite\n");
  644. return 0;
  645. }
  646. struct button_key {
  647. char const *name;
  648. unsigned gpnum;
  649. char ident;
  650. };
  651. static struct button_key const buttons[] = {
  652. {"back", IMX_GPIO_NR(2, 2), 'B'},
  653. {"home", IMX_GPIO_NR(2, 4), 'H'},
  654. {"menu", IMX_GPIO_NR(2, 1), 'M'},
  655. {"search", IMX_GPIO_NR(2, 3), 'S'},
  656. {"volup", IMX_GPIO_NR(7, 13), 'V'},
  657. {"voldown", IMX_GPIO_NR(4, 5), 'v'},
  658. };
  659. /*
  660. * generate a null-terminated string containing the buttons pressed
  661. * returns number of keys pressed
  662. */
  663. static int read_keys(char *buf)
  664. {
  665. int i, numpressed = 0;
  666. for (i = 0; i < ARRAY_SIZE(buttons); i++) {
  667. if (!gpio_get_value(buttons[i].gpnum))
  668. buf[numpressed++] = buttons[i].ident;
  669. }
  670. buf[numpressed] = '\0';
  671. return numpressed;
  672. }
  673. static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  674. {
  675. char envvalue[ARRAY_SIZE(buttons)+1];
  676. int numpressed = read_keys(envvalue);
  677. setenv("keybd", envvalue);
  678. return numpressed == 0;
  679. }
  680. U_BOOT_CMD(
  681. kbd, 1, 1, do_kbd,
  682. "Tests for keypresses, sets 'keybd' environment variable",
  683. "Returns 0 (true) to shell if key is pressed."
  684. );
  685. #ifdef CONFIG_PREBOOT
  686. static char const kbd_magic_prefix[] = "key_magic";
  687. static char const kbd_command_prefix[] = "key_cmd";
  688. static void preboot_keys(void)
  689. {
  690. int numpressed;
  691. char keypress[ARRAY_SIZE(buttons)+1];
  692. numpressed = read_keys(keypress);
  693. if (numpressed) {
  694. char *kbd_magic_keys = getenv("magic_keys");
  695. char *suffix;
  696. /*
  697. * loop over all magic keys
  698. */
  699. for (suffix = kbd_magic_keys; *suffix; ++suffix) {
  700. char *keys;
  701. char magic[sizeof(kbd_magic_prefix) + 1];
  702. sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
  703. keys = getenv(magic);
  704. if (keys) {
  705. if (!strcmp(keys, keypress))
  706. break;
  707. }
  708. }
  709. if (*suffix) {
  710. char cmd_name[sizeof(kbd_command_prefix) + 1];
  711. char *cmd;
  712. sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
  713. cmd = getenv(cmd_name);
  714. if (cmd) {
  715. setenv("preboot", cmd);
  716. return;
  717. }
  718. }
  719. }
  720. }
  721. #endif
  722. #ifdef CONFIG_CMD_BMODE
  723. static const struct boot_mode board_boot_modes[] = {
  724. /* 4 bit bus width */
  725. {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  726. {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
  727. {NULL, 0},
  728. };
  729. #endif
  730. int misc_init_r(void)
  731. {
  732. #ifdef CONFIG_PREBOOT
  733. preboot_keys();
  734. #endif
  735. #ifdef CONFIG_CMD_BMODE
  736. add_board_boot_modes(board_boot_modes);
  737. #endif
  738. return 0;
  739. }