omap_common.h 17 KB

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  1. /*
  2. * (C) Copyright 2010
  3. * Texas Instruments, <www.ti.com>
  4. *
  5. * Aneesh V <aneesh@ti.com>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #ifndef _OMAP_COMMON_H_
  10. #define _OMAP_COMMON_H_
  11. #ifndef __ASSEMBLY__
  12. #include <common.h>
  13. #define NUM_SYS_CLKS 7
  14. struct prcm_regs {
  15. /* cm1.ckgen */
  16. u32 cm_clksel_core;
  17. u32 cm_clksel_abe;
  18. u32 cm_dll_ctrl;
  19. u32 cm_clkmode_dpll_core;
  20. u32 cm_idlest_dpll_core;
  21. u32 cm_autoidle_dpll_core;
  22. u32 cm_clksel_dpll_core;
  23. u32 cm_div_m2_dpll_core;
  24. u32 cm_div_m3_dpll_core;
  25. u32 cm_div_h11_dpll_core;
  26. u32 cm_div_h12_dpll_core;
  27. u32 cm_div_h13_dpll_core;
  28. u32 cm_div_h14_dpll_core;
  29. u32 cm_div_h21_dpll_core;
  30. u32 cm_div_h24_dpll_core;
  31. u32 cm_ssc_deltamstep_dpll_core;
  32. u32 cm_ssc_modfreqdiv_dpll_core;
  33. u32 cm_emu_override_dpll_core;
  34. u32 cm_div_h22_dpllcore;
  35. u32 cm_div_h23_dpll_core;
  36. u32 cm_clkmode_dpll_mpu;
  37. u32 cm_idlest_dpll_mpu;
  38. u32 cm_autoidle_dpll_mpu;
  39. u32 cm_clksel_dpll_mpu;
  40. u32 cm_div_m2_dpll_mpu;
  41. u32 cm_ssc_deltamstep_dpll_mpu;
  42. u32 cm_ssc_modfreqdiv_dpll_mpu;
  43. u32 cm_bypclk_dpll_mpu;
  44. u32 cm_clkmode_dpll_iva;
  45. u32 cm_idlest_dpll_iva;
  46. u32 cm_autoidle_dpll_iva;
  47. u32 cm_clksel_dpll_iva;
  48. u32 cm_div_h11_dpll_iva;
  49. u32 cm_div_h12_dpll_iva;
  50. u32 cm_ssc_deltamstep_dpll_iva;
  51. u32 cm_ssc_modfreqdiv_dpll_iva;
  52. u32 cm_bypclk_dpll_iva;
  53. u32 cm_clkmode_dpll_abe;
  54. u32 cm_idlest_dpll_abe;
  55. u32 cm_autoidle_dpll_abe;
  56. u32 cm_clksel_dpll_abe;
  57. u32 cm_div_m2_dpll_abe;
  58. u32 cm_div_m3_dpll_abe;
  59. u32 cm_ssc_deltamstep_dpll_abe;
  60. u32 cm_ssc_modfreqdiv_dpll_abe;
  61. u32 cm_clkmode_dpll_ddrphy;
  62. u32 cm_idlest_dpll_ddrphy;
  63. u32 cm_autoidle_dpll_ddrphy;
  64. u32 cm_clksel_dpll_ddrphy;
  65. u32 cm_div_m2_dpll_ddrphy;
  66. u32 cm_div_h11_dpll_ddrphy;
  67. u32 cm_div_h12_dpll_ddrphy;
  68. u32 cm_div_h13_dpll_ddrphy;
  69. u32 cm_ssc_deltamstep_dpll_ddrphy;
  70. u32 cm_clkmode_dpll_dsp;
  71. u32 cm_shadow_freq_config1;
  72. u32 cm_clkmode_dpll_gmac;
  73. u32 cm_mpu_mpu_clkctrl;
  74. /* cm1.dsp */
  75. u32 cm_dsp_clkstctrl;
  76. u32 cm_dsp_dsp_clkctrl;
  77. /* cm1.abe */
  78. u32 cm1_abe_clkstctrl;
  79. u32 cm1_abe_l4abe_clkctrl;
  80. u32 cm1_abe_aess_clkctrl;
  81. u32 cm1_abe_pdm_clkctrl;
  82. u32 cm1_abe_dmic_clkctrl;
  83. u32 cm1_abe_mcasp_clkctrl;
  84. u32 cm1_abe_mcbsp1_clkctrl;
  85. u32 cm1_abe_mcbsp2_clkctrl;
  86. u32 cm1_abe_mcbsp3_clkctrl;
  87. u32 cm1_abe_slimbus_clkctrl;
  88. u32 cm1_abe_timer5_clkctrl;
  89. u32 cm1_abe_timer6_clkctrl;
  90. u32 cm1_abe_timer7_clkctrl;
  91. u32 cm1_abe_timer8_clkctrl;
  92. u32 cm1_abe_wdt3_clkctrl;
  93. /* cm2.ckgen */
  94. u32 cm_clksel_mpu_m3_iss_root;
  95. u32 cm_clksel_usb_60mhz;
  96. u32 cm_scale_fclk;
  97. u32 cm_core_dvfs_perf1;
  98. u32 cm_core_dvfs_perf2;
  99. u32 cm_core_dvfs_perf3;
  100. u32 cm_core_dvfs_perf4;
  101. u32 cm_core_dvfs_current;
  102. u32 cm_iva_dvfs_perf_tesla;
  103. u32 cm_iva_dvfs_perf_ivahd;
  104. u32 cm_iva_dvfs_perf_abe;
  105. u32 cm_iva_dvfs_current;
  106. u32 cm_clkmode_dpll_per;
  107. u32 cm_idlest_dpll_per;
  108. u32 cm_autoidle_dpll_per;
  109. u32 cm_clksel_dpll_per;
  110. u32 cm_div_m2_dpll_per;
  111. u32 cm_div_m3_dpll_per;
  112. u32 cm_div_h11_dpll_per;
  113. u32 cm_div_h12_dpll_per;
  114. u32 cm_div_h13_dpll_per;
  115. u32 cm_div_h14_dpll_per;
  116. u32 cm_ssc_deltamstep_dpll_per;
  117. u32 cm_ssc_modfreqdiv_dpll_per;
  118. u32 cm_emu_override_dpll_per;
  119. u32 cm_clkmode_dpll_usb;
  120. u32 cm_idlest_dpll_usb;
  121. u32 cm_autoidle_dpll_usb;
  122. u32 cm_clksel_dpll_usb;
  123. u32 cm_div_m2_dpll_usb;
  124. u32 cm_ssc_deltamstep_dpll_usb;
  125. u32 cm_ssc_modfreqdiv_dpll_usb;
  126. u32 cm_clkdcoldo_dpll_usb;
  127. u32 cm_clkmode_dpll_pcie_ref;
  128. u32 cm_clkmode_apll_pcie;
  129. u32 cm_idlest_apll_pcie;
  130. u32 cm_div_m2_apll_pcie;
  131. u32 cm_clkvcoldo_apll_pcie;
  132. u32 cm_clkmode_dpll_unipro;
  133. u32 cm_idlest_dpll_unipro;
  134. u32 cm_autoidle_dpll_unipro;
  135. u32 cm_clksel_dpll_unipro;
  136. u32 cm_div_m2_dpll_unipro;
  137. u32 cm_ssc_deltamstep_dpll_unipro;
  138. u32 cm_ssc_modfreqdiv_dpll_unipro;
  139. /* cm2.core */
  140. u32 cm_coreaon_bandgap_clkctrl;
  141. u32 cm_coreaon_io_srcomp_clkctrl;
  142. u32 cm_l3_1_clkstctrl;
  143. u32 cm_l3_1_dynamicdep;
  144. u32 cm_l3_1_l3_1_clkctrl;
  145. u32 cm_l3_2_clkstctrl;
  146. u32 cm_l3_2_dynamicdep;
  147. u32 cm_l3_2_l3_2_clkctrl;
  148. u32 cm_l3_gpmc_clkctrl;
  149. u32 cm_l3_2_ocmc_ram_clkctrl;
  150. u32 cm_mpu_m3_clkstctrl;
  151. u32 cm_mpu_m3_staticdep;
  152. u32 cm_mpu_m3_dynamicdep;
  153. u32 cm_mpu_m3_mpu_m3_clkctrl;
  154. u32 cm_sdma_clkstctrl;
  155. u32 cm_sdma_staticdep;
  156. u32 cm_sdma_dynamicdep;
  157. u32 cm_sdma_sdma_clkctrl;
  158. u32 cm_memif_clkstctrl;
  159. u32 cm_memif_dmm_clkctrl;
  160. u32 cm_memif_emif_fw_clkctrl;
  161. u32 cm_memif_emif_1_clkctrl;
  162. u32 cm_memif_emif_2_clkctrl;
  163. u32 cm_memif_dll_clkctrl;
  164. u32 cm_memif_emif_h1_clkctrl;
  165. u32 cm_memif_emif_h2_clkctrl;
  166. u32 cm_memif_dll_h_clkctrl;
  167. u32 cm_c2c_clkstctrl;
  168. u32 cm_c2c_staticdep;
  169. u32 cm_c2c_dynamicdep;
  170. u32 cm_c2c_sad2d_clkctrl;
  171. u32 cm_c2c_modem_icr_clkctrl;
  172. u32 cm_c2c_sad2d_fw_clkctrl;
  173. u32 cm_l4cfg_clkstctrl;
  174. u32 cm_l4cfg_dynamicdep;
  175. u32 cm_l4cfg_l4_cfg_clkctrl;
  176. u32 cm_l4cfg_hw_sem_clkctrl;
  177. u32 cm_l4cfg_mailbox_clkctrl;
  178. u32 cm_l4cfg_sar_rom_clkctrl;
  179. u32 cm_l3instr_clkstctrl;
  180. u32 cm_l3instr_l3_3_clkctrl;
  181. u32 cm_l3instr_l3_instr_clkctrl;
  182. u32 cm_l3instr_intrconn_wp1_clkctrl;
  183. /* cm2.ivahd */
  184. u32 cm_ivahd_clkstctrl;
  185. u32 cm_ivahd_ivahd_clkctrl;
  186. u32 cm_ivahd_sl2_clkctrl;
  187. /* cm2.cam */
  188. u32 cm_cam_clkstctrl;
  189. u32 cm_cam_iss_clkctrl;
  190. u32 cm_cam_fdif_clkctrl;
  191. u32 cm_cam_vip1_clkctrl;
  192. u32 cm_cam_vip2_clkctrl;
  193. u32 cm_cam_vip3_clkctrl;
  194. u32 cm_cam_lvdsrx_clkctrl;
  195. u32 cm_cam_csi1_clkctrl;
  196. u32 cm_cam_csi2_clkctrl;
  197. /* cm2.dss */
  198. u32 cm_dss_clkstctrl;
  199. u32 cm_dss_dss_clkctrl;
  200. /* cm2.sgx */
  201. u32 cm_sgx_clkstctrl;
  202. u32 cm_sgx_sgx_clkctrl;
  203. /* cm2.l3init */
  204. u32 cm_l3init_clkstctrl;
  205. /* cm2.l3init */
  206. u32 cm_l3init_hsmmc1_clkctrl;
  207. u32 cm_l3init_hsmmc2_clkctrl;
  208. u32 cm_l3init_hsi_clkctrl;
  209. u32 cm_l3init_hsusbhost_clkctrl;
  210. u32 cm_l3init_hsusbotg_clkctrl;
  211. u32 cm_l3init_hsusbtll_clkctrl;
  212. u32 cm_l3init_p1500_clkctrl;
  213. u32 cm_l3init_fsusb_clkctrl;
  214. u32 cm_l3init_ocp2scp1_clkctrl;
  215. u32 prm_irqstatus_mpu_2;
  216. /* cm2.l4per */
  217. u32 cm_l4per_clkstctrl;
  218. u32 cm_l4per_dynamicdep;
  219. u32 cm_l4per_adc_clkctrl;
  220. u32 cm_l4per_gptimer10_clkctrl;
  221. u32 cm_l4per_gptimer11_clkctrl;
  222. u32 cm_l4per_gptimer2_clkctrl;
  223. u32 cm_l4per_gptimer3_clkctrl;
  224. u32 cm_l4per_gptimer4_clkctrl;
  225. u32 cm_l4per_gptimer9_clkctrl;
  226. u32 cm_l4per_elm_clkctrl;
  227. u32 cm_l4per_gpio2_clkctrl;
  228. u32 cm_l4per_gpio3_clkctrl;
  229. u32 cm_l4per_gpio4_clkctrl;
  230. u32 cm_l4per_gpio5_clkctrl;
  231. u32 cm_l4per_gpio6_clkctrl;
  232. u32 cm_l4per_hdq1w_clkctrl;
  233. u32 cm_l4per_hecc1_clkctrl;
  234. u32 cm_l4per_hecc2_clkctrl;
  235. u32 cm_l4per_i2c1_clkctrl;
  236. u32 cm_l4per_i2c2_clkctrl;
  237. u32 cm_l4per_i2c3_clkctrl;
  238. u32 cm_l4per_i2c4_clkctrl;
  239. u32 cm_l4per_l4per_clkctrl;
  240. u32 cm_l4per_mcasp2_clkctrl;
  241. u32 cm_l4per_mcasp3_clkctrl;
  242. u32 cm_l4per_mgate_clkctrl;
  243. u32 cm_l4per_mcspi1_clkctrl;
  244. u32 cm_l4per_mcspi2_clkctrl;
  245. u32 cm_l4per_mcspi3_clkctrl;
  246. u32 cm_l4per_mcspi4_clkctrl;
  247. u32 cm_l4per_gpio7_clkctrl;
  248. u32 cm_l4per_gpio8_clkctrl;
  249. u32 cm_l4per_mmcsd3_clkctrl;
  250. u32 cm_l4per_mmcsd4_clkctrl;
  251. u32 cm_l4per_msprohg_clkctrl;
  252. u32 cm_l4per_slimbus2_clkctrl;
  253. u32 cm_l4per_uart1_clkctrl;
  254. u32 cm_l4per_uart2_clkctrl;
  255. u32 cm_l4per_uart3_clkctrl;
  256. u32 cm_l4per_uart4_clkctrl;
  257. u32 cm_l4per_mmcsd5_clkctrl;
  258. u32 cm_l4per_i2c5_clkctrl;
  259. u32 cm_l4per_uart5_clkctrl;
  260. u32 cm_l4per_uart6_clkctrl;
  261. u32 cm_l4sec_clkstctrl;
  262. u32 cm_l4sec_staticdep;
  263. u32 cm_l4sec_dynamicdep;
  264. u32 cm_l4sec_aes1_clkctrl;
  265. u32 cm_l4sec_aes2_clkctrl;
  266. u32 cm_l4sec_des3des_clkctrl;
  267. u32 cm_l4sec_pkaeip29_clkctrl;
  268. u32 cm_l4sec_rng_clkctrl;
  269. u32 cm_l4sec_sha2md51_clkctrl;
  270. u32 cm_l4sec_cryptodma_clkctrl;
  271. /* l4 wkup regs */
  272. u32 cm_abe_pll_ref_clksel;
  273. u32 cm_sys_clksel;
  274. u32 cm_abe_pll_sys_clksel;
  275. u32 cm_wkup_clkstctrl;
  276. u32 cm_wkup_l4wkup_clkctrl;
  277. u32 cm_wkup_wdtimer1_clkctrl;
  278. u32 cm_wkup_wdtimer2_clkctrl;
  279. u32 cm_wkup_gpio1_clkctrl;
  280. u32 cm_wkup_gptimer1_clkctrl;
  281. u32 cm_wkup_gptimer12_clkctrl;
  282. u32 cm_wkup_synctimer_clkctrl;
  283. u32 cm_wkup_usim_clkctrl;
  284. u32 cm_wkup_sarram_clkctrl;
  285. u32 cm_wkup_keyboard_clkctrl;
  286. u32 cm_wkup_rtc_clkctrl;
  287. u32 cm_wkup_bandgap_clkctrl;
  288. u32 cm_wkupaon_scrm_clkctrl;
  289. u32 cm_wkupaon_io_srcomp_clkctrl;
  290. u32 prm_rstctrl;
  291. u32 prm_rstst;
  292. u32 prm_rsttime;
  293. u32 prm_vc_val_bypass;
  294. u32 prm_vc_cfg_i2c_mode;
  295. u32 prm_vc_cfg_i2c_clk;
  296. u32 prm_sldo_core_setup;
  297. u32 prm_sldo_core_ctrl;
  298. u32 prm_sldo_mpu_setup;
  299. u32 prm_sldo_mpu_ctrl;
  300. u32 prm_sldo_mm_setup;
  301. u32 prm_sldo_mm_ctrl;
  302. u32 prm_abbldo_mpu_setup;
  303. u32 prm_abbldo_mpu_ctrl;
  304. u32 cm_div_m4_dpll_core;
  305. u32 cm_div_m5_dpll_core;
  306. u32 cm_div_m6_dpll_core;
  307. u32 cm_div_m7_dpll_core;
  308. u32 cm_div_m4_dpll_iva;
  309. u32 cm_div_m5_dpll_iva;
  310. u32 cm_div_m4_dpll_ddrphy;
  311. u32 cm_div_m5_dpll_ddrphy;
  312. u32 cm_div_m6_dpll_ddrphy;
  313. u32 cm_div_m4_dpll_per;
  314. u32 cm_div_m5_dpll_per;
  315. u32 cm_div_m6_dpll_per;
  316. u32 cm_div_m7_dpll_per;
  317. u32 cm_l3instr_intrconn_wp1_clkct;
  318. u32 cm_l3init_usbphy_clkctrl;
  319. u32 cm_l4per_mcbsp4_clkctrl;
  320. u32 prm_vc_cfg_channel;
  321. /* SCRM stuff, used by some boards */
  322. u32 scrm_auxclk0;
  323. u32 scrm_auxclk1;
  324. /* GMAC Clk Ctrl */
  325. u32 cm_gmac_gmac_clkctrl;
  326. u32 cm_gmac_clkstctrl;
  327. };
  328. struct omap_sys_ctrl_regs {
  329. u32 control_status;
  330. u32 control_core_mac_id_0_lo;
  331. u32 control_core_mac_id_0_hi;
  332. u32 control_core_mac_id_1_lo;
  333. u32 control_core_mac_id_1_hi;
  334. u32 control_std_fuse_opp_vdd_mpu_2;
  335. u32 control_core_mmr_lock1;
  336. u32 control_core_mmr_lock2;
  337. u32 control_core_mmr_lock3;
  338. u32 control_core_mmr_lock4;
  339. u32 control_core_mmr_lock5;
  340. u32 control_core_control_io1;
  341. u32 control_core_control_io2;
  342. u32 control_id_code;
  343. u32 control_std_fuse_opp_bgap;
  344. u32 control_ldosram_iva_voltage_ctrl;
  345. u32 control_ldosram_mpu_voltage_ctrl;
  346. u32 control_ldosram_core_voltage_ctrl;
  347. u32 control_usbotghs_ctrl;
  348. u32 control_padconf_core_base;
  349. u32 control_paconf_global;
  350. u32 control_paconf_mode;
  351. u32 control_smart1io_padconf_0;
  352. u32 control_smart1io_padconf_1;
  353. u32 control_smart1io_padconf_2;
  354. u32 control_smart2io_padconf_0;
  355. u32 control_smart2io_padconf_1;
  356. u32 control_smart2io_padconf_2;
  357. u32 control_smart3io_padconf_0;
  358. u32 control_smart3io_padconf_1;
  359. u32 control_pbias;
  360. u32 control_i2c_0;
  361. u32 control_camera_rx;
  362. u32 control_hdmi_tx_phy;
  363. u32 control_uniportm;
  364. u32 control_dsiphy;
  365. u32 control_mcbsplp;
  366. u32 control_usb2phycore;
  367. u32 control_hdmi_1;
  368. u32 control_hsi;
  369. u32 control_ddr3ch1_0;
  370. u32 control_ddr3ch2_0;
  371. u32 control_ddrch1_0;
  372. u32 control_ddrch1_1;
  373. u32 control_ddrch2_0;
  374. u32 control_ddrch2_1;
  375. u32 control_lpddr2ch1_0;
  376. u32 control_lpddr2ch1_1;
  377. u32 control_ddrio_0;
  378. u32 control_ddrio_1;
  379. u32 control_ddrio_2;
  380. u32 control_ddr_control_ext_0;
  381. u32 control_lpddr2io1_0;
  382. u32 control_lpddr2io1_1;
  383. u32 control_lpddr2io1_2;
  384. u32 control_lpddr2io1_3;
  385. u32 control_lpddr2io2_0;
  386. u32 control_lpddr2io2_1;
  387. u32 control_lpddr2io2_2;
  388. u32 control_lpddr2io2_3;
  389. u32 control_hyst_1;
  390. u32 control_usbb_hsic_control;
  391. u32 control_c2c;
  392. u32 control_core_control_spare_rw;
  393. u32 control_core_control_spare_r;
  394. u32 control_core_control_spare_r_c0;
  395. u32 control_srcomp_north_side;
  396. u32 control_srcomp_south_side;
  397. u32 control_srcomp_east_side;
  398. u32 control_srcomp_west_side;
  399. u32 control_srcomp_code_latch;
  400. u32 control_pbiaslite;
  401. u32 control_port_emif1_sdram_config;
  402. u32 control_port_emif1_lpddr2_nvm_config;
  403. u32 control_port_emif2_sdram_config;
  404. u32 control_emif1_sdram_config_ext;
  405. u32 control_emif2_sdram_config_ext;
  406. u32 control_wkup_ldovbb_mpu_voltage_ctrl;
  407. u32 control_smart1nopmio_padconf_0;
  408. u32 control_smart1nopmio_padconf_1;
  409. u32 control_padconf_mode;
  410. u32 control_xtal_oscillator;
  411. u32 control_i2c_2;
  412. u32 control_ckobuffer;
  413. u32 control_wkup_control_spare_rw;
  414. u32 control_wkup_control_spare_r;
  415. u32 control_wkup_control_spare_r_c0;
  416. u32 control_srcomp_east_side_wkup;
  417. u32 control_efuse_1;
  418. u32 control_efuse_2;
  419. u32 control_efuse_3;
  420. u32 control_efuse_4;
  421. u32 control_efuse_5;
  422. u32 control_efuse_6;
  423. u32 control_efuse_7;
  424. u32 control_efuse_8;
  425. u32 control_efuse_9;
  426. u32 control_efuse_10;
  427. u32 control_efuse_11;
  428. u32 control_efuse_12;
  429. u32 control_efuse_13;
  430. u32 control_padconf_wkup_base;
  431. };
  432. struct dpll_params {
  433. u32 m;
  434. u32 n;
  435. s8 m2;
  436. s8 m3;
  437. s8 m4_h11;
  438. s8 m5_h12;
  439. s8 m6_h13;
  440. s8 m7_h14;
  441. s8 h21;
  442. s8 h22;
  443. s8 h23;
  444. s8 h24;
  445. };
  446. struct dpll_regs {
  447. u32 cm_clkmode_dpll;
  448. u32 cm_idlest_dpll;
  449. u32 cm_autoidle_dpll;
  450. u32 cm_clksel_dpll;
  451. u32 cm_div_m2_dpll;
  452. u32 cm_div_m3_dpll;
  453. u32 cm_div_m4_h11_dpll;
  454. u32 cm_div_m5_h12_dpll;
  455. u32 cm_div_m6_h13_dpll;
  456. u32 cm_div_m7_h14_dpll;
  457. u32 reserved[2];
  458. u32 cm_div_h21_dpll;
  459. u32 cm_div_h22_dpll;
  460. u32 cm_div_h23_dpll;
  461. u32 cm_div_h24_dpll;
  462. };
  463. struct dplls {
  464. const struct dpll_params *mpu;
  465. const struct dpll_params *core;
  466. const struct dpll_params *per;
  467. const struct dpll_params *abe;
  468. const struct dpll_params *iva;
  469. const struct dpll_params *usb;
  470. const struct dpll_params *ddr;
  471. const struct dpll_params *gmac;
  472. };
  473. struct pmic_data {
  474. u32 base_offset;
  475. u32 step;
  476. u32 start_code;
  477. unsigned gpio;
  478. int gpio_en;
  479. u32 i2c_slave_addr;
  480. void (*pmic_bus_init)(void);
  481. int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
  482. };
  483. /**
  484. * struct volts_efuse_data - efuse definition for voltage
  485. * @reg: register address for efuse
  486. * @reg_bits: Number of bits in a register address, mandatory.
  487. */
  488. struct volts_efuse_data {
  489. u32 reg;
  490. u8 reg_bits;
  491. };
  492. struct volts {
  493. u32 value;
  494. u32 addr;
  495. struct volts_efuse_data efuse;
  496. struct pmic_data *pmic;
  497. };
  498. struct vcores_data {
  499. struct volts mpu;
  500. struct volts core;
  501. struct volts mm;
  502. struct volts gpu;
  503. struct volts eve;
  504. struct volts iva;
  505. };
  506. extern struct prcm_regs const **prcm;
  507. extern struct prcm_regs const omap5_es1_prcm;
  508. extern struct prcm_regs const omap5_es2_prcm;
  509. extern struct prcm_regs const omap4_prcm;
  510. extern struct prcm_regs const dra7xx_prcm;
  511. extern struct dplls const **dplls_data;
  512. extern struct vcores_data const **omap_vcores;
  513. extern const u32 sys_clk_array[8];
  514. extern struct omap_sys_ctrl_regs const **ctrl;
  515. extern struct omap_sys_ctrl_regs const omap4_ctrl;
  516. extern struct omap_sys_ctrl_regs const omap5_ctrl;
  517. extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
  518. void hw_data_init(void);
  519. const struct dpll_params *get_mpu_dpll_params(struct dplls const *);
  520. const struct dpll_params *get_core_dpll_params(struct dplls const *);
  521. const struct dpll_params *get_per_dpll_params(struct dplls const *);
  522. const struct dpll_params *get_iva_dpll_params(struct dplls const *);
  523. const struct dpll_params *get_usb_dpll_params(struct dplls const *);
  524. const struct dpll_params *get_abe_dpll_params(struct dplls const *);
  525. void do_enable_clocks(u32 const *clk_domains,
  526. u32 const *clk_modules_hw_auto,
  527. u32 const *clk_modules_explicit_en,
  528. u8 wait_for_enable);
  529. void setup_post_dividers(u32 const base,
  530. const struct dpll_params *params);
  531. u32 omap_ddr_clk(void);
  532. u32 get_sys_clk_index(void);
  533. void enable_basic_clocks(void);
  534. void enable_basic_uboot_clocks(void);
  535. void enable_non_essential_clocks(void);
  536. void scale_vcores(struct vcores_data const *);
  537. u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
  538. void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
  539. void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
  540. u32 txdone, u32 txdone_mask, u32 opp);
  541. s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
  542. /* HW Init Context */
  543. #define OMAP_INIT_CONTEXT_SPL 0
  544. #define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1
  545. #define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2
  546. #define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3
  547. /* ABB */
  548. #define OMAP_ABB_NOMINAL_OPP 0
  549. #define OMAP_ABB_FAST_OPP 1
  550. #define OMAP_ABB_SLOW_OPP 3
  551. #define OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK (0x1 << 0)
  552. #define OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK (0x1 << 1)
  553. #define OMAP_ABB_CONTROL_OPP_CHANGE_MASK (0x1 << 2)
  554. #define OMAP_ABB_CONTROL_SR2_IN_TRANSITION_MASK (0x1 << 6)
  555. #define OMAP_ABB_SETUP_SR2EN_MASK (0x1 << 0)
  556. #define OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK (0x1 << 2)
  557. #define OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK (0x1 << 1)
  558. #define OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK (0xff << 8)
  559. static inline u32 omap_revision(void)
  560. {
  561. extern u32 *const omap_si_rev;
  562. return *omap_si_rev;
  563. }
  564. #define OMAP54xx 0x54000000
  565. static inline u8 is_omap54xx(void)
  566. {
  567. extern u32 *const omap_si_rev;
  568. return ((*omap_si_rev & 0xFF000000) == OMAP54xx);
  569. }
  570. #endif
  571. /*
  572. * silicon revisions.
  573. * Moving this to common, so that most of code can be moved to common,
  574. * directories.
  575. */
  576. /* omap4 */
  577. #define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
  578. #define OMAP4430_ES1_0 0x44300100
  579. #define OMAP4430_ES2_0 0x44300200
  580. #define OMAP4430_ES2_1 0x44300210
  581. #define OMAP4430_ES2_2 0x44300220
  582. #define OMAP4430_ES2_3 0x44300230
  583. #define OMAP4460_ES1_0 0x44600100
  584. #define OMAP4460_ES1_1 0x44600110
  585. #define OMAP4470_ES1_0 0x44700100
  586. /* omap5 */
  587. #define OMAP5430_SILICON_ID_INVALID 0
  588. #define OMAP5430_ES1_0 0x54300100
  589. #define OMAP5432_ES1_0 0x54320100
  590. #define OMAP5430_ES2_0 0x54300200
  591. #define OMAP5432_ES2_0 0x54320200
  592. /* DRA7XX */
  593. #define DRA752_ES1_0 0x07520100
  594. /*
  595. * SRAM scratch space entries
  596. */
  597. #define OMAP_SRAM_SCRATCH_OMAP_REV SRAM_SCRATCH_SPACE_ADDR
  598. #define OMAP_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
  599. #define OMAP_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
  600. #define OMAP_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
  601. #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
  602. #define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
  603. #define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
  604. #define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
  605. #define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24)
  606. #define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x28)
  607. #endif /* _OMAP_COMMON_H_ */