hardware.h 2.4 KB

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  1. /*
  2. * Copyright (c) 2013 Xilinx Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef _ASM_ARCH_HARDWARE_H
  7. #define _ASM_ARCH_HARDWARE_H
  8. #define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000
  9. #define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
  10. #define ZYNQ_SCU_BASEADDR 0xF8F00000
  11. #define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600
  12. #define ZYNQ_GEM_BASEADDR0 0xE000B000
  13. #define ZYNQ_GEM_BASEADDR1 0xE000C000
  14. #define ZYNQ_SDHCI_BASEADDR0 0xE0100000
  15. #define ZYNQ_SDHCI_BASEADDR1 0xE0101000
  16. #define ZYNQ_I2C_BASEADDR0 0xE0004000
  17. #define ZYNQ_I2C_BASEADDR1 0xE0005000
  18. #define ZYNQ_SPI_BASEADDR0 0xE0006000
  19. #define ZYNQ_SPI_BASEADDR1 0xE0007000
  20. #define ZYNQ_DDRC_BASEADDR 0xF8006000
  21. /* Reflect slcr offsets */
  22. struct slcr_regs {
  23. u32 scl; /* 0x0 */
  24. u32 slcr_lock; /* 0x4 */
  25. u32 slcr_unlock; /* 0x8 */
  26. u32 reserved0[75];
  27. u32 gem0_rclk_ctrl; /* 0x138 */
  28. u32 gem1_rclk_ctrl; /* 0x13c */
  29. u32 gem0_clk_ctrl; /* 0x140 */
  30. u32 gem1_clk_ctrl; /* 0x144 */
  31. u32 reserved1[46];
  32. u32 pss_rst_ctrl; /* 0x200 */
  33. u32 reserved2[15];
  34. u32 fpga_rst_ctrl; /* 0x240 */
  35. u32 reserved3[5];
  36. u32 reboot_status; /* 0x258 */
  37. u32 boot_mode; /* 0x25c */
  38. u32 reserved4[116];
  39. u32 trust_zone; /* 0x430 */ /* FIXME */
  40. u32 reserved5_1[63];
  41. u32 pss_idcode; /* 0x530 */
  42. u32 reserved5_2[51];
  43. u32 ddr_urgent; /* 0x600 */
  44. u32 reserved6[6];
  45. u32 ddr_urgent_sel; /* 0x61c */
  46. u32 reserved7[56];
  47. u32 mio_pin[54]; /* 0x700 - 0x7D4 */
  48. u32 reserved8[74];
  49. u32 lvl_shftr_en; /* 0x900 */
  50. u32 reserved9[3];
  51. u32 ocm_cfg; /* 0x910 */
  52. };
  53. #define slcr_base ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR)
  54. struct devcfg_regs {
  55. u32 ctrl; /* 0x0 */
  56. u32 lock; /* 0x4 */
  57. u32 cfg; /* 0x8 */
  58. u32 int_sts; /* 0xc */
  59. u32 int_mask; /* 0x10 */
  60. u32 status; /* 0x14 */
  61. u32 dma_src_addr; /* 0x18 */
  62. u32 dma_dst_addr; /* 0x1c */
  63. u32 dma_src_len; /* 0x20 */
  64. u32 dma_dst_len; /* 0x24 */
  65. u32 rom_shadow; /* 0x28 */
  66. u32 reserved1[2];
  67. u32 unlock; /* 0x34 */
  68. u32 reserved2[18];
  69. u32 mctrl; /* 0x80 */
  70. u32 reserved3;
  71. u32 write_count; /* 0x88 */
  72. u32 read_count; /* 0x8c */
  73. };
  74. #define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR)
  75. struct scu_regs {
  76. u32 reserved1[16];
  77. u32 filter_start; /* 0x40 */
  78. u32 filter_end; /* 0x44 */
  79. };
  80. #define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR)
  81. struct ddrc_regs {
  82. u32 ddrc_ctrl; /* 0x0 */
  83. u32 reserved[60];
  84. u32 ecc_scrub; /* 0xF4 */
  85. };
  86. #define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR)
  87. #endif /* _ASM_ARCH_HARDWARE_H */