omap.h 7.2 KB

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  1. /*
  2. * (C) Copyright 2010
  3. * Texas Instruments, <www.ti.com>
  4. *
  5. * Authors:
  6. * Aneesh V <aneesh@ti.com>
  7. * Sricharan R <r.sricharan@ti.com>
  8. *
  9. * SPDX-License-Identifier: GPL-2.0+
  10. */
  11. #ifndef _OMAP5_H_
  12. #define _OMAP5_H_
  13. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  14. #include <asm/types.h>
  15. #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
  16. /*
  17. * L4 Peripherals - L4 Wakeup and L4 Core now
  18. */
  19. #define OMAP54XX_L4_CORE_BASE 0x4A000000
  20. #define OMAP54XX_L4_WKUP_BASE 0x4Ae00000
  21. #define OMAP54XX_L4_PER_BASE 0x48000000
  22. #define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
  23. #define OMAP54XX_DRAM_ADDR_SPACE_END 0xFFFFFFFF
  24. #define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START
  25. #define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END
  26. /* CONTROL ID CODE */
  27. #define CONTROL_CORE_ID_CODE 0x4A002204
  28. #define CONTROL_WKUP_ID_CODE 0x4AE0C204
  29. #ifdef CONFIG_DRA7XX
  30. #define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE
  31. #else
  32. #define CONTROL_ID_CODE CONTROL_CORE_ID_CODE
  33. #endif
  34. /* To be verified */
  35. #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F
  36. #define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F
  37. #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F
  38. #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F
  39. #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F
  40. /* UART */
  41. #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
  42. #define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000)
  43. #define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000)
  44. /* General Purpose Timers */
  45. #define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000)
  46. #define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000)
  47. #define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000)
  48. /* Watchdog Timer2 - MPU watchdog */
  49. #define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000)
  50. /* GPMC */
  51. #define OMAP54XX_GPMC_BASE 0x50000000
  52. /*
  53. * Hardware Register Details
  54. */
  55. /* Watchdog Timer */
  56. #define WD_UNLOCK1 0xAAAA
  57. #define WD_UNLOCK2 0x5555
  58. /* GP Timer */
  59. #define TCLR_ST (0x1 << 0)
  60. #define TCLR_AR (0x1 << 1)
  61. #define TCLR_PRE (0x1 << 5)
  62. /* Control Module */
  63. #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5)
  64. #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f
  65. #define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110
  66. #define CONTROL_EFUSE_2_OVERRIDE 0x00084000
  67. /* LPDDR2 IO regs */
  68. #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
  69. #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
  70. #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
  71. #define LPDDR2IO_GR10_WD_MASK (3 << 17)
  72. #define CONTROL_LPDDR2IO_3_VAL 0xA0888C00
  73. /* CONTROL_EFUSE_2 */
  74. #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
  75. #define SDCARD_BIAS_PWRDNZ (1 << 27)
  76. #define SDCARD_PWRDNZ (1 << 26)
  77. #define SDCARD_BIAS_HIZ_MODE (1 << 25)
  78. #define SDCARD_PBIASLITE_VMODE (1 << 21)
  79. #ifndef __ASSEMBLY__
  80. struct s32ktimer {
  81. unsigned char res[0x10];
  82. unsigned int s32k_cr; /* 0x10 */
  83. };
  84. #define DEVICE_TYPE_SHIFT 0x6
  85. #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
  86. #define DEVICE_GP 0x3
  87. /* Output impedance control */
  88. #define ds_120_ohm 0x0
  89. #define ds_60_ohm 0x1
  90. #define ds_45_ohm 0x2
  91. #define ds_30_ohm 0x3
  92. #define ds_mask 0x3
  93. /* Slew rate control */
  94. #define sc_slow 0x0
  95. #define sc_medium 0x1
  96. #define sc_fast 0x2
  97. #define sc_na 0x3
  98. #define sc_mask 0x3
  99. /* Target capacitance control */
  100. #define lb_5_12_pf 0x0
  101. #define lb_12_25_pf 0x1
  102. #define lb_25_50_pf 0x2
  103. #define lb_50_80_pf 0x3
  104. #define lb_mask 0x3
  105. #define usb_i_mask 0x7
  106. #define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN 0x80828082
  107. #define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200
  108. #define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421
  109. #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
  110. #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
  111. #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C
  112. #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464
  113. #define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631
  114. #define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC
  115. #define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0
  116. #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
  117. #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465
  118. #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
  119. #define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8
  120. #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
  121. #define EFUSE_1 0x45145100
  122. #define EFUSE_2 0x45145100
  123. #define EFUSE_3 0x45145100
  124. #define EFUSE_4 0x45145100
  125. #endif /* __ASSEMBLY__ */
  126. /*
  127. * In all cases, the TRM defines the RAM Memory Map for the processor
  128. * and indicates the area for the downloaded image. We use all of that
  129. * space for download and once up and running may use other parts of the
  130. * map for our needs. We set a scratch space that is at the end of the
  131. * OMAP5 download area, but within the DRA7xx download area (as it is
  132. * much larger) and do not, at this time, make use of the additional
  133. * space.
  134. */
  135. #ifdef CONFIG_DRA7XX
  136. #define NON_SECURE_SRAM_START 0x40300000
  137. #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
  138. #else
  139. #define NON_SECURE_SRAM_START 0x40300000
  140. #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
  141. #endif
  142. #define SRAM_SCRATCH_SPACE_ADDR 0x4031E000
  143. /* base address for indirect vectors (internal boot mode) */
  144. #define SRAM_ROM_VECT_BASE 0x4031F000
  145. /* CONTROL_SRCOMP_XXX_SIDE */
  146. #define OVERRIDE_XS_SHIFT 30
  147. #define OVERRIDE_XS_MASK (1 << 30)
  148. #define SRCODE_READ_XS_SHIFT 12
  149. #define SRCODE_READ_XS_MASK (0xff << 12)
  150. #define PWRDWN_XS_SHIFT 11
  151. #define PWRDWN_XS_MASK (1 << 11)
  152. #define DIVIDE_FACTOR_XS_SHIFT 4
  153. #define DIVIDE_FACTOR_XS_MASK (0x7f << 4)
  154. #define MULTIPLY_FACTOR_XS_SHIFT 1
  155. #define MULTIPLY_FACTOR_XS_MASK (0x7 << 1)
  156. #define SRCODE_OVERRIDE_SEL_XS_SHIFT 0
  157. #define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0)
  158. /* ABB settings */
  159. #define OMAP_ABB_SETTLING_TIME 50
  160. #define OMAP_ABB_CLOCK_CYCLES 16
  161. /* ABB tranxdone mask */
  162. #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7)
  163. /* ABB efuse masks */
  164. #define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24)
  165. #define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29)
  166. #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10)
  167. #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0)
  168. /* IO Delay module defines */
  169. #define CFG_IO_DELAY_BASE 0x4844A000
  170. #define CFG_IO_DELAY_LOCK (CFG_IO_DELAY_BASE + 0x02C)
  171. /* CPSW IO Delay registers*/
  172. #define CFG_RGMII0_TXCTL (CFG_IO_DELAY_BASE + 0x74C)
  173. #define CFG_RGMII0_TXD0 (CFG_IO_DELAY_BASE + 0x758)
  174. #define CFG_RGMII0_TXD1 (CFG_IO_DELAY_BASE + 0x764)
  175. #define CFG_RGMII0_TXD2 (CFG_IO_DELAY_BASE + 0x770)
  176. #define CFG_RGMII0_TXD3 (CFG_IO_DELAY_BASE + 0x77C)
  177. #define CFG_VIN2A_D13 (CFG_IO_DELAY_BASE + 0xA7C)
  178. #define CFG_VIN2A_D17 (CFG_IO_DELAY_BASE + 0xAAC)
  179. #define CFG_VIN2A_D16 (CFG_IO_DELAY_BASE + 0xAA0)
  180. #define CFG_VIN2A_D15 (CFG_IO_DELAY_BASE + 0xA94)
  181. #define CFG_VIN2A_D14 (CFG_IO_DELAY_BASE + 0xA88)
  182. #define CFG_IO_DELAY_UNLOCK_KEY 0x0000AAAA
  183. #define CFG_IO_DELAY_LOCK_KEY 0x0000AAAB
  184. #define CFG_IO_DELAY_ACCESS_PATTERN 0x00029000
  185. #define CFG_IO_DELAY_LOCK_MASK 0x400
  186. #ifndef __ASSEMBLY__
  187. struct srcomp_params {
  188. s8 divide_factor;
  189. s8 multiply_factor;
  190. };
  191. struct ctrl_ioregs {
  192. u32 ctrl_ddrch;
  193. u32 ctrl_lpddr2ch;
  194. u32 ctrl_ddr3ch;
  195. u32 ctrl_ddrio_0;
  196. u32 ctrl_ddrio_1;
  197. u32 ctrl_ddrio_2;
  198. u32 ctrl_emif_sdram_config_ext;
  199. u32 ctrl_ddr_ctrl_ext_0;
  200. };
  201. struct io_delay {
  202. u32 addr;
  203. u32 dly;
  204. };
  205. #endif /* __ASSEMBLY__ */
  206. #endif