clock.h 7.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250
  1. /*
  2. * (C) Copyright 2010
  3. * Texas Instruments, <www.ti.com>
  4. *
  5. * Aneesh V <aneesh@ti.com>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #ifndef _CLOCKS_OMAP4_H_
  10. #define _CLOCKS_OMAP4_H_
  11. #include <common.h>
  12. #include <asm/omap_common.h>
  13. /*
  14. * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
  15. * loop, allow for a minimum of 2 ms wait (in reality the wait will be
  16. * much more than that)
  17. */
  18. #define LDELAY 1000000
  19. /* CM_DLL_CTRL */
  20. #define CM_DLL_CTRL_OVERRIDE_SHIFT 0
  21. #define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
  22. #define CM_DLL_CTRL_NO_OVERRIDE 0
  23. /* CM_CLKMODE_DPLL */
  24. #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
  25. #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
  26. #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
  27. #define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
  28. #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
  29. #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
  30. #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
  31. #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
  32. #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
  33. #define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
  34. #define CM_CLKMODE_DPLL_EN_SHIFT 0
  35. #define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
  36. #define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
  37. #define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
  38. #define DPLL_EN_STOP 1
  39. #define DPLL_EN_MN_BYPASS 4
  40. #define DPLL_EN_LOW_POWER_BYPASS 5
  41. #define DPLL_EN_FAST_RELOCK_BYPASS 6
  42. #define DPLL_EN_LOCK 7
  43. /* CM_IDLEST_DPLL fields */
  44. #define ST_DPLL_CLK_MASK 1
  45. /* CM_CLKSEL_DPLL */
  46. #define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24
  47. #define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24)
  48. #define CM_CLKSEL_DPLL_M_SHIFT 8
  49. #define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
  50. #define CM_CLKSEL_DPLL_N_SHIFT 0
  51. #define CM_CLKSEL_DPLL_N_MASK 0x7F
  52. #define CM_CLKSEL_DCC_EN_SHIFT 22
  53. #define CM_CLKSEL_DCC_EN_MASK (1 << 22)
  54. /* CM_SYS_CLKSEL */
  55. #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
  56. /* CM_CLKSEL_CORE */
  57. #define CLKSEL_CORE_SHIFT 0
  58. #define CLKSEL_L3_SHIFT 4
  59. #define CLKSEL_L4_SHIFT 8
  60. #define CLKSEL_CORE_X2_DIV_1 0
  61. #define CLKSEL_L3_CORE_DIV_2 1
  62. #define CLKSEL_L4_L3_DIV_2 1
  63. /* CM_ABE_PLL_REF_CLKSEL */
  64. #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0
  65. #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1
  66. #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
  67. #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
  68. /* CM_BYPCLK_DPLL_IVA */
  69. #define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
  70. #define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
  71. #define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1
  72. /* CM_SHADOW_FREQ_CONFIG1 */
  73. #define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
  74. #define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
  75. #define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
  76. #define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
  77. #define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
  78. #define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
  79. #define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
  80. /*CM_<clock_domain>__CLKCTRL */
  81. #define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
  82. #define CD_CLKCTRL_CLKTRCTRL_MASK 3
  83. #define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
  84. #define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
  85. #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
  86. #define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
  87. /* CM_<clock_domain>_<module>_CLKCTRL */
  88. #define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
  89. #define MODULE_CLKCTRL_MODULEMODE_MASK 3
  90. #define MODULE_CLKCTRL_IDLEST_SHIFT 16
  91. #define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
  92. #define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
  93. #define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
  94. #define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
  95. #define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
  96. #define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
  97. #define MODULE_CLKCTRL_IDLEST_IDLE 2
  98. #define MODULE_CLKCTRL_IDLEST_DISABLED 3
  99. /* CM_L4PER_GPIO4_CLKCTRL */
  100. #define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
  101. /* CM_L3INIT_HSMMCn_CLKCTRL */
  102. #define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
  103. /* CM_WKUP_GPTIMER1_CLKCTRL */
  104. #define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
  105. /* CM_CAM_ISS_CLKCTRL */
  106. #define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
  107. /* CM_DSS_DSS_CLKCTRL */
  108. #define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00
  109. /* CM_L3INIT_USBPHY_CLKCTRL */
  110. #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
  111. /* CM_MPU_MPU_CLKCTRL */
  112. #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
  113. #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
  114. #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25
  115. #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
  116. /* Clock frequencies */
  117. #define OMAP_SYS_CLK_IND_38_4_MHZ 6
  118. /* PRM_VC_VAL_BYPASS */
  119. #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
  120. /* PMIC */
  121. #define SMPS_I2C_SLAVE_ADDR 0x12
  122. /* TWL6030 SMPS */
  123. #define SMPS_REG_ADDR_VCORE1 0x55
  124. #define SMPS_REG_ADDR_VCORE2 0x5B
  125. #define SMPS_REG_ADDR_VCORE3 0x61
  126. /* TWL6032 SMPS */
  127. #define SMPS_REG_ADDR_SMPS1 0x55
  128. #define SMPS_REG_ADDR_SMPS2 0x5B
  129. #define SMPS_REG_ADDR_SMPS5 0x49
  130. #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700
  131. #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000
  132. /* TPS */
  133. #define TPS62361_I2C_SLAVE_ADDR 0x60
  134. #define TPS62361_REG_ADDR_SET0 0x0
  135. #define TPS62361_REG_ADDR_SET1 0x1
  136. #define TPS62361_REG_ADDR_SET2 0x2
  137. #define TPS62361_REG_ADDR_SET3 0x3
  138. #define TPS62361_REG_ADDR_CTRL 0x4
  139. #define TPS62361_REG_ADDR_TEMP 0x5
  140. #define TPS62361_REG_ADDR_RMP_CTRL 0x6
  141. #define TPS62361_REG_ADDR_CHIP_ID 0x8
  142. #define TPS62361_REG_ADDR_CHIP_ID_2 0x9
  143. #define TPS62361_BASE_VOLT_MV 500
  144. #define TPS62361_VSEL0_GPIO 7
  145. /* AUXCLKx reg fields */
  146. #define AUXCLK_ENABLE_MASK (1 << 8)
  147. #define AUXCLK_SRCSELECT_SHIFT 1
  148. #define AUXCLK_SRCSELECT_MASK (3 << 1)
  149. #define AUXCLK_CLKDIV_SHIFT 16
  150. #define AUXCLK_CLKDIV_MASK (0xF << 16)
  151. #define AUXCLK_SRCSELECT_SYS_CLK 0
  152. #define AUXCLK_SRCSELECT_CORE_DPLL 1
  153. #define AUXCLK_SRCSELECT_PER_DPLL 2
  154. #define AUXCLK_SRCSELECT_ALTERNATE 3
  155. #define AUXCLK_CLKDIV_2 1
  156. #define AUXCLK_CLKDIV_16 0xF
  157. /* ALTCLKSRC */
  158. #define ALTCLKSRC_MODE_MASK 3
  159. #define ALTCLKSRC_ENABLE_INT_MASK 4
  160. #define ALTCLKSRC_ENABLE_EXT_MASK 8
  161. #define ALTCLKSRC_MODE_ACTIVE 1
  162. #define DPLL_NO_LOCK 0
  163. #define DPLL_LOCK 1
  164. /* Clock Defines */
  165. #define V_OSCK 38400000 /* Clock output from T2 */
  166. #define V_SCLK V_OSCK
  167. struct omap4_scrm_regs {
  168. u32 revision; /* 0x0000 */
  169. u32 pad00[63];
  170. u32 clksetuptime; /* 0x0100 */
  171. u32 pmicsetuptime; /* 0x0104 */
  172. u32 pad01[2];
  173. u32 altclksrc; /* 0x0110 */
  174. u32 pad02[2];
  175. u32 c2cclkm; /* 0x011c */
  176. u32 pad03[56];
  177. u32 extclkreq; /* 0x0200 */
  178. u32 accclkreq; /* 0x0204 */
  179. u32 pwrreq; /* 0x0208 */
  180. u32 pad04[1];
  181. u32 auxclkreq0; /* 0x0210 */
  182. u32 auxclkreq1; /* 0x0214 */
  183. u32 auxclkreq2; /* 0x0218 */
  184. u32 auxclkreq3; /* 0x021c */
  185. u32 auxclkreq4; /* 0x0220 */
  186. u32 auxclkreq5; /* 0x0224 */
  187. u32 pad05[3];
  188. u32 c2cclkreq; /* 0x0234 */
  189. u32 pad06[54];
  190. u32 auxclk0; /* 0x0310 */
  191. u32 auxclk1; /* 0x0314 */
  192. u32 auxclk2; /* 0x0318 */
  193. u32 auxclk3; /* 0x031c */
  194. u32 auxclk4; /* 0x0320 */
  195. u32 auxclk5; /* 0x0324 */
  196. u32 pad07[54];
  197. u32 rsttime_reg; /* 0x0400 */
  198. u32 pad08[6];
  199. u32 c2crstctrl; /* 0x041c */
  200. u32 extpwronrstctrl; /* 0x0420 */
  201. u32 pad09[59];
  202. u32 extwarmrstst_reg; /* 0x0510 */
  203. u32 apewarmrstst_reg; /* 0x0514 */
  204. u32 pad10[1];
  205. u32 c2cwarmrstst_reg; /* 0x051C */
  206. };
  207. #endif /* _CLOCKS_OMAP4_H_ */