sama5d3.h 6.9 KB

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  1. /*
  2. * Chip-specific header file for the SAMA5D3 family
  3. *
  4. * (C) 2012 - 2013 Atmel Corporation.
  5. * Bo Shen <voice.shen@atmel.com>
  6. *
  7. * Definitions for the SoC:
  8. * SAMA5D3
  9. *
  10. * SPDX-License-Identifier: GPL-2.0+
  11. */
  12. #ifndef SAMA5D3_H
  13. #define SAMA5D3_H
  14. /*
  15. * defines to be used in other places
  16. */
  17. #define CONFIG_ARMV7 /* ARM A5 Core */
  18. #define CONFIG_AT91FAMILY /* it's a member of AT91 */
  19. /*
  20. * Peripheral identifiers/interrupts.
  21. */
  22. #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
  23. #define ATMEL_ID_SYS 1 /* System Controller Interrupt */
  24. #define ATMEL_ID_DBGU 2 /* Debug Unit Interrupt */
  25. #define ATMEL_ID_PIT 3 /* Periodic Interval Timer Interrupt */
  26. #define ATMEL_ID_WDT 4 /* Watchdog timer Interrupt */
  27. #define ATMEL_ID_SMC 5 /* Multi-bit ECC Interrupt */
  28. #define ATMEL_ID_PIOA 6 /* Parallel I/O Controller A */
  29. #define ATMEL_ID_PIOB 7 /* Parallel I/O Controller B */
  30. #define ATMEL_ID_PIOC 8 /* Parallel I/O Controller C */
  31. #define ATMEL_ID_PIOD 9 /* Parallel I/O Controller D */
  32. #define ATMEL_ID_PIOE 10 /* Parallel I/O Controller E */
  33. #define ATMEL_ID_SMD 11 /* SMD Soft Modem */
  34. #define ATMEL_ID_USART0 12 /* USART 0 */
  35. #define ATMEL_ID_USART1 13 /* USART 1 */
  36. #define ATMEL_ID_USART2 14 /* USART 2 */
  37. #define ATMEL_ID_USART3 15 /* USART 3 */
  38. #define ATMEL_ID_UART0 16
  39. #define ATMEL_ID_UART1 17
  40. #define ATMEL_ID_TWI0 18 /* Two-Wire Interface 0 */
  41. #define ATMEL_ID_TWI1 19 /* Two-Wire Interface 1 */
  42. #define ATMEL_ID_TWI2 20 /* Two-Wire Interface 2 */
  43. #define ATMEL_ID_MCI0 21 /* High Speed Multimedia Card Interface 0 */
  44. #define ATMEL_ID_MCI1 22 /* */
  45. #define ATMEL_ID_MCI2 23 /* */
  46. #define ATMEL_ID_SPI0 24 /* Serial Peripheral Interface 0 */
  47. #define ATMEL_ID_SPI1 25 /* Serial Peripheral Interface 1 */
  48. #define ATMEL_ID_TC0 26 /* */
  49. #define ATMEL_ID_TC1 27 /* */
  50. #define ATMEL_ID_PWMC 28 /* Pulse Width Modulation Controller */
  51. #define ATMEL_ID_TSC 29 /* Touch Screen ADC Controller */
  52. #define ATMEL_ID_DMA0 30 /* DMA Controller */
  53. #define ATMEL_ID_DMA1 31 /* DMA Controller */
  54. #define ATMEL_ID_UHPHS 32 /* USB Host High Speed */
  55. #define ATMEL_ID_UDPHS 33 /* USB Device High Speed */
  56. #define ATMEL_ID_GMAC 34
  57. #define ATMEL_ID_EMAC 35 /* Ethernet MAC */
  58. #define ATMEL_ID_LCDC 36 /* LCD Controller */
  59. #define ATMEL_ID_ISI 37 /* Image Sensor Interface */
  60. #define ATMEL_ID_SSC0 38 /* Synchronous Serial Controller 0 */
  61. #define ATMEL_ID_SSC1 39 /* Synchronous Serial Controller 1 */
  62. #define ATMEL_ID_CAN0 40
  63. #define ATMEL_ID_CAN1 41
  64. #define ATMEL_ID_SHA 42
  65. #define ATMEL_ID_AES 43
  66. #define ATMEL_ID_TDES 44
  67. #define ATMEL_ID_TRNG 45
  68. #define ATMEL_ID_ARM 46
  69. #define ATMEL_ID_IRQ0 47 /* Advanced Interrupt Controller */
  70. #define ATMEL_ID_FUSE 48
  71. #define ATMEL_ID_MPDDRC 49
  72. /* sama5d3 series chip id definitions */
  73. #define ARCH_ID_SAMA5D3 0x8a5c07c0
  74. #define ARCH_EXID_SAMA5D31 0x00444300
  75. #define ARCH_EXID_SAMA5D33 0x00414300
  76. #define ARCH_EXID_SAMA5D34 0x00414301
  77. #define ARCH_EXID_SAMA5D35 0x00584300
  78. #define cpu_is_sama5d3() (get_chip_id() == ARCH_ID_SAMA5D3)
  79. #define cpu_is_sama5d31() (cpu_is_sama5d3() && \
  80. (get_extension_chip_id() == ARCH_EXID_SAMA5D31))
  81. #define cpu_is_sama5d33() (cpu_is_sama5d3() && \
  82. (get_extension_chip_id() == ARCH_EXID_SAMA5D33))
  83. #define cpu_is_sama5d34() (cpu_is_sama5d3() && \
  84. (get_extension_chip_id() == ARCH_EXID_SAMA5D34))
  85. #define cpu_is_sama5d35() (cpu_is_sama5d3() && \
  86. (get_extension_chip_id() == ARCH_EXID_SAMA5D35))
  87. /*
  88. * User Peripherals physical base addresses.
  89. */
  90. #define ATMEL_BASE_MCI0 0xf0000000
  91. #define ATMEL_BASE_SPI0 0xf0004000
  92. #define ATMEL_BASE_SSC0 0xf000C000
  93. #define ATMEL_BASE_TC2 0xf0010000
  94. #define ATMEL_BASE_TWI0 0xf0014000
  95. #define ATMEL_BASE_TWI1 0xf0018000
  96. #define ATMEL_BASE_USART0 0xf001c000
  97. #define ATMEL_BASE_USART1 0xf0020000
  98. #define ATMEL_BASE_UART0 0xf0024000
  99. #define ATMEL_BASE_GMAC 0xf0028000
  100. #define ATMEL_BASE_PWMC 0xf002c000
  101. #define ATMEL_BASE_LCDC 0xf0030000
  102. #define ATMEL_BASE_ISI 0xf0034000
  103. #define ATMEL_BASE_SFR 0xf0038000
  104. /* Reserved: 0xf003c000 - 0xf8000000 */
  105. #define ATMEL_BASE_MCI1 0xf8000000
  106. #define ATMEL_BASE_MCI2 0xf8004000
  107. #define ATMEL_BASE_SPI1 0xf8008000
  108. #define ATMEL_BASE_SSC1 0xf800c000
  109. #define ATMEL_BASE_CAN1 0xf8010000
  110. #define ATMEL_BASE_TC3 0xf8014000
  111. #define ATMEL_BASE_TSADC 0xf8018000
  112. #define ATMEL_BASE_TWI2 0xf801c000
  113. #define ATMEL_BASE_USART2 0xf8020000
  114. #define ATMEL_BASE_USART3 0xf8024000
  115. #define ATMEL_BASE_UART1 0xf8028000
  116. #define ATMEL_BASE_EMAC 0xf802c000
  117. #define ATMEL_BASE_UDHPS 0xf8030000
  118. #define ATMEL_BASE_SHA 0xf8034000
  119. #define ATMEL_BASE_AES 0xf8038000
  120. #define ATMEL_BASE_TDES 0xf803c000
  121. #define ATMEL_BASE_TRNG 0xf8040000
  122. /* Reserved: 0xf804400 - 0xffffc00 */
  123. /*
  124. * System Peripherals physical base addresses.
  125. */
  126. #define ATMEL_BASE_SYS 0xffffc000
  127. #define ATMEL_BASE_SMC 0xffffc000
  128. #define ATMEL_BASE_PMECC (ATMEL_BASE_SMC + 0x070)
  129. #define ATMEL_BASE_PMERRLOC (ATMEL_BASE_SMC + 0x500)
  130. #define ATMEL_BASE_FUSE 0xffffe400
  131. #define ATMEL_BASE_DMAC0 0xffffe600
  132. #define ATMEL_BASE_DMAC1 0xffffe800
  133. #define ATMEL_BASE_MPDDRC 0xffffea00
  134. #define ATMEL_BASE_MATRIX 0xffffec00
  135. #define ATMEL_BASE_DBGU 0xffffee00
  136. #define ATMEL_BASE_AIC 0xfffff000
  137. #define ATMEL_BASE_PIOA 0xfffff200
  138. #define ATMEL_BASE_PIOB 0xfffff400
  139. #define ATMEL_BASE_PIOC 0xfffff600
  140. #define ATMEL_BASE_PIOD 0xfffff800
  141. #define ATMEL_BASE_PIOE 0xfffffa00
  142. #define ATMEL_BASE_PMC 0xfffffc00
  143. #define ATMEL_BASE_RSTC 0xfffffe00
  144. #define ATMEL_BASE_SHDWN 0xfffffe10
  145. #define ATMEL_BASE_PIT 0xfffffe30
  146. #define ATMEL_BASE_WDT 0xfffffe40
  147. #define ATMEL_BASE_SCKCR 0xfffffe50
  148. #define ATMEL_BASE_GPBR 0xfffffe60
  149. #define ATMEL_BASE_RTC 0xfffffeb0
  150. /* Reserved: 0xfffffee0 - 0xffffffff */
  151. /*
  152. * Internal Memory.
  153. */
  154. #define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */
  155. #define ATMEL_BASE_SRAM 0x00200000 /* Internal ROM base address */
  156. #define ATMEL_BASE_SRAM0 0x00300000 /* Internal SRAM base address */
  157. #define ATMEL_BASE_SRAM1 0x00310000 /* Internal SRAM base address */
  158. #define ATMEL_BASE_SMD 0x00400000 /* Internal ROM base address */
  159. #define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */
  160. #define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */
  161. #define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */
  162. #define ATMEL_BASE_AXI 0x00800000 /* Video Decoder Controller */
  163. #define ATMEL_BASE_DAP 0x00900000 /* Video Decoder Controller */
  164. /*
  165. * External memory
  166. */
  167. #define ATMEL_BASE_CS0 0x10000000
  168. #define ATMEL_BASE_DDRCS 0x20000000
  169. #define ATMEL_BASE_CS1 0x40000000
  170. #define ATMEL_BASE_CS2 0x50000000
  171. #define ATMEL_BASE_CS3 0x60000000
  172. /*
  173. * Other misc defines
  174. */
  175. #define ATMEL_PIO_PORTS 5
  176. #define CPU_HAS_PIO3
  177. #define PIO_SCDR_DIV 0x3fff
  178. /*
  179. * PMECC table in ROM
  180. */
  181. #define ATMEL_PMECC_INDEX_OFFSET_512 0x10000
  182. #define ATMEL_PMECC_INDEX_OFFSET_1024 0x18000
  183. /*
  184. * SAMA5D3 specific prototypes
  185. */
  186. #ifndef __ASSEMBLY__
  187. unsigned int get_chip_id(void);
  188. unsigned int get_extension_chip_id(void);
  189. unsigned int has_emac(void);
  190. unsigned int has_gmac(void);
  191. unsigned int has_lcdc(void);
  192. char *get_cpu_name(void);
  193. #endif
  194. #endif