at91sam9x5.h 6.1 KB

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  1. /*
  2. * Chip-specific header file for the AT91SAM9x5 family
  3. *
  4. * Copyright (C) 2012-2013 Atmel Corporation.
  5. *
  6. * Definitions for the SoC:
  7. * AT91SAM9x5 & AT91SAM9N12
  8. *
  9. * SPDX-License-Identifier: GPL-2.0+
  10. */
  11. #ifndef __AT91SAM9X5_H__
  12. #define __AT91SAM9X5_H__
  13. /*
  14. * Peripheral identifiers/interrupts.
  15. */
  16. #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
  17. #define ATMEL_ID_SYS 1 /* System Controller Interrupt */
  18. #define ATMEL_ID_PIOAB 2 /* Parallel I/O Controller A and B */
  19. #define ATMEL_ID_PIOCD 3 /* Parallel I/O Controller C and D */
  20. #define ATMEL_ID_SMD 4 /* SMD Soft Modem (SMD), only for AT91SAM9X5 */
  21. #define ATMEL_ID_FUSE 4 /* FUSE Controller, only for AT91SAM9N12 */
  22. #define ATMEL_ID_USART0 5 /* USART 0 */
  23. #define ATMEL_ID_USART1 6 /* USART 1 */
  24. #define ATMEL_ID_USART2 7 /* USART 2 */
  25. #define ATMEL_ID_USART3 8 /* USART 3 */
  26. #define ATMEL_ID_TWI0 9 /* Two-Wire Interface 0 */
  27. #define ATMEL_ID_TWI1 10 /* Two-Wire Interface 1 */
  28. #define ATMEL_ID_TWI2 11 /* Two-Wire Interface 2 */
  29. #define ATMEL_ID_HSMCI0 12 /* High Speed Multimedia Card Interface 0 */
  30. #define ATMEL_ID_SPI0 13 /* Serial Peripheral Interface 0 */
  31. #define ATMEL_ID_SPI1 14 /* Serial Peripheral Interface 1 */
  32. #define ATMEL_ID_UART0 15 /* UART 0 */
  33. #define ATMEL_ID_UART1 16 /* UART 1 */
  34. #define ATMEL_ID_TC01 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
  35. #define ATMEL_ID_PWM 18 /* Pulse Width Modulation Controller */
  36. #define ATMEL_ID_ADC 19 /* ADC Controller */
  37. #define ATMEL_ID_DMAC0 20 /* DMA Controller 0 */
  38. #define ATMEL_ID_DMAC1 21 /* DMA Controller 1 */
  39. #define ATMEL_ID_UHPHS 22 /* USB Host High Speed */
  40. #define ATMEL_ID_UDPHS 23 /* USB Device High Speed */
  41. #define ATMEL_ID_EMAC0 24 /* Ethernet MAC0 */
  42. #define ATMEL_ID_LCDC 25 /* LCD Controller */
  43. #define ATMEL_ID_HSMCI1 26 /* High Speed Multimedia Card Interface 1 */
  44. #define ATMEL_ID_EMAC1 27 /* Ethernet MAC1 */
  45. #define ATMEL_ID_SSC 28 /* Synchronous Serial Controller */
  46. #define ATMEL_ID_TRNG 30 /* True Random Number Generator */
  47. #define ATMEL_ID_IRQ 31 /* Advanced Interrupt Controller */
  48. /*
  49. * User Peripheral physical base addresses.
  50. */
  51. #define ATMEL_BASE_SPI0 0xf0000000
  52. #define ATMEL_BASE_SPI1 0xf0004000
  53. #define ATMEL_BASE_HSMCI0 0xf0008000
  54. #define ATMEL_BASE_HSMCI1 0xf000c000
  55. #define ATMEL_BASE_SSC 0xf0010000
  56. #define ATMEL_BASE_CAN0 0xf8000000
  57. #define ATMEL_BASE_CAN1 0xf8004000
  58. #define ATMEL_BASE_TC0 0xf8008000
  59. #define ATMEL_BASE_TC1 0xf8008040
  60. #define ATMEL_BASE_TC2 0xf8008080
  61. #define ATMEL_BASE_TC3 0xf800c000
  62. #define ATMEL_BASE_TC4 0xf800c040
  63. #define ATMEL_BASE_TC5 0xf800c080
  64. #define ATMEL_BASE_TWI0 0xf8010000
  65. #define ATMEL_BASE_TWI1 0xf8014000
  66. #define ATMEL_BASE_TWI2 0xf8018000
  67. #define ATMEL_BASE_USART0 0xf801c000
  68. #define ATMEL_BASE_USART1 0xf8020000
  69. #define ATMEL_BASE_USART2 0xf8024000
  70. #define ATMEL_BASE_USART3 0xf8028000
  71. #define ATMEL_BASE_EMAC0 0xf802c000
  72. #define ATMEL_BASE_EMAC1 0xf8030000
  73. #define ATMEL_BASE_PWM 0xf8034000
  74. #define ATMEL_BASE_LCDC 0xf8038000
  75. #define ATMEL_BASE_UDPHS 0xf803c000
  76. #define ATMEL_BASE_UART0 0xf8040000
  77. #define ATMEL_BASE_UART1 0xf8044000
  78. #define ATMEL_BASE_ISI 0xf8048000
  79. #define ATMEL_BASE_ADC 0xf804c000
  80. #define ATMEL_BASE_SYS 0xffffc000
  81. /*
  82. * System Peripherals
  83. */
  84. #define ATMEL_BASE_FUSE 0xffffdc00
  85. #define ATMEL_BASE_MATRIX 0xffffde00
  86. #define ATMEL_BASE_PMECC 0xffffe000
  87. #define ATMEL_BASE_PMERRLOC 0xffffe600
  88. #define ATMEL_BASE_DDRSDRC 0xffffe800
  89. #define ATMEL_BASE_SMC 0xffffea00
  90. #define ATMEL_BASE_DMAC0 0xffffec00
  91. #define ATMEL_BASE_DMAC1 0xffffee00
  92. #define ATMEL_BASE_AIC 0xfffff000
  93. #define ATMEL_BASE_DBGU 0xfffff200
  94. #define ATMEL_BASE_PIOA 0xfffff400
  95. #define ATMEL_BASE_PIOB 0xfffff600
  96. #define ATMEL_BASE_PIOC 0xfffff800
  97. #define ATMEL_BASE_PIOD 0xfffffa00
  98. #define ATMEL_BASE_PMC 0xfffffc00
  99. #define ATMEL_BASE_RSTC 0xfffffe00
  100. #define ATMEL_BASE_SHDWC 0xfffffe10
  101. #define ATMEL_BASE_PIT 0xfffffe30
  102. #define ATMEL_BASE_WDT 0xfffffe40
  103. #define ATMEL_BASE_GPBR 0xfffffe60
  104. #define ATMEL_BASE_RTC 0xfffffeb0
  105. /*
  106. * Internal Memory.
  107. */
  108. #define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */
  109. #define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */
  110. #ifdef CONFIG_AT91SAM9N12
  111. #define ATMEL_BASE_OHCI 0x00500000 /* USB Host controller */
  112. #else /* AT91SAM9X5 */
  113. #define ATMEL_BASE_SMD 0x00400000 /* SMD Controller */
  114. #define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */
  115. #define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */
  116. #define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */
  117. #endif
  118. /* 9x5 series chip id definitions */
  119. #define ARCH_ID_AT91SAM9X5 0x819a05a0
  120. #define ARCH_ID_VERSION_MASK 0x1f
  121. #define ARCH_EXID_AT91SAM9G15 0x00000000
  122. #define ARCH_EXID_AT91SAM9G35 0x00000001
  123. #define ARCH_EXID_AT91SAM9X35 0x00000002
  124. #define ARCH_EXID_AT91SAM9G25 0x00000003
  125. #define ARCH_EXID_AT91SAM9X25 0x00000004
  126. #define cpu_is_at91sam9x5() (get_chip_id() == ARCH_ID_AT91SAM9X5)
  127. #define cpu_is_at91sam9g15() (cpu_is_at91sam9x5() && \
  128. (get_extension_chip_id() == ARCH_EXID_AT91SAM9G15))
  129. #define cpu_is_at91sam9g25() (cpu_is_at91sam9x5() && \
  130. (get_extension_chip_id() == ARCH_EXID_AT91SAM9G25))
  131. #define cpu_is_at91sam9g35() (cpu_is_at91sam9x5() && \
  132. (get_extension_chip_id() == ARCH_EXID_AT91SAM9G35))
  133. #define cpu_is_at91sam9x25() (cpu_is_at91sam9x5() && \
  134. (get_extension_chip_id() == ARCH_EXID_AT91SAM9X25))
  135. #define cpu_is_at91sam9x35() (cpu_is_at91sam9x5() && \
  136. (get_extension_chip_id() == ARCH_EXID_AT91SAM9X35))
  137. /*
  138. * Cpu Name
  139. */
  140. #ifdef CONFIG_AT91SAM9N12
  141. #define ATMEL_CPU_NAME "AT91SAM9N12"
  142. #else /* AT91SAM9X5 */
  143. #define ATMEL_CPU_NAME get_cpu_name()
  144. #endif
  145. /*
  146. * Other misc defines
  147. */
  148. #define ATMEL_PIO_PORTS 4
  149. #define CPU_HAS_PIO3
  150. #define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */
  151. #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
  152. #define ATMEL_ID_UHP ATMEL_ID_UHPHS
  153. /*
  154. * PMECC table in ROM
  155. */
  156. #define ATMEL_PMECC_INDEX_OFFSET_512 0x8000
  157. #define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000
  158. /*
  159. * at91sam9x5 specific prototypes
  160. */
  161. #ifndef __ASSEMBLY__
  162. unsigned int get_chip_id(void);
  163. unsigned int get_extension_chip_id(void);
  164. unsigned int has_emac1(void);
  165. unsigned int has_emac0(void);
  166. unsigned int has_lcdc(void);
  167. char *get_cpu_name(void);
  168. #endif
  169. #endif