hardware_am33xx.h 1.5 KB

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  1. /*
  2. * hardware_am33xx.h
  3. *
  4. * AM33xx hardware specific header
  5. *
  6. * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #ifndef __AM33XX_HARDWARE_AM33XX_H
  11. #define __AM33XX_HARDWARE_AM33XX_H
  12. /* Module base addresses */
  13. /* UART Base Address */
  14. #define UART0_BASE 0x44E09000
  15. /* GPIO Base address */
  16. #define GPIO2_BASE 0x481AC000
  17. /* Watchdog Timer */
  18. #define WDT_BASE 0x44E35000
  19. /* Control Module Base Address */
  20. #define CTRL_BASE 0x44E10000
  21. #define CTRL_DEVICE_BASE 0x44E10600
  22. /* PRCM Base Address */
  23. #define PRCM_BASE 0x44E00000
  24. #define CM_PER 0x44E00000
  25. #define CM_WKUP 0x44E00400
  26. #define PRM_RSTCTRL (PRCM_BASE + 0x0F00)
  27. #define PRM_RSTST (PRM_RSTCTRL + 8)
  28. /* VTP Base address */
  29. #define VTP0_CTRL_ADDR 0x44E10E0C
  30. #define VTP1_CTRL_ADDR 0x48140E10
  31. /* DDR Base address */
  32. #define DDR_PHY_CMD_ADDR 0x44E12000
  33. #define DDR_PHY_DATA_ADDR 0x44E120C8
  34. #define DDR_PHY_CMD_ADDR2 0x47C0C800
  35. #define DDR_PHY_DATA_ADDR2 0x47C0C8C8
  36. #define DDR_DATA_REGS_NR 2
  37. #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
  38. #define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
  39. /* CPSW Config space */
  40. #define CPSW_MDIO_BASE 0x4A101000
  41. /* RTC base address */
  42. #define RTC_BASE 0x44E3E000
  43. /* OTG */
  44. #define USB0_OTG_BASE 0x47401000
  45. #define USB1_OTG_BASE 0x47401800
  46. /* LCD Controller */
  47. #define LCD_CNTL_BASE 0x4830E000
  48. /* PWMSS */
  49. #define PWMSS0_BASE 0x48300000
  50. #define AM33XX_ECAP0_BASE 0x48300100
  51. #endif /* __AM33XX_HARDWARE_AM33XX_H */