cpu.h 17 KB

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  1. /*
  2. * cpu.h
  3. *
  4. * AM33xx specific header file
  5. *
  6. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #ifndef _AM33XX_CPU_H
  11. #define _AM33XX_CPU_H
  12. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  13. #include <asm/types.h>
  14. #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
  15. #include <asm/arch/hardware.h>
  16. #define BIT(x) (1 << x)
  17. #define CL_BIT(x) (0 << x)
  18. /* Timer register bits */
  19. #define TCLR_ST BIT(0) /* Start=1 Stop=0 */
  20. #define TCLR_AR BIT(1) /* Auto reload */
  21. #define TCLR_PRE BIT(5) /* Pre-scaler enable */
  22. #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
  23. #define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
  24. /* device type */
  25. #define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
  26. #define TST_DEVICE 0x0
  27. #define EMU_DEVICE 0x1
  28. #define HS_DEVICE 0x2
  29. #define GP_DEVICE 0x3
  30. /* cpu-id for AM33XX and TI81XX family */
  31. #define AM335X 0xB944
  32. #define TI81XX 0xB81E
  33. #define DEVICE_ID (CTRL_BASE + 0x0600)
  34. /* This gives the status of the boot mode pins on the evm */
  35. #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
  36. | BIT(3) | BIT(4))
  37. #define PRM_RSTCTRL_RESET 0x01
  38. #define PRM_RSTST_WARM_RESET_MASK 0x232
  39. /*
  40. * Watchdog:
  41. * Using the prescaler, the OMAP watchdog could go for many
  42. * months before firing. These limits work without scaling,
  43. * with the 60 second default assumed by most tools and docs.
  44. */
  45. #define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */
  46. #define TIMER_MARGIN_DEFAULT 60 /* 60 secs */
  47. #define TIMER_MARGIN_MIN 1
  48. #define PTV 0 /* prescale */
  49. #define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
  50. #define WDT_WWPS_PEND_WCLR BIT(0)
  51. #define WDT_WWPS_PEND_WLDR BIT(2)
  52. #define WDT_WWPS_PEND_WTGR BIT(3)
  53. #define WDT_WWPS_PEND_WSPR BIT(4)
  54. #define WDT_WCLR_PRE BIT(5)
  55. #define WDT_WCLR_PTV_OFF 2
  56. #ifndef __KERNEL_STRICT_NAMES
  57. #ifndef __ASSEMBLY__
  58. struct gpmc_cs {
  59. u32 config1; /* 0x00 */
  60. u32 config2; /* 0x04 */
  61. u32 config3; /* 0x08 */
  62. u32 config4; /* 0x0C */
  63. u32 config5; /* 0x10 */
  64. u32 config6; /* 0x14 */
  65. u32 config7; /* 0x18 */
  66. u32 nand_cmd; /* 0x1C */
  67. u32 nand_adr; /* 0x20 */
  68. u32 nand_dat; /* 0x24 */
  69. u8 res[8]; /* blow up to 0x30 byte */
  70. };
  71. struct bch_res_0_3 {
  72. u32 bch_result_x[4];
  73. };
  74. struct gpmc {
  75. u8 res1[0x10];
  76. u32 sysconfig; /* 0x10 */
  77. u8 res2[0x4];
  78. u32 irqstatus; /* 0x18 */
  79. u32 irqenable; /* 0x1C */
  80. u8 res3[0x20];
  81. u32 timeout_control; /* 0x40 */
  82. u8 res4[0xC];
  83. u32 config; /* 0x50 */
  84. u32 status; /* 0x54 */
  85. u8 res5[0x8]; /* 0x58 */
  86. struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
  87. u8 res6[0x14]; /* 0x1E0 */
  88. u32 ecc_config; /* 0x1F4 */
  89. u32 ecc_control; /* 0x1F8 */
  90. u32 ecc_size_config; /* 0x1FC */
  91. u32 ecc1_result; /* 0x200 */
  92. u32 ecc2_result; /* 0x204 */
  93. u32 ecc3_result; /* 0x208 */
  94. u32 ecc4_result; /* 0x20C */
  95. u32 ecc5_result; /* 0x210 */
  96. u32 ecc6_result; /* 0x214 */
  97. u32 ecc7_result; /* 0x218 */
  98. u32 ecc8_result; /* 0x21C */
  99. u32 ecc9_result; /* 0x220 */
  100. u8 res7[12]; /* 0x224 */
  101. u32 testmomde_ctrl; /* 0x230 */
  102. u8 res8[12]; /* 0x234 */
  103. struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */
  104. };
  105. /* Used for board specific gpmc initialization */
  106. extern struct gpmc *gpmc_cfg;
  107. #ifndef CONFIG_AM43XX
  108. /* Encapsulating core pll registers */
  109. struct cm_wkuppll {
  110. unsigned int wkclkstctrl; /* offset 0x00 */
  111. unsigned int wkctrlclkctrl; /* offset 0x04 */
  112. unsigned int wkgpio0clkctrl; /* offset 0x08 */
  113. unsigned int wkl4wkclkctrl; /* offset 0x0c */
  114. unsigned int resv2[4];
  115. unsigned int idlestdpllmpu; /* offset 0x20 */
  116. unsigned int resv3[2];
  117. unsigned int clkseldpllmpu; /* offset 0x2c */
  118. unsigned int resv4[1];
  119. unsigned int idlestdpllddr; /* offset 0x34 */
  120. unsigned int resv5[2];
  121. unsigned int clkseldpllddr; /* offset 0x40 */
  122. unsigned int resv6[4];
  123. unsigned int clkseldplldisp; /* offset 0x54 */
  124. unsigned int resv7[1];
  125. unsigned int idlestdpllcore; /* offset 0x5c */
  126. unsigned int resv8[2];
  127. unsigned int clkseldpllcore; /* offset 0x68 */
  128. unsigned int resv9[1];
  129. unsigned int idlestdpllper; /* offset 0x70 */
  130. unsigned int resv10[2];
  131. unsigned int clkdcoldodpllper; /* offset 0x7c */
  132. unsigned int divm4dpllcore; /* offset 0x80 */
  133. unsigned int divm5dpllcore; /* offset 0x84 */
  134. unsigned int clkmoddpllmpu; /* offset 0x88 */
  135. unsigned int clkmoddpllper; /* offset 0x8c */
  136. unsigned int clkmoddpllcore; /* offset 0x90 */
  137. unsigned int clkmoddpllddr; /* offset 0x94 */
  138. unsigned int clkmoddplldisp; /* offset 0x98 */
  139. unsigned int clkseldpllper; /* offset 0x9c */
  140. unsigned int divm2dpllddr; /* offset 0xA0 */
  141. unsigned int divm2dplldisp; /* offset 0xA4 */
  142. unsigned int divm2dpllmpu; /* offset 0xA8 */
  143. unsigned int divm2dpllper; /* offset 0xAC */
  144. unsigned int resv11[1];
  145. unsigned int wkup_uart0ctrl; /* offset 0xB4 */
  146. unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
  147. unsigned int resv12[7];
  148. unsigned int divm6dpllcore; /* offset 0xD8 */
  149. };
  150. /**
  151. * Encapsulating peripheral functional clocks
  152. * pll registers
  153. */
  154. struct cm_perpll {
  155. unsigned int l4lsclkstctrl; /* offset 0x00 */
  156. unsigned int l3sclkstctrl; /* offset 0x04 */
  157. unsigned int l4fwclkstctrl; /* offset 0x08 */
  158. unsigned int l3clkstctrl; /* offset 0x0c */
  159. unsigned int resv1;
  160. unsigned int cpgmac0clkctrl; /* offset 0x14 */
  161. unsigned int lcdclkctrl; /* offset 0x18 */
  162. unsigned int usb0clkctrl; /* offset 0x1C */
  163. unsigned int resv2;
  164. unsigned int tptc0clkctrl; /* offset 0x24 */
  165. unsigned int emifclkctrl; /* offset 0x28 */
  166. unsigned int ocmcramclkctrl; /* offset 0x2c */
  167. unsigned int gpmcclkctrl; /* offset 0x30 */
  168. unsigned int mcasp0clkctrl; /* offset 0x34 */
  169. unsigned int uart5clkctrl; /* offset 0x38 */
  170. unsigned int mmc0clkctrl; /* offset 0x3C */
  171. unsigned int elmclkctrl; /* offset 0x40 */
  172. unsigned int i2c2clkctrl; /* offset 0x44 */
  173. unsigned int i2c1clkctrl; /* offset 0x48 */
  174. unsigned int spi0clkctrl; /* offset 0x4C */
  175. unsigned int spi1clkctrl; /* offset 0x50 */
  176. unsigned int resv3[3];
  177. unsigned int l4lsclkctrl; /* offset 0x60 */
  178. unsigned int l4fwclkctrl; /* offset 0x64 */
  179. unsigned int mcasp1clkctrl; /* offset 0x68 */
  180. unsigned int uart1clkctrl; /* offset 0x6C */
  181. unsigned int uart2clkctrl; /* offset 0x70 */
  182. unsigned int uart3clkctrl; /* offset 0x74 */
  183. unsigned int uart4clkctrl; /* offset 0x78 */
  184. unsigned int timer7clkctrl; /* offset 0x7C */
  185. unsigned int timer2clkctrl; /* offset 0x80 */
  186. unsigned int timer3clkctrl; /* offset 0x84 */
  187. unsigned int timer4clkctrl; /* offset 0x88 */
  188. unsigned int resv4[8];
  189. unsigned int gpio1clkctrl; /* offset 0xAC */
  190. unsigned int gpio2clkctrl; /* offset 0xB0 */
  191. unsigned int gpio3clkctrl; /* offset 0xB4 */
  192. unsigned int resv5;
  193. unsigned int tpccclkctrl; /* offset 0xBC */
  194. unsigned int dcan0clkctrl; /* offset 0xC0 */
  195. unsigned int dcan1clkctrl; /* offset 0xC4 */
  196. unsigned int resv6[2];
  197. unsigned int emiffwclkctrl; /* offset 0xD0 */
  198. unsigned int epwmss0clkctrl; /* offset 0xD4 */
  199. unsigned int epwmss2clkctrl; /* offset 0xD8 */
  200. unsigned int l3instrclkctrl; /* offset 0xDC */
  201. unsigned int l3clkctrl; /* Offset 0xE0 */
  202. unsigned int resv8[4];
  203. unsigned int mmc1clkctrl; /* offset 0xF4 */
  204. unsigned int mmc2clkctrl; /* offset 0xF8 */
  205. unsigned int resv9[8];
  206. unsigned int l4hsclkstctrl; /* offset 0x11C */
  207. unsigned int l4hsclkctrl; /* offset 0x120 */
  208. unsigned int resv10[8];
  209. unsigned int cpswclkstctrl; /* offset 0x144 */
  210. unsigned int lcdcclkstctrl; /* offset 0x148 */
  211. };
  212. #else
  213. /* Encapsulating core pll registers */
  214. struct cm_wkuppll {
  215. unsigned int resv0[136];
  216. unsigned int wkl4wkclkctrl; /* offset 0x220 */
  217. unsigned int resv1[55];
  218. unsigned int wkclkstctrl; /* offset 0x300 */
  219. unsigned int resv2[15];
  220. unsigned int wkup_i2c0ctrl; /* offset 0x340 */
  221. unsigned int resv3;
  222. unsigned int wkup_uart0ctrl; /* offset 0x348 */
  223. unsigned int resv4[5];
  224. unsigned int wkctrlclkctrl; /* offset 0x360 */
  225. unsigned int resv5;
  226. unsigned int wkgpio0clkctrl; /* offset 0x368 */
  227. unsigned int resv6[109];
  228. unsigned int clkmoddpllcore; /* offset 0x520 */
  229. unsigned int idlestdpllcore; /* offset 0x524 */
  230. unsigned int resv61;
  231. unsigned int clkseldpllcore; /* offset 0x52C */
  232. unsigned int resv7[2];
  233. unsigned int divm4dpllcore; /* offset 0x538 */
  234. unsigned int divm5dpllcore; /* offset 0x53C */
  235. unsigned int divm6dpllcore; /* offset 0x540 */
  236. unsigned int resv8[7];
  237. unsigned int clkmoddpllmpu; /* offset 0x560 */
  238. unsigned int idlestdpllmpu; /* offset 0x564 */
  239. unsigned int resv9;
  240. unsigned int clkseldpllmpu; /* offset 0x56c */
  241. unsigned int divm2dpllmpu; /* offset 0x570 */
  242. unsigned int resv10[11];
  243. unsigned int clkmoddpllddr; /* offset 0x5A0 */
  244. unsigned int idlestdpllddr; /* offset 0x5A4 */
  245. unsigned int resv11;
  246. unsigned int clkseldpllddr; /* offset 0x5AC */
  247. unsigned int divm2dpllddr; /* offset 0x5B0 */
  248. unsigned int resv12[11];
  249. unsigned int clkmoddpllper; /* offset 0x5E0 */
  250. unsigned int idlestdpllper; /* offset 0x5E4 */
  251. unsigned int resv13;
  252. unsigned int clkseldpllper; /* offset 0x5EC */
  253. unsigned int divm2dpllper; /* offset 0x5F0 */
  254. unsigned int resv14[8];
  255. unsigned int clkdcoldodpllper; /* offset 0x614 */
  256. unsigned int resv15[2];
  257. unsigned int clkmoddplldisp; /* offset 0x620 */
  258. unsigned int resv16[2];
  259. unsigned int clkseldplldisp; /* offset 0x62C */
  260. unsigned int divm2dplldisp; /* offset 0x630 */
  261. };
  262. /*
  263. * Encapsulating peripheral functional clocks
  264. * pll registers
  265. */
  266. struct cm_perpll {
  267. unsigned int l3clkstctrl; /* offset 0x00 */
  268. unsigned int resv0[7];
  269. unsigned int l3clkctrl; /* Offset 0x20 */
  270. unsigned int resv1[7];
  271. unsigned int l3instrclkctrl; /* offset 0x40 */
  272. unsigned int resv2[3];
  273. unsigned int ocmcramclkctrl; /* offset 0x50 */
  274. unsigned int resv3[9];
  275. unsigned int tpccclkctrl; /* offset 0x78 */
  276. unsigned int resv4;
  277. unsigned int tptc0clkctrl; /* offset 0x80 */
  278. unsigned int resv5[7];
  279. unsigned int l4hsclkctrl; /* offset 0x0A0 */
  280. unsigned int resv6;
  281. unsigned int l4fwclkctrl; /* offset 0x0A8 */
  282. unsigned int resv7[85];
  283. unsigned int l3sclkstctrl; /* offset 0x200 */
  284. unsigned int resv8[7];
  285. unsigned int gpmcclkctrl; /* offset 0x220 */
  286. unsigned int resv9[5];
  287. unsigned int mcasp0clkctrl; /* offset 0x238 */
  288. unsigned int resv10;
  289. unsigned int mcasp1clkctrl; /* offset 0x240 */
  290. unsigned int resv11;
  291. unsigned int mmc2clkctrl; /* offset 0x248 */
  292. unsigned int resv12[5];
  293. unsigned int usb0clkctrl; /* offset 0x260 */
  294. unsigned int resv13[103];
  295. unsigned int l4lsclkstctrl; /* offset 0x400 */
  296. unsigned int resv14[7];
  297. unsigned int l4lsclkctrl; /* offset 0x420 */
  298. unsigned int resv15;
  299. unsigned int dcan0clkctrl; /* offset 0x428 */
  300. unsigned int resv16;
  301. unsigned int dcan1clkctrl; /* offset 0x430 */
  302. unsigned int resv17[13];
  303. unsigned int elmclkctrl; /* offset 0x468 */
  304. unsigned int resv18[3];
  305. unsigned int gpio1clkctrl; /* offset 0x478 */
  306. unsigned int resv19;
  307. unsigned int gpio2clkctrl; /* offset 0x480 */
  308. unsigned int resv20;
  309. unsigned int gpio3clkctrl; /* offset 0x488 */
  310. unsigned int resv21[7];
  311. unsigned int i2c1clkctrl; /* offset 0x4A8 */
  312. unsigned int resv22;
  313. unsigned int i2c2clkctrl; /* offset 0x4B0 */
  314. unsigned int resv23[3];
  315. unsigned int mmc0clkctrl; /* offset 0x4C0 */
  316. unsigned int resv24;
  317. unsigned int mmc1clkctrl; /* offset 0x4C8 */
  318. unsigned int resv25[13];
  319. unsigned int spi0clkctrl; /* offset 0x500 */
  320. unsigned int resv26;
  321. unsigned int spi1clkctrl; /* offset 0x508 */
  322. unsigned int resv27[9];
  323. unsigned int timer2clkctrl; /* offset 0x530 */
  324. unsigned int resv28;
  325. unsigned int timer3clkctrl; /* offset 0x538 */
  326. unsigned int resv29;
  327. unsigned int timer4clkctrl; /* offset 0x540 */
  328. unsigned int resv30[5];
  329. unsigned int timer7clkctrl; /* offset 0x558 */
  330. unsigned int resv31[9];
  331. unsigned int uart1clkctrl; /* offset 0x580 */
  332. unsigned int resv32;
  333. unsigned int uart2clkctrl; /* offset 0x588 */
  334. unsigned int resv33;
  335. unsigned int uart3clkctrl; /* offset 0x590 */
  336. unsigned int resv34;
  337. unsigned int uart4clkctrl; /* offset 0x598 */
  338. unsigned int resv35;
  339. unsigned int uart5clkctrl; /* offset 0x5A0 */
  340. unsigned int resv36[87];
  341. unsigned int emifclkstctrl; /* offset 0x700 */
  342. unsigned int resv361[7];
  343. unsigned int emifclkctrl; /* offset 0x720 */
  344. unsigned int resv37[3];
  345. unsigned int emiffwclkctrl; /* offset 0x730 */
  346. unsigned int resv371;
  347. unsigned int otfaemifclkctrl; /* offset 0x738 */
  348. unsigned int resv38[57];
  349. unsigned int lcdclkctrl; /* offset 0x820 */
  350. unsigned int resv39[183];
  351. unsigned int cpswclkstctrl; /* offset 0xB00 */
  352. unsigned int resv40[7];
  353. unsigned int cpgmac0clkctrl; /* offset 0xB20 */
  354. };
  355. #endif /* CONFIG_AM43XX */
  356. /* Encapsulating Display pll registers */
  357. struct cm_dpll {
  358. unsigned int resv1[2];
  359. unsigned int clktimer2clk; /* offset 0x08 */
  360. unsigned int resv2[10];
  361. unsigned int clklcdcpixelclk; /* offset 0x34 */
  362. };
  363. /* Control Module RTC registers */
  364. struct cm_rtc {
  365. unsigned int rtcclkctrl; /* offset 0x0 */
  366. unsigned int clkstctrl; /* offset 0x4 */
  367. };
  368. /* Watchdog timer registers */
  369. struct wd_timer {
  370. unsigned int resv1[4];
  371. unsigned int wdtwdsc; /* offset 0x010 */
  372. unsigned int wdtwdst; /* offset 0x014 */
  373. unsigned int wdtwisr; /* offset 0x018 */
  374. unsigned int wdtwier; /* offset 0x01C */
  375. unsigned int wdtwwer; /* offset 0x020 */
  376. unsigned int wdtwclr; /* offset 0x024 */
  377. unsigned int wdtwcrr; /* offset 0x028 */
  378. unsigned int wdtwldr; /* offset 0x02C */
  379. unsigned int wdtwtgr; /* offset 0x030 */
  380. unsigned int wdtwwps; /* offset 0x034 */
  381. unsigned int resv2[3];
  382. unsigned int wdtwdly; /* offset 0x044 */
  383. unsigned int wdtwspr; /* offset 0x048 */
  384. unsigned int resv3[1];
  385. unsigned int wdtwqeoi; /* offset 0x050 */
  386. unsigned int wdtwqstar; /* offset 0x054 */
  387. unsigned int wdtwqsta; /* offset 0x058 */
  388. unsigned int wdtwqens; /* offset 0x05C */
  389. unsigned int wdtwqenc; /* offset 0x060 */
  390. unsigned int resv4[39];
  391. unsigned int wdt_unfr; /* offset 0x100 */
  392. };
  393. /* Timer 32 bit registers */
  394. struct gptimer {
  395. unsigned int tidr; /* offset 0x00 */
  396. unsigned char res1[12];
  397. unsigned int tiocp_cfg; /* offset 0x10 */
  398. unsigned char res2[12];
  399. unsigned int tier; /* offset 0x20 */
  400. unsigned int tistatr; /* offset 0x24 */
  401. unsigned int tistat; /* offset 0x28 */
  402. unsigned int tisr; /* offset 0x2c */
  403. unsigned int tcicr; /* offset 0x30 */
  404. unsigned int twer; /* offset 0x34 */
  405. unsigned int tclr; /* offset 0x38 */
  406. unsigned int tcrr; /* offset 0x3c */
  407. unsigned int tldr; /* offset 0x40 */
  408. unsigned int ttgr; /* offset 0x44 */
  409. unsigned int twpc; /* offset 0x48 */
  410. unsigned int tmar; /* offset 0x4c */
  411. unsigned int tcar1; /* offset 0x50 */
  412. unsigned int tscir; /* offset 0x54 */
  413. unsigned int tcar2; /* offset 0x58 */
  414. };
  415. /* RTC Registers */
  416. struct rtc_regs {
  417. unsigned int res[21];
  418. unsigned int osc; /* offset 0x54 */
  419. unsigned int res2[5];
  420. unsigned int kick0r; /* offset 0x6c */
  421. unsigned int kick1r; /* offset 0x70 */
  422. };
  423. /* UART Registers */
  424. struct uart_sys {
  425. unsigned int resv1[21];
  426. unsigned int uartsyscfg; /* offset 0x54 */
  427. unsigned int uartsyssts; /* offset 0x58 */
  428. };
  429. /* VTP Registers */
  430. struct vtp_reg {
  431. unsigned int vtp0ctrlreg;
  432. };
  433. /* Control Status Register */
  434. struct ctrl_stat {
  435. unsigned int resv1[16];
  436. unsigned int statusreg; /* ofset 0x40 */
  437. unsigned int resv2[51];
  438. unsigned int secure_emif_sdram_config; /* offset 0x0110 */
  439. };
  440. /* AM33XX GPIO registers */
  441. #define OMAP_GPIO_REVISION 0x0000
  442. #define OMAP_GPIO_SYSCONFIG 0x0010
  443. #define OMAP_GPIO_SYSSTATUS 0x0114
  444. #define OMAP_GPIO_IRQSTATUS1 0x002c
  445. #define OMAP_GPIO_IRQSTATUS2 0x0030
  446. #define OMAP_GPIO_CTRL 0x0130
  447. #define OMAP_GPIO_OE 0x0134
  448. #define OMAP_GPIO_DATAIN 0x0138
  449. #define OMAP_GPIO_DATAOUT 0x013c
  450. #define OMAP_GPIO_LEVELDETECT0 0x0140
  451. #define OMAP_GPIO_LEVELDETECT1 0x0144
  452. #define OMAP_GPIO_RISINGDETECT 0x0148
  453. #define OMAP_GPIO_FALLINGDETECT 0x014c
  454. #define OMAP_GPIO_DEBOUNCE_EN 0x0150
  455. #define OMAP_GPIO_DEBOUNCE_VAL 0x0154
  456. #define OMAP_GPIO_CLEARDATAOUT 0x0190
  457. #define OMAP_GPIO_SETDATAOUT 0x0194
  458. /* Control Device Register */
  459. struct ctrl_dev {
  460. unsigned int deviceid; /* offset 0x00 */
  461. unsigned int resv1[7];
  462. unsigned int usb_ctrl0; /* offset 0x20 */
  463. unsigned int resv2;
  464. unsigned int usb_ctrl1; /* offset 0x28 */
  465. unsigned int resv3;
  466. unsigned int macid0l; /* offset 0x30 */
  467. unsigned int macid0h; /* offset 0x34 */
  468. unsigned int macid1l; /* offset 0x38 */
  469. unsigned int macid1h; /* offset 0x3c */
  470. unsigned int resv4[4];
  471. unsigned int miisel; /* offset 0x50 */
  472. };
  473. /* gmii_sel register defines */
  474. #define GMII1_SEL_MII 0x0
  475. #define GMII1_SEL_RMII 0x1
  476. #define GMII1_SEL_RGMII 0x2
  477. #define GMII2_SEL_MII 0x0
  478. #define GMII2_SEL_RMII 0x4
  479. #define GMII2_SEL_RGMII 0x8
  480. #define RGMII1_IDMODE BIT(4)
  481. #define RGMII2_IDMODE BIT(5)
  482. #define RMII1_IO_CLK_EN BIT(6)
  483. #define RMII2_IO_CLK_EN BIT(7)
  484. #define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII)
  485. #define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII)
  486. #define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
  487. #define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE)
  488. #define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
  489. /* PWMSS */
  490. struct pwmss_regs {
  491. unsigned int idver;
  492. unsigned int sysconfig;
  493. unsigned int clkconfig;
  494. unsigned int clkstatus;
  495. };
  496. #define ECAP_CLK_EN BIT(0)
  497. #define ECAP_CLK_STOP_REQ BIT(1)
  498. struct pwmss_ecap_regs {
  499. unsigned int tsctr;
  500. unsigned int ctrphs;
  501. unsigned int cap1;
  502. unsigned int cap2;
  503. unsigned int cap3;
  504. unsigned int cap4;
  505. unsigned int resv1[4];
  506. unsigned short ecctl1;
  507. unsigned short ecctl2;
  508. };
  509. /* Capture Control register 2 */
  510. #define ECTRL2_SYNCOSEL_MASK (0x03 << 6)
  511. #define ECTRL2_MDSL_ECAP BIT(9)
  512. #define ECTRL2_CTRSTP_FREERUN BIT(4)
  513. #define ECTRL2_PLSL_LOW BIT(10)
  514. #define ECTRL2_SYNC_EN BIT(5)
  515. #endif /* __ASSEMBLY__ */
  516. #endif /* __KERNEL_STRICT_NAMES */
  517. #endif /* _AM33XX_CPU_H */