slcr.c 2.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108
  1. /*
  2. * Copyright (c) 2013 Xilinx Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <malloc.h>
  9. #include <asm/arch/hardware.h>
  10. #define SLCR_LOCK_MAGIC 0x767B
  11. #define SLCR_UNLOCK_MAGIC 0xDF0D
  12. #define SLCR_IDCODE_MASK 0x1F000
  13. #define SLCR_IDCODE_SHIFT 12
  14. static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
  15. void zynq_slcr_lock(void)
  16. {
  17. if (!slcr_lock)
  18. writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
  19. }
  20. void zynq_slcr_unlock(void)
  21. {
  22. if (slcr_lock)
  23. writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
  24. }
  25. /* Reset the entire system */
  26. void zynq_slcr_cpu_reset(void)
  27. {
  28. /*
  29. * Unlock the SLCR then reset the system.
  30. * Note that this seems to require raw i/o
  31. * functions or there's a lockup?
  32. */
  33. zynq_slcr_unlock();
  34. /*
  35. * Clear 0x0F000000 bits of reboot status register to workaround
  36. * the FSBL not loading the bitstream after soft-reboot
  37. * This is a temporary solution until we know more.
  38. */
  39. clrbits_le32(&slcr_base->reboot_status, 0xF000000);
  40. writel(1, &slcr_base->pss_rst_ctrl);
  41. }
  42. /* Setup clk for network */
  43. void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
  44. {
  45. zynq_slcr_unlock();
  46. if (gem_id > 1) {
  47. printf("Non existing GEM id %d\n", gem_id);
  48. goto out;
  49. }
  50. if (gem_id) {
  51. /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
  52. writel(clk, &slcr_base->gem1_clk_ctrl);
  53. /* Configure GEM_RCLK_CTRL */
  54. writel(rclk, &slcr_base->gem1_rclk_ctrl);
  55. } else {
  56. /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
  57. writel(clk, &slcr_base->gem0_clk_ctrl);
  58. /* Configure GEM_RCLK_CTRL */
  59. writel(rclk, &slcr_base->gem0_rclk_ctrl);
  60. }
  61. udelay(100000);
  62. out:
  63. zynq_slcr_lock();
  64. }
  65. void zynq_slcr_devcfg_disable(void)
  66. {
  67. zynq_slcr_unlock();
  68. /* Disable AXI interface */
  69. writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
  70. /* Set Level Shifters DT618760 */
  71. writel(0xA, &slcr_base->lvl_shftr_en);
  72. zynq_slcr_lock();
  73. }
  74. void zynq_slcr_devcfg_enable(void)
  75. {
  76. zynq_slcr_unlock();
  77. /* Set Level Shifters DT618760 */
  78. writel(0xF, &slcr_base->lvl_shftr_en);
  79. /* Disable AXI interface */
  80. writel(0x0, &slcr_base->fpga_rst_ctrl);
  81. zynq_slcr_lock();
  82. }
  83. u32 zynq_slcr_get_idcode(void)
  84. {
  85. return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
  86. SLCR_IDCODE_SHIFT;
  87. }