ddrc.c 1.4 KB

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  1. /*
  2. * Copyright (C) 2012 - 2013 Michal Simek <monstr@monstr.eu>
  3. * Copyright (C) 2012 - 2013 Xilinx, Inc. All rights reserved.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/sys_proto.h>
  10. #include <asm/arch/hardware.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. /* Control regsiter bitfield definitions */
  13. #define ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK 0xC
  14. #define ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT 2
  15. #define ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT 1
  16. /* ECC scrub regsiter definitions */
  17. #define ZYNQ_DDRC_ECC_SCRUBREG_ECC_MODE_MASK 0x7
  18. #define ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED 0x4
  19. void zynq_ddrc_init(void)
  20. {
  21. u32 width, ecctype;
  22. width = readl(&ddrc_base->ddrc_ctrl);
  23. width = (width & ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK) >>
  24. ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT;
  25. ecctype = (readl(&ddrc_base->ecc_scrub) &
  26. ZYNQ_DDRC_ECC_SCRUBREG_ECC_MODE_MASK);
  27. /* ECC is enabled when memory is in 16bit mode and it is enabled */
  28. if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) &&
  29. (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)) {
  30. puts("Memory: ECC enabled\n");
  31. /*
  32. * Clear the first 1MB because it is not initialized from
  33. * first stage bootloader. To get ECC to work all memory has
  34. * been initialized by writing any value.
  35. */
  36. memset(0, 0, 1 * 1024 * 1024);
  37. } else {
  38. puts("Memory: ECC disabled\n");
  39. }
  40. if (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)
  41. gd->ram_size /= 2;
  42. }