sdram_elpida.c 8.1 KB

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  1. /*
  2. * Timing and Organization details of the Elpida parts used in OMAP4
  3. * SDPs and Panda
  4. *
  5. * (C) Copyright 2010
  6. * Texas Instruments, <www.ti.com>
  7. *
  8. * Aneesh V <aneesh@ti.com>
  9. *
  10. * SPDX-License-Identifier: GPL-2.0+
  11. */
  12. #include <asm/emif.h>
  13. #include <asm/arch/sys_proto.h>
  14. /*
  15. * This file provides details of the LPDDR2 SDRAM parts used on OMAP4430
  16. * SDP and Panda. Since the parts used and geometry are identical for
  17. * SDP and Panda for a given OMAP4 revision, this information is kept
  18. * here instead of being in board directory. However the key functions
  19. * exported are weakly linked so that they can be over-ridden in the board
  20. * directory if there is a OMAP4 board in the future that uses a different
  21. * memory device or geometry.
  22. *
  23. * For any new board with different memory devices over-ride one or more
  24. * of the following functions as per the CONFIG flags you intend to enable:
  25. * - emif_get_reg_dump()
  26. * - emif_get_dmm_regs()
  27. * - emif_get_device_details()
  28. * - emif_get_device_timings()
  29. */
  30. #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  31. static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
  32. .sdram_config_init = 0x80000eb9,
  33. .sdram_config = 0x80001ab9,
  34. .ref_ctrl = 0x0000030c,
  35. .sdram_tim1 = 0x08648311,
  36. .sdram_tim2 = 0x101b06ca,
  37. .sdram_tim3 = 0x0048a19f,
  38. .read_idle_ctrl = 0x000501ff,
  39. .zq_config = 0x500b3214,
  40. .temp_alert_config = 0xd8016893,
  41. .emif_ddr_phy_ctlr_1_init = 0x049ffff5,
  42. .emif_ddr_phy_ctlr_1 = 0x049ff808
  43. };
  44. static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
  45. .sdram_config_init = 0x80000eb1,
  46. .sdram_config = 0x80001ab1,
  47. .ref_ctrl = 0x000005cd,
  48. .sdram_tim1 = 0x10cb0622,
  49. .sdram_tim2 = 0x20350d52,
  50. .sdram_tim3 = 0x00b1431f,
  51. .read_idle_ctrl = 0x000501ff,
  52. .zq_config = 0x500b3214,
  53. .temp_alert_config = 0x58016893,
  54. .emif_ddr_phy_ctlr_1_init = 0x049ffff5,
  55. .emif_ddr_phy_ctlr_1 = 0x049ff418
  56. };
  57. const struct emif_regs emif_regs_elpida_400_mhz_1cs = {
  58. .sdram_config_init = 0x80800eb2,
  59. .sdram_config = 0x80801ab2,
  60. .ref_ctrl = 0x00000618,
  61. .sdram_tim1 = 0x10eb0662,
  62. .sdram_tim2 = 0x20370dd2,
  63. .sdram_tim3 = 0x00b1c33f,
  64. .read_idle_ctrl = 0x000501ff,
  65. .zq_config = 0x500b3215,
  66. .temp_alert_config = 0x58016893,
  67. .emif_ddr_phy_ctlr_1_init = 0x049ffff5,
  68. .emif_ddr_phy_ctlr_1 = 0x049ff418
  69. };
  70. const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
  71. .sdram_config_init = 0x80000eb9,
  72. .sdram_config = 0x80001ab9,
  73. .ref_ctrl = 0x00000618,
  74. .sdram_tim1 = 0x10eb0662,
  75. .sdram_tim2 = 0x20370dd2,
  76. .sdram_tim3 = 0x00b1c33f,
  77. .read_idle_ctrl = 0x000501ff,
  78. .zq_config = 0xd00b3214,
  79. .temp_alert_config = 0xd8016893,
  80. .emif_ddr_phy_ctlr_1_init = 0x049ffff5,
  81. .emif_ddr_phy_ctlr_1 = 0x049ff418
  82. };
  83. const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
  84. .dmm_lisa_map_0 = 0xFF020100,
  85. .dmm_lisa_map_1 = 0,
  86. .dmm_lisa_map_2 = 0,
  87. .dmm_lisa_map_3 = 0x80540300,
  88. .is_ma_present = 0x0
  89. };
  90. const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
  91. .dmm_lisa_map_0 = 0xFF020100,
  92. .dmm_lisa_map_1 = 0,
  93. .dmm_lisa_map_2 = 0,
  94. .dmm_lisa_map_3 = 0x80640300,
  95. .is_ma_present = 0x0
  96. };
  97. const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = {
  98. .dmm_lisa_map_0 = 0xFF020100,
  99. .dmm_lisa_map_1 = 0,
  100. .dmm_lisa_map_2 = 0,
  101. .dmm_lisa_map_3 = 0x80640300,
  102. .is_ma_present = 0x1
  103. };
  104. static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
  105. {
  106. u32 omap4_rev = omap_revision();
  107. /* Same devices and geometry on both EMIFs */
  108. if (omap4_rev == OMAP4430_ES1_0)
  109. *regs = &emif_regs_elpida_380_mhz_1cs;
  110. else if (omap4_rev == OMAP4430_ES2_0)
  111. *regs = &emif_regs_elpida_200_mhz_2cs;
  112. else if (omap4_rev < OMAP4470_ES1_0)
  113. *regs = &emif_regs_elpida_400_mhz_2cs;
  114. else
  115. *regs = &emif_regs_elpida_400_mhz_1cs;
  116. }
  117. void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
  118. __attribute__((weak, alias("emif_get_reg_dump_sdp")));
  119. static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
  120. **dmm_lisa_regs)
  121. {
  122. u32 omap_rev = omap_revision();
  123. if (omap_rev == OMAP4430_ES1_0)
  124. *dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
  125. else if (omap_rev < OMAP4460_ES1_0)
  126. *dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
  127. else
  128. *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
  129. }
  130. void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  131. __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
  132. #else
  133. static const struct lpddr2_device_details elpida_2G_S4_details = {
  134. .type = LPDDR2_TYPE_S4,
  135. .density = LPDDR2_DENSITY_2Gb,
  136. .io_width = LPDDR2_IO_WIDTH_32,
  137. .manufacturer = LPDDR2_MANUFACTURER_ELPIDA
  138. };
  139. static const struct lpddr2_device_details elpida_4G_S4_details = {
  140. .type = LPDDR2_TYPE_S4,
  141. .density = LPDDR2_DENSITY_4Gb,
  142. .io_width = LPDDR2_IO_WIDTH_32,
  143. .manufacturer = LPDDR2_MANUFACTURER_ELPIDA
  144. };
  145. struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
  146. struct lpddr2_device_details *lpddr2_dev_details)
  147. {
  148. u32 omap_rev = omap_revision();
  149. /* EMIF1 & EMIF2 have identical configuration */
  150. if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
  151. && (cs == CS1)) {
  152. /* Nothing connected on CS1 for 4430/4470 ES1.0 */
  153. return NULL;
  154. } else if (omap_rev < OMAP4470_ES1_0) {
  155. /* In all other 4430/4460 cases Elpida 2G device */
  156. *lpddr2_dev_details = elpida_2G_S4_details;
  157. } else {
  158. /* 4470: 4G device */
  159. *lpddr2_dev_details = elpida_4G_S4_details;
  160. }
  161. return lpddr2_dev_details;
  162. }
  163. struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
  164. struct lpddr2_device_details *lpddr2_dev_details)
  165. __attribute__((weak, alias("emif_get_device_details_sdp")));
  166. #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
  167. #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
  168. static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
  169. .max_freq = 400000000,
  170. .RL = 6,
  171. .tRPab = 21,
  172. .tRCD = 18,
  173. .tWR = 15,
  174. .tRASmin = 42,
  175. .tRRD = 10,
  176. .tWTRx2 = 15,
  177. .tXSR = 140,
  178. .tXPx2 = 15,
  179. .tRFCab = 130,
  180. .tRTPx2 = 15,
  181. .tCKE = 3,
  182. .tCKESR = 15,
  183. .tZQCS = 90,
  184. .tZQCL = 360,
  185. .tZQINIT = 1000,
  186. .tDQSCKMAXx2 = 11,
  187. .tRASmax = 70,
  188. .tFAW = 50
  189. };
  190. static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
  191. .max_freq = 333000000,
  192. .RL = 5,
  193. .tRPab = 21,
  194. .tRCD = 18,
  195. .tWR = 15,
  196. .tRASmin = 42,
  197. .tRRD = 10,
  198. .tWTRx2 = 15,
  199. .tXSR = 140,
  200. .tXPx2 = 15,
  201. .tRFCab = 130,
  202. .tRTPx2 = 15,
  203. .tCKE = 3,
  204. .tCKESR = 15,
  205. .tZQCS = 90,
  206. .tZQCL = 360,
  207. .tZQINIT = 1000,
  208. .tDQSCKMAXx2 = 11,
  209. .tRASmax = 70,
  210. .tFAW = 50
  211. };
  212. static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
  213. .max_freq = 200000000,
  214. .RL = 3,
  215. .tRPab = 21,
  216. .tRCD = 18,
  217. .tWR = 15,
  218. .tRASmin = 42,
  219. .tRRD = 10,
  220. .tWTRx2 = 20,
  221. .tXSR = 140,
  222. .tXPx2 = 15,
  223. .tRFCab = 130,
  224. .tRTPx2 = 15,
  225. .tCKE = 3,
  226. .tCKESR = 15,
  227. .tZQCS = 90,
  228. .tZQCL = 360,
  229. .tZQINIT = 1000,
  230. .tDQSCKMAXx2 = 11,
  231. .tRASmax = 70,
  232. .tFAW = 50
  233. };
  234. static const struct lpddr2_min_tck min_tck_elpida = {
  235. .tRL = 3,
  236. .tRP_AB = 3,
  237. .tRCD = 3,
  238. .tWR = 3,
  239. .tRAS_MIN = 3,
  240. .tRRD = 2,
  241. .tWTR = 2,
  242. .tXP = 2,
  243. .tRTP = 2,
  244. .tCKE = 3,
  245. .tCKESR = 3,
  246. .tFAW = 8
  247. };
  248. static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
  249. &timings_elpida_200_mhz,
  250. &timings_elpida_333_mhz,
  251. &timings_elpida_400_mhz
  252. };
  253. static const struct lpddr2_device_timings elpida_2G_S4_timings = {
  254. .ac_timings = elpida_ac_timings,
  255. .min_tck = &min_tck_elpida,
  256. };
  257. void emif_get_device_timings_sdp(u32 emif_nr,
  258. const struct lpddr2_device_timings **cs0_device_timings,
  259. const struct lpddr2_device_timings **cs1_device_timings)
  260. {
  261. u32 omap_rev = omap_revision();
  262. /* Identical devices on EMIF1 & EMIF2 */
  263. *cs0_device_timings = &elpida_2G_S4_timings;
  264. if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
  265. *cs1_device_timings = NULL;
  266. else
  267. *cs1_device_timings = &elpida_2G_S4_timings;
  268. }
  269. void emif_get_device_timings(u32 emif_nr,
  270. const struct lpddr2_device_timings **cs0_device_timings,
  271. const struct lpddr2_device_timings **cs1_device_timings)
  272. __attribute__((weak, alias("emif_get_device_timings_sdp")));
  273. #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
  274. const struct lpddr2_mr_regs mr_regs = {
  275. .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3,
  276. .mr2 = 0x4,
  277. .mr3 = -1,
  278. .mr10 = MR10_ZQ_ZQINIT,
  279. .mr16 = MR16_REF_FULL_ARRAY
  280. };
  281. void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
  282. {
  283. *regs = &mr_regs;
  284. }