hw_data.c 16 KB

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  1. /*
  2. *
  3. * HW data initialization for OMAP4
  4. *
  5. * (C) Copyright 2013
  6. * Texas Instruments, <www.ti.com>
  7. *
  8. * Sricharan R <r.sricharan@ti.com>
  9. *
  10. * SPDX-License-Identifier: GPL-2.0+
  11. */
  12. #include <common.h>
  13. #include <asm/arch/omap.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/omap_common.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/omap_gpio.h>
  18. #include <asm/io.h>
  19. struct prcm_regs const **prcm =
  20. (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
  21. struct dplls const **dplls_data =
  22. (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
  23. struct vcores_data const **omap_vcores =
  24. (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
  25. struct omap_sys_ctrl_regs const **ctrl =
  26. (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
  27. /*
  28. * The M & N values in the following tables are created using the
  29. * following tool:
  30. * tools/omap/clocks_get_m_n.c
  31. * Please use this tool for creating the table for any new frequency.
  32. */
  33. /*
  34. * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
  35. * OMAP4460 OPP_NOM frequency
  36. */
  37. static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
  38. {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  39. {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  40. {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  41. {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  42. {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  43. {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  44. {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  45. };
  46. /*
  47. * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
  48. * OMAP4430 OPP_TURBO frequency
  49. * OMAP4470 OPP_NOM frequency
  50. */
  51. static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
  52. {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  53. {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  54. {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  55. {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  56. {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  57. {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  58. {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  59. };
  60. /*
  61. * dpll locked at 1200 MHz - MPU clk at 600 MHz
  62. * OMAP4430 OPP_NOM frequency
  63. */
  64. static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
  65. {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  66. {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  67. {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  68. {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  69. {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  70. {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  71. {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  72. };
  73. /* OMAP4460 OPP_NOM frequency */
  74. /* OMAP4470 OPP_NOM (Low Power) frequency */
  75. static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
  76. {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
  77. {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
  78. {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
  79. {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
  80. {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
  81. {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
  82. {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
  83. };
  84. /* OMAP4430 ES1 OPP_NOM frequency */
  85. static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
  86. {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
  87. {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
  88. {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
  89. {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
  90. {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
  91. {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
  92. {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
  93. };
  94. /* OMAP4430 ES2.X OPP_NOM frequency */
  95. static const struct dpll_params
  96. core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
  97. {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
  98. {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
  99. {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
  100. {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
  101. {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
  102. {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
  103. {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
  104. };
  105. static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
  106. {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */
  107. {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */
  108. {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */
  109. {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */
  110. {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */
  111. {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */
  112. {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */
  113. };
  114. static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
  115. {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  116. {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  117. {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  118. {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  119. {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  120. {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  121. {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  122. };
  123. /* ABE M & N values with sys_clk as source */
  124. static const struct dpll_params
  125. abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
  126. {49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  127. {68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  128. {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  129. {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  130. {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  131. {29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  132. {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  133. };
  134. /* ABE M & N values with 32K clock as source */
  135. static const struct dpll_params abe_dpll_params_32k_196608khz = {
  136. 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
  137. };
  138. static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
  139. {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  140. {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  141. {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  142. {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  143. {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  144. {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  145. {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  146. };
  147. struct dplls omap4430_dplls_es1 = {
  148. .mpu = mpu_dpll_params_1200mhz,
  149. .core = core_dpll_params_es1_1524mhz,
  150. .per = per_dpll_params_1536mhz,
  151. .iva = iva_dpll_params_1862mhz,
  152. #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
  153. .abe = abe_dpll_params_sysclk_196608khz,
  154. #else
  155. .abe = &abe_dpll_params_32k_196608khz,
  156. #endif
  157. .usb = usb_dpll_params_1920mhz,
  158. .ddr = NULL
  159. };
  160. struct dplls omap4430_dplls = {
  161. .mpu = mpu_dpll_params_1200mhz,
  162. .core = core_dpll_params_1600mhz,
  163. .per = per_dpll_params_1536mhz,
  164. .iva = iva_dpll_params_1862mhz,
  165. #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
  166. .abe = abe_dpll_params_sysclk_196608khz,
  167. #else
  168. .abe = &abe_dpll_params_32k_196608khz,
  169. #endif
  170. .usb = usb_dpll_params_1920mhz,
  171. .ddr = NULL
  172. };
  173. struct dplls omap4460_dplls = {
  174. .mpu = mpu_dpll_params_1400mhz,
  175. .core = core_dpll_params_1600mhz,
  176. .per = per_dpll_params_1536mhz,
  177. .iva = iva_dpll_params_1862mhz,
  178. #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
  179. .abe = abe_dpll_params_sysclk_196608khz,
  180. #else
  181. .abe = &abe_dpll_params_32k_196608khz,
  182. #endif
  183. .usb = usb_dpll_params_1920mhz,
  184. .ddr = NULL
  185. };
  186. struct dplls omap4470_dplls = {
  187. .mpu = mpu_dpll_params_1600mhz,
  188. .core = core_dpll_params_1600mhz,
  189. .per = per_dpll_params_1536mhz,
  190. .iva = iva_dpll_params_1862mhz,
  191. #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
  192. .abe = abe_dpll_params_sysclk_196608khz,
  193. #else
  194. .abe = &abe_dpll_params_32k_196608khz,
  195. #endif
  196. .usb = usb_dpll_params_1920mhz,
  197. .ddr = NULL
  198. };
  199. struct pmic_data twl6030_4430es1 = {
  200. .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
  201. .step = 12660, /* 12.66 mV represented in uV */
  202. /* The code starts at 1 not 0 */
  203. .start_code = 1,
  204. .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
  205. .pmic_bus_init = sri2c_init,
  206. .pmic_write = omap_vc_bypass_send_value,
  207. };
  208. /* twl6030 struct is used for TWL6030 and TWL6032 PMIC */
  209. struct pmic_data twl6030 = {
  210. .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
  211. .step = 12660, /* 12.66 mV represented in uV */
  212. /* The code starts at 1 not 0 */
  213. .start_code = 1,
  214. .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
  215. .pmic_bus_init = sri2c_init,
  216. .pmic_write = omap_vc_bypass_send_value,
  217. };
  218. struct pmic_data tps62361 = {
  219. .base_offset = TPS62361_BASE_VOLT_MV,
  220. .step = 10000, /* 10 mV represented in uV */
  221. .start_code = 0,
  222. .gpio = TPS62361_VSEL0_GPIO,
  223. .gpio_en = 1,
  224. .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
  225. .pmic_bus_init = sri2c_init,
  226. .pmic_write = omap_vc_bypass_send_value,
  227. };
  228. struct vcores_data omap4430_volts_es1 = {
  229. .mpu.value = 1325,
  230. .mpu.addr = SMPS_REG_ADDR_VCORE1,
  231. .mpu.pmic = &twl6030_4430es1,
  232. .core.value = 1200,
  233. .core.addr = SMPS_REG_ADDR_VCORE3,
  234. .core.pmic = &twl6030_4430es1,
  235. .mm.value = 1200,
  236. .mm.addr = SMPS_REG_ADDR_VCORE2,
  237. .mm.pmic = &twl6030_4430es1,
  238. };
  239. struct vcores_data omap4430_volts = {
  240. .mpu.value = 1325,
  241. .mpu.addr = SMPS_REG_ADDR_VCORE1,
  242. .mpu.pmic = &twl6030,
  243. .core.value = 1200,
  244. .core.addr = SMPS_REG_ADDR_VCORE3,
  245. .core.pmic = &twl6030,
  246. .mm.value = 1200,
  247. .mm.addr = SMPS_REG_ADDR_VCORE2,
  248. .mm.pmic = &twl6030,
  249. };
  250. struct vcores_data omap4460_volts = {
  251. .mpu.value = 1203,
  252. .mpu.addr = TPS62361_REG_ADDR_SET1,
  253. .mpu.pmic = &tps62361,
  254. .core.value = 1200,
  255. .core.addr = SMPS_REG_ADDR_VCORE1,
  256. .core.pmic = &twl6030,
  257. .mm.value = 1200,
  258. .mm.addr = SMPS_REG_ADDR_VCORE2,
  259. .mm.pmic = &twl6030,
  260. };
  261. struct vcores_data omap4470_volts = {
  262. .mpu.value = 1200,
  263. .mpu.addr = SMPS_REG_ADDR_SMPS1,
  264. .mpu.pmic = &twl6030,
  265. .core.value = 1126,
  266. .core.addr = SMPS_REG_ADDR_SMPS1,
  267. .core.pmic = &twl6030,
  268. .mm.value = 1137,
  269. .mm.addr = SMPS_REG_ADDR_SMPS1,
  270. .mm.pmic = &twl6030,
  271. };
  272. /*
  273. * Enable essential clock domains, modules and
  274. * do some additional special settings needed
  275. */
  276. void enable_basic_clocks(void)
  277. {
  278. u32 const clk_domains_essential[] = {
  279. (*prcm)->cm_l4per_clkstctrl,
  280. (*prcm)->cm_l3init_clkstctrl,
  281. (*prcm)->cm_memif_clkstctrl,
  282. (*prcm)->cm_l4cfg_clkstctrl,
  283. 0
  284. };
  285. u32 const clk_modules_hw_auto_essential[] = {
  286. (*prcm)->cm_l3_gpmc_clkctrl,
  287. (*prcm)->cm_memif_emif_1_clkctrl,
  288. (*prcm)->cm_memif_emif_2_clkctrl,
  289. (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
  290. (*prcm)->cm_wkup_gpio1_clkctrl,
  291. (*prcm)->cm_l4per_gpio2_clkctrl,
  292. (*prcm)->cm_l4per_gpio3_clkctrl,
  293. (*prcm)->cm_l4per_gpio4_clkctrl,
  294. (*prcm)->cm_l4per_gpio5_clkctrl,
  295. (*prcm)->cm_l4per_gpio6_clkctrl,
  296. 0
  297. };
  298. u32 const clk_modules_explicit_en_essential[] = {
  299. (*prcm)->cm_wkup_gptimer1_clkctrl,
  300. (*prcm)->cm_l3init_hsmmc1_clkctrl,
  301. (*prcm)->cm_l3init_hsmmc2_clkctrl,
  302. (*prcm)->cm_l4per_gptimer2_clkctrl,
  303. (*prcm)->cm_wkup_wdtimer2_clkctrl,
  304. (*prcm)->cm_l4per_uart3_clkctrl,
  305. 0
  306. };
  307. /* Enable optional additional functional clock for GPIO4 */
  308. setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
  309. GPIO4_CLKCTRL_OPTFCLKEN_MASK);
  310. /* Enable 96 MHz clock for MMC1 & MMC2 */
  311. setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
  312. HSMMC_CLKCTRL_CLKSEL_MASK);
  313. setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
  314. HSMMC_CLKCTRL_CLKSEL_MASK);
  315. /* Select 32KHz clock as the source of GPTIMER1 */
  316. setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
  317. GPTIMER1_CLKCTRL_CLKSEL_MASK);
  318. /* Enable optional 48M functional clock for USB PHY */
  319. setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
  320. USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
  321. do_enable_clocks(clk_domains_essential,
  322. clk_modules_hw_auto_essential,
  323. clk_modules_explicit_en_essential,
  324. 1);
  325. }
  326. void enable_basic_uboot_clocks(void)
  327. {
  328. u32 const clk_domains_essential[] = {
  329. 0
  330. };
  331. u32 const clk_modules_hw_auto_essential[] = {
  332. (*prcm)->cm_l3init_hsusbotg_clkctrl,
  333. (*prcm)->cm_l3init_usbphy_clkctrl,
  334. (*prcm)->cm_l3init_usbphy_clkctrl,
  335. (*prcm)->cm_clksel_usb_60mhz,
  336. (*prcm)->cm_l3init_hsusbtll_clkctrl,
  337. 0
  338. };
  339. u32 const clk_modules_explicit_en_essential[] = {
  340. (*prcm)->cm_l4per_mcspi1_clkctrl,
  341. (*prcm)->cm_l4per_i2c1_clkctrl,
  342. (*prcm)->cm_l4per_i2c2_clkctrl,
  343. (*prcm)->cm_l4per_i2c3_clkctrl,
  344. (*prcm)->cm_l4per_i2c4_clkctrl,
  345. (*prcm)->cm_l3init_hsusbhost_clkctrl,
  346. 0
  347. };
  348. do_enable_clocks(clk_domains_essential,
  349. clk_modules_hw_auto_essential,
  350. clk_modules_explicit_en_essential,
  351. 1);
  352. }
  353. /*
  354. * Enable non-essential clock domains, modules and
  355. * do some additional special settings needed
  356. */
  357. void enable_non_essential_clocks(void)
  358. {
  359. u32 const clk_domains_non_essential[] = {
  360. (*prcm)->cm_mpu_m3_clkstctrl,
  361. (*prcm)->cm_ivahd_clkstctrl,
  362. (*prcm)->cm_dsp_clkstctrl,
  363. (*prcm)->cm_dss_clkstctrl,
  364. (*prcm)->cm_sgx_clkstctrl,
  365. (*prcm)->cm1_abe_clkstctrl,
  366. (*prcm)->cm_c2c_clkstctrl,
  367. (*prcm)->cm_cam_clkstctrl,
  368. (*prcm)->cm_dss_clkstctrl,
  369. (*prcm)->cm_sdma_clkstctrl,
  370. 0
  371. };
  372. u32 const clk_modules_hw_auto_non_essential[] = {
  373. (*prcm)->cm_l3instr_l3_3_clkctrl,
  374. (*prcm)->cm_l3instr_l3_instr_clkctrl,
  375. (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
  376. (*prcm)->cm_l3init_hsi_clkctrl,
  377. 0
  378. };
  379. u32 const clk_modules_explicit_en_non_essential[] = {
  380. (*prcm)->cm1_abe_aess_clkctrl,
  381. (*prcm)->cm1_abe_pdm_clkctrl,
  382. (*prcm)->cm1_abe_dmic_clkctrl,
  383. (*prcm)->cm1_abe_mcasp_clkctrl,
  384. (*prcm)->cm1_abe_mcbsp1_clkctrl,
  385. (*prcm)->cm1_abe_mcbsp2_clkctrl,
  386. (*prcm)->cm1_abe_mcbsp3_clkctrl,
  387. (*prcm)->cm1_abe_slimbus_clkctrl,
  388. (*prcm)->cm1_abe_timer5_clkctrl,
  389. (*prcm)->cm1_abe_timer6_clkctrl,
  390. (*prcm)->cm1_abe_timer7_clkctrl,
  391. (*prcm)->cm1_abe_timer8_clkctrl,
  392. (*prcm)->cm1_abe_wdt3_clkctrl,
  393. (*prcm)->cm_l4per_gptimer9_clkctrl,
  394. (*prcm)->cm_l4per_gptimer10_clkctrl,
  395. (*prcm)->cm_l4per_gptimer11_clkctrl,
  396. (*prcm)->cm_l4per_gptimer3_clkctrl,
  397. (*prcm)->cm_l4per_gptimer4_clkctrl,
  398. (*prcm)->cm_l4per_hdq1w_clkctrl,
  399. (*prcm)->cm_l4per_mcbsp4_clkctrl,
  400. (*prcm)->cm_l4per_mcspi2_clkctrl,
  401. (*prcm)->cm_l4per_mcspi3_clkctrl,
  402. (*prcm)->cm_l4per_mcspi4_clkctrl,
  403. (*prcm)->cm_l4per_mmcsd3_clkctrl,
  404. (*prcm)->cm_l4per_mmcsd4_clkctrl,
  405. (*prcm)->cm_l4per_mmcsd5_clkctrl,
  406. (*prcm)->cm_l4per_uart1_clkctrl,
  407. (*prcm)->cm_l4per_uart2_clkctrl,
  408. (*prcm)->cm_l4per_uart4_clkctrl,
  409. (*prcm)->cm_wkup_keyboard_clkctrl,
  410. (*prcm)->cm_wkup_wdtimer2_clkctrl,
  411. (*prcm)->cm_cam_iss_clkctrl,
  412. (*prcm)->cm_cam_fdif_clkctrl,
  413. (*prcm)->cm_dss_dss_clkctrl,
  414. (*prcm)->cm_sgx_sgx_clkctrl,
  415. 0
  416. };
  417. /* Enable optional functional clock for ISS */
  418. setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
  419. /* Enable all optional functional clocks of DSS */
  420. setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
  421. do_enable_clocks(clk_domains_non_essential,
  422. clk_modules_hw_auto_non_essential,
  423. clk_modules_explicit_en_non_essential,
  424. 0);
  425. /* Put camera module in no sleep mode */
  426. clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
  427. MODULE_CLKCTRL_MODULEMODE_MASK,
  428. CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
  429. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  430. }
  431. void hw_data_init(void)
  432. {
  433. u32 omap_rev = omap_revision();
  434. (*prcm) = &omap4_prcm;
  435. switch (omap_rev) {
  436. case OMAP4430_ES1_0:
  437. *dplls_data = &omap4430_dplls_es1;
  438. *omap_vcores = &omap4430_volts_es1;
  439. break;
  440. case OMAP4430_ES2_0:
  441. case OMAP4430_ES2_1:
  442. case OMAP4430_ES2_2:
  443. case OMAP4430_ES2_3:
  444. *dplls_data = &omap4430_dplls;
  445. *omap_vcores = &omap4430_volts;
  446. break;
  447. case OMAP4460_ES1_0:
  448. case OMAP4460_ES1_1:
  449. *dplls_data = &omap4460_dplls;
  450. *omap_vcores = &omap4460_volts;
  451. break;
  452. case OMAP4470_ES1_0:
  453. *dplls_data = &omap4470_dplls;
  454. *omap_vcores = &omap4470_volts;
  455. break;
  456. default:
  457. printf("\n INVALID OMAP REVISION ");
  458. }
  459. *ctrl = &omap4_ctrl;
  460. }