lowlevel_init.S 13 KB

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  1. /*
  2. * Board specific setup info
  3. *
  4. * (C) Copyright 2008
  5. * Texas Instruments, <www.ti.com>
  6. *
  7. * Initial Code by:
  8. * Richard Woodruff <r-woodruff2@ti.com>
  9. * Syed Mohammed Khasim <khasim@ti.com>
  10. *
  11. * SPDX-License-Identifier: GPL-2.0+
  12. */
  13. #include <config.h>
  14. #include <version.h>
  15. #include <asm/arch/mem.h>
  16. #include <asm/arch/clocks_omap3.h>
  17. #include <linux/linkage.h>
  18. _TEXT_BASE:
  19. .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
  20. #ifdef CONFIG_SPL_BUILD
  21. ENTRY(save_boot_params)
  22. ldr r4, =omap3_boot_device
  23. ldr r5, [r0, #0x4]
  24. and r5, r5, #0xff
  25. str r5, [r4]
  26. bx lr
  27. ENDPROC(save_boot_params)
  28. #endif
  29. ENTRY(omap3_gp_romcode_call)
  30. PUSH {r4-r12, lr} @ Save all registers from ROM code!
  31. MOV r12, r0 @ Copy the Service ID in R12
  32. MOV r0, r1 @ Copy parameter to R0
  33. mcr p15, 0, r0, c7, c10, 4 @ DSB
  34. mcr p15, 0, r0, c7, c10, 5 @ DMB
  35. .word 0xe1600070 @ SMC #0 to enter monitor - hand assembled
  36. @ because we use -march=armv5
  37. POP {r4-r12, pc}
  38. ENDPROC(omap3_gp_romcode_call)
  39. /*
  40. * Funtion for making PPA HAL API calls in secure devices
  41. * Input:
  42. * R0 - Service ID
  43. * R1 - paramer list
  44. */
  45. ENTRY(do_omap3_emu_romcode_call)
  46. PUSH {r4-r12, lr} @ Save all registers from ROM code!
  47. MOV r12, r0 @ Copy the Secure Service ID in R12
  48. MOV r3, r1 @ Copy the pointer to va_list in R3
  49. MOV r1, #0 @ Process ID - 0
  50. MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer
  51. @ to va_list in R3
  52. MOV r6, #0xFF @ Indicate new Task call
  53. mcr p15, 0, r0, c7, c10, 4 @ DSB
  54. mcr p15, 0, r0, c7, c10, 5 @ DMB
  55. .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled
  56. @ because we use -march=armv5
  57. POP {r4-r12, pc}
  58. ENDPROC(do_omap3_emu_romcode_call)
  59. #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
  60. /**************************************************************************
  61. * cpy_clk_code: relocates clock code into SRAM where its safer to execute
  62. * R1 = SRAM destination address.
  63. *************************************************************************/
  64. ENTRY(cpy_clk_code)
  65. /* Copy DPLL code into SRAM */
  66. adr r0, go_to_speed /* copy from start of go_to_speed... */
  67. adr r2, lowlevel_init /* ... up to start of low_level_init */
  68. next2:
  69. ldmia r0!, {r3 - r10} /* copy from source address [r0] */
  70. stmia r1!, {r3 - r10} /* copy to target address [r1] */
  71. cmp r0, r2 /* until source end address [r2] */
  72. blo next2
  73. mov pc, lr /* back to caller */
  74. ENDPROC(cpy_clk_code)
  75. /* ***************************************************************************
  76. * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
  77. * -executed from SRAM.
  78. * R0 = CM_CLKEN_PLL-bypass value
  79. * R1 = CM_CLKSEL1_PLL-m, n, and divider values
  80. * R2 = CM_CLKSEL_CORE-divider values
  81. * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
  82. *
  83. * Note: If core unlocks/relocks and SDRAM is running fast already it gets
  84. * confused. A reset of the controller gets it back. Taking away its
  85. * L3 when its not in self refresh seems bad for it. Normally, this
  86. * code runs from flash before SDR is init so that should be ok.
  87. ****************************************************************************/
  88. ENTRY(go_to_speed)
  89. stmfd sp!, {r4 - r6}
  90. /* move into fast relock bypass */
  91. ldr r4, pll_ctl_add
  92. str r0, [r4]
  93. wait1:
  94. ldr r5, [r3] /* get status */
  95. and r5, r5, #0x1 /* isolate core status */
  96. cmp r5, #0x1 /* still locked? */
  97. beq wait1 /* if lock, loop */
  98. /* set new dpll dividers _after_ in bypass */
  99. ldr r5, pll_div_add1
  100. str r1, [r5] /* set m, n, m2 */
  101. ldr r5, pll_div_add2
  102. str r2, [r5] /* set l3/l4/.. dividers*/
  103. ldr r5, pll_div_add3 /* wkup */
  104. ldr r2, pll_div_val3 /* rsm val */
  105. str r2, [r5]
  106. ldr r5, pll_div_add4 /* gfx */
  107. ldr r2, pll_div_val4
  108. str r2, [r5]
  109. ldr r5, pll_div_add5 /* emu */
  110. ldr r2, pll_div_val5
  111. str r2, [r5]
  112. /* now prepare GPMC (flash) for new dpll speed */
  113. /* flash needs to be stable when we jump back to it */
  114. ldr r5, flash_cfg3_addr
  115. ldr r2, flash_cfg3_val
  116. str r2, [r5]
  117. ldr r5, flash_cfg4_addr
  118. ldr r2, flash_cfg4_val
  119. str r2, [r5]
  120. ldr r5, flash_cfg5_addr
  121. ldr r2, flash_cfg5_val
  122. str r2, [r5]
  123. ldr r5, flash_cfg1_addr
  124. ldr r2, [r5]
  125. orr r2, r2, #0x3 /* up gpmc divider */
  126. str r2, [r5]
  127. /* lock DPLL3 and wait a bit */
  128. orr r0, r0, #0x7 /* set up for lock mode */
  129. str r0, [r4] /* lock */
  130. nop /* ARM slow at this point working at sys_clk */
  131. nop
  132. nop
  133. nop
  134. wait2:
  135. ldr r5, [r3] /* get status */
  136. and r5, r5, #0x1 /* isolate core status */
  137. cmp r5, #0x1 /* still locked? */
  138. bne wait2 /* if lock, loop */
  139. nop
  140. nop
  141. nop
  142. nop
  143. ldmfd sp!, {r4 - r6}
  144. mov pc, lr /* back to caller, locked */
  145. ENDPROC(go_to_speed)
  146. _go_to_speed: .word go_to_speed
  147. /* these constants need to be close for PIC code */
  148. /* The Nor has to be in the Flash Base CS0 for this condition to happen */
  149. flash_cfg1_addr:
  150. .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
  151. flash_cfg3_addr:
  152. .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
  153. flash_cfg3_val:
  154. .word STNOR_GPMC_CONFIG3
  155. flash_cfg4_addr:
  156. .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
  157. flash_cfg4_val:
  158. .word STNOR_GPMC_CONFIG4
  159. flash_cfg5_val:
  160. .word STNOR_GPMC_CONFIG5
  161. flash_cfg5_addr:
  162. .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
  163. pll_ctl_add:
  164. .word CM_CLKEN_PLL
  165. pll_div_add1:
  166. .word CM_CLKSEL1_PLL
  167. pll_div_add2:
  168. .word CM_CLKSEL_CORE
  169. pll_div_add3:
  170. .word CM_CLKSEL_WKUP
  171. pll_div_val3:
  172. .word (WKUP_RSM << 1)
  173. pll_div_add4:
  174. .word CM_CLKSEL_GFX
  175. pll_div_val4:
  176. .word (GFX_DIV << 0)
  177. pll_div_add5:
  178. .word CM_CLKSEL1_EMU
  179. pll_div_val5:
  180. .word CLSEL1_EMU_VAL
  181. #endif
  182. ENTRY(lowlevel_init)
  183. ldr sp, SRAM_STACK
  184. str ip, [sp] /* stash ip register */
  185. mov ip, lr /* save link reg across call */
  186. #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
  187. /*
  188. * No need to copy/exec the clock code - DPLL adjust already done
  189. * in NAND/oneNAND Boot.
  190. */
  191. ldr r1, =SRAM_CLK_CODE
  192. bl cpy_clk_code
  193. #endif /* NAND Boot */
  194. mov lr, ip /* restore link reg */
  195. ldr ip, [sp] /* restore save ip */
  196. /* tail-call s_init to setup pll, mux, memory */
  197. b s_init
  198. ENDPROC(lowlevel_init)
  199. /* the literal pools origin */
  200. .ltorg
  201. REG_CONTROL_STATUS:
  202. .word CONTROL_STATUS
  203. SRAM_STACK:
  204. .word LOW_LEVEL_SRAM_STACK
  205. /* DPLL(1-4) PARAM TABLES */
  206. /*
  207. * Each of the tables has M, N, FREQSEL, M2 values defined for nominal
  208. * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
  209. * The values are defined for all possible sysclk and for ES1 and ES2.
  210. */
  211. mpu_dpll_param:
  212. /* 12MHz */
  213. /* ES1 */
  214. .word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
  215. /* ES2 */
  216. .word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
  217. /* 3410 */
  218. .word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
  219. /* 13MHz */
  220. /* ES1 */
  221. .word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
  222. /* ES2 */
  223. .word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
  224. /* 3410 */
  225. .word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
  226. /* 19.2MHz */
  227. /* ES1 */
  228. .word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
  229. /* ES2 */
  230. .word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
  231. /* 3410 */
  232. .word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
  233. /* 26MHz */
  234. /* ES1 */
  235. .word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
  236. /* ES2 */
  237. .word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
  238. /* 3410 */
  239. .word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
  240. /* 38.4MHz */
  241. /* ES1 */
  242. .word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
  243. /* ES2 */
  244. .word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
  245. /* 3410 */
  246. .word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
  247. .globl get_mpu_dpll_param
  248. get_mpu_dpll_param:
  249. adr r0, mpu_dpll_param
  250. mov pc, lr
  251. iva_dpll_param:
  252. /* 12MHz */
  253. /* ES1 */
  254. .word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
  255. /* ES2 */
  256. .word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
  257. /* 3410 */
  258. .word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
  259. /* 13MHz */
  260. /* ES1 */
  261. .word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
  262. /* ES2 */
  263. .word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2
  264. /* 3410 */
  265. .word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
  266. /* 19.2MHz */
  267. /* ES1 */
  268. .word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
  269. /* ES2 */
  270. .word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
  271. /* 3410 */
  272. .word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
  273. /* 26MHz */
  274. /* ES1 */
  275. .word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
  276. /* ES2 */
  277. .word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
  278. /* 3410 */
  279. .word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
  280. /* 38.4MHz */
  281. /* ES1 */
  282. .word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
  283. /* ES2 */
  284. .word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
  285. /* 3410 */
  286. .word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
  287. .globl get_iva_dpll_param
  288. get_iva_dpll_param:
  289. adr r0, iva_dpll_param
  290. mov pc, lr
  291. /* Core DPLL targets for L3 at 166 & L133 */
  292. core_dpll_param:
  293. /* 12MHz */
  294. /* ES1 */
  295. .word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
  296. /* ES2 */
  297. .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
  298. /* 3410 */
  299. .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
  300. /* 13MHz */
  301. /* ES1 */
  302. .word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
  303. /* ES2 */
  304. .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
  305. /* 3410 */
  306. .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
  307. /* 19.2MHz */
  308. /* ES1 */
  309. .word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
  310. /* ES2 */
  311. .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
  312. /* 3410 */
  313. .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
  314. /* 26MHz */
  315. /* ES1 */
  316. .word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
  317. /* ES2 */
  318. .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
  319. /* 3410 */
  320. .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
  321. /* 38.4MHz */
  322. /* ES1 */
  323. .word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
  324. /* ES2 */
  325. .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
  326. /* 3410 */
  327. .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
  328. .globl get_core_dpll_param
  329. get_core_dpll_param:
  330. adr r0, core_dpll_param
  331. mov pc, lr
  332. /* PER DPLL values are same for both ES1 and ES2 */
  333. per_dpll_param:
  334. /* 12MHz */
  335. .word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
  336. /* 13MHz */
  337. .word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
  338. /* 19.2MHz */
  339. .word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
  340. /* 26MHz */
  341. .word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
  342. /* 38.4MHz */
  343. .word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
  344. .globl get_per_dpll_param
  345. get_per_dpll_param:
  346. adr r0, per_dpll_param
  347. mov pc, lr
  348. /* PER2 DPLL values */
  349. per2_dpll_param:
  350. /* 12MHz */
  351. .word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
  352. /* 13MHz */
  353. .word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
  354. /* 19.2MHz */
  355. .word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
  356. /* 26MHz */
  357. .word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
  358. /* 38.4MHz */
  359. .word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
  360. .globl get_per2_dpll_param
  361. get_per2_dpll_param:
  362. adr r0, per2_dpll_param
  363. mov pc, lr
  364. /*
  365. * Tables for 36XX/37XX devices
  366. *
  367. */
  368. mpu_36x_dpll_param:
  369. /* 12MHz */
  370. .word 50, 0, 0, 1
  371. /* 13MHz */
  372. .word 600, 12, 0, 1
  373. /* 19.2MHz */
  374. .word 125, 3, 0, 1
  375. /* 26MHz */
  376. .word 300, 12, 0, 1
  377. /* 38.4MHz */
  378. .word 125, 7, 0, 1
  379. iva_36x_dpll_param:
  380. /* 12MHz */
  381. .word 130, 2, 0, 1
  382. /* 13MHz */
  383. .word 20, 0, 0, 1
  384. /* 19.2MHz */
  385. .word 325, 11, 0, 1
  386. /* 26MHz */
  387. .word 10, 0, 0, 1
  388. /* 38.4MHz */
  389. .word 325, 23, 0, 1
  390. core_36x_dpll_param:
  391. /* 12MHz */
  392. .word 100, 2, 0, 1
  393. /* 13MHz */
  394. .word 400, 12, 0, 1
  395. /* 19.2MHz */
  396. .word 375, 17, 0, 1
  397. /* 26MHz */
  398. .word 200, 12, 0, 1
  399. /* 38.4MHz */
  400. .word 375, 35, 0, 1
  401. per_36x_dpll_param:
  402. /* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */
  403. .word 12000, 360, 4, 9, 16, 5, 4, 3, 1
  404. .word 13000, 864, 12, 9, 16, 9, 4, 3, 1
  405. .word 19200, 360, 7, 9, 16, 5, 4, 3, 1
  406. .word 26000, 432, 12, 9, 16, 9, 4, 3, 1
  407. .word 38400, 360, 15, 9, 16, 5, 4, 3, 1
  408. per2_36x_dpll_param:
  409. /* 12MHz */
  410. .word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12
  411. /* 13MHz */
  412. .word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13
  413. /* 19.2MHz */
  414. .word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2
  415. /* 26MHz */
  416. .word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26
  417. /* 38.4MHz */
  418. .word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4
  419. ENTRY(get_36x_mpu_dpll_param)
  420. adr r0, mpu_36x_dpll_param
  421. mov pc, lr
  422. ENDPROC(get_36x_mpu_dpll_param)
  423. ENTRY(get_36x_iva_dpll_param)
  424. adr r0, iva_36x_dpll_param
  425. mov pc, lr
  426. ENDPROC(get_36x_iva_dpll_param)
  427. ENTRY(get_36x_core_dpll_param)
  428. adr r0, core_36x_dpll_param
  429. mov pc, lr
  430. ENDPROC(get_36x_core_dpll_param)
  431. ENTRY(get_36x_per_dpll_param)
  432. adr r0, per_36x_dpll_param
  433. mov pc, lr
  434. ENDPROC(get_36x_per_dpll_param)
  435. ENTRY(get_36x_per2_dpll_param)
  436. adr r0, per2_36x_dpll_param
  437. mov pc, lr
  438. ENDPROC(get_36x_per2_dpll_param)