clock.c 22 KB

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  1. /*
  2. * (C) Copyright 2008
  3. * Texas Instruments, <www.ti.com>
  4. *
  5. * Author :
  6. * Manikandan Pillai <mani.pillai@ti.com>
  7. *
  8. * Derived from Beagle Board and OMAP3 SDP code by
  9. * Richard Woodruff <r-woodruff2@ti.com>
  10. * Syed Mohammed Khasim <khasim@ti.com>
  11. *
  12. * SPDX-License-Identifier: GPL-2.0+
  13. */
  14. #include <common.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/clocks_omap3.h>
  18. #include <asm/arch/mem.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <environment.h>
  21. #include <command.h>
  22. /******************************************************************************
  23. * get_sys_clk_speed() - determine reference oscillator speed
  24. * based on known 32kHz clock and gptimer.
  25. *****************************************************************************/
  26. u32 get_osc_clk_speed(void)
  27. {
  28. u32 start, cstart, cend, cdiff, cdiv, val;
  29. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  30. struct prm *prm_base = (struct prm *)PRM_BASE;
  31. struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
  32. struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
  33. val = readl(&prm_base->clksrc_ctrl);
  34. if (val & SYSCLKDIV_2)
  35. cdiv = 2;
  36. else
  37. cdiv = 1;
  38. /* enable timer2 */
  39. val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
  40. /* select sys_clk for GPT1 */
  41. writel(val, &prcm_base->clksel_wkup);
  42. /* Enable I and F Clocks for GPT1 */
  43. val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
  44. writel(val, &prcm_base->iclken_wkup);
  45. val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
  46. writel(val, &prcm_base->fclken_wkup);
  47. writel(0, &gpt1_base->tldr); /* start counting at 0 */
  48. writel(GPT_EN, &gpt1_base->tclr); /* enable clock */
  49. /* enable 32kHz source, determine sys_clk via gauging */
  50. /* start time in 20 cycles */
  51. start = 20 + readl(&s32k_base->s32k_cr);
  52. /* dead loop till start time */
  53. while (readl(&s32k_base->s32k_cr) < start);
  54. /* get start sys_clk count */
  55. cstart = readl(&gpt1_base->tcrr);
  56. /* wait for 40 cycles */
  57. while (readl(&s32k_base->s32k_cr) < (start + 20)) ;
  58. cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */
  59. cdiff = cend - cstart; /* get elapsed ticks */
  60. cdiff *= cdiv;
  61. /* based on number of ticks assign speed */
  62. if (cdiff > 19000)
  63. return S38_4M;
  64. else if (cdiff > 15200)
  65. return S26M;
  66. else if (cdiff > 13000)
  67. return S24M;
  68. else if (cdiff > 9000)
  69. return S19_2M;
  70. else if (cdiff > 7600)
  71. return S13M;
  72. else
  73. return S12M;
  74. }
  75. /******************************************************************************
  76. * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
  77. * input oscillator clock frequency.
  78. *****************************************************************************/
  79. void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
  80. {
  81. switch(osc_clk) {
  82. case S38_4M:
  83. *sys_clkin_sel = 4;
  84. break;
  85. case S26M:
  86. *sys_clkin_sel = 3;
  87. break;
  88. case S19_2M:
  89. *sys_clkin_sel = 2;
  90. break;
  91. case S13M:
  92. *sys_clkin_sel = 1;
  93. break;
  94. case S12M:
  95. default:
  96. *sys_clkin_sel = 0;
  97. }
  98. }
  99. /*
  100. * OMAP34XX/35XX specific functions
  101. */
  102. static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
  103. {
  104. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  105. dpll_param *ptr = (dpll_param *) get_core_dpll_param();
  106. void (*f_lock_pll) (u32, u32, u32, u32);
  107. int xip_safe, p0, p1, p2, p3;
  108. xip_safe = is_running_in_sram();
  109. /* Moving to the right sysclk and ES rev base */
  110. ptr = ptr + (3 * clk_index) + sil_index;
  111. if (xip_safe) {
  112. /*
  113. * CORE DPLL
  114. * sr32(CM_CLKSEL2_EMU) set override to work when asleep
  115. */
  116. sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
  117. wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
  118. LDELAY);
  119. /*
  120. * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't
  121. * work. write another value and then default value.
  122. */
  123. /* CM_CLKSEL1_EMU[DIV_DPLL3] */
  124. sr32(&prcm_base->clksel1_emu, 16, 5, (CORE_M3X2 + 1)) ;
  125. sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
  126. /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
  127. sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
  128. /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
  129. sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
  130. /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
  131. sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
  132. /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
  133. sr32(&prcm_base->clksel1_pll, 6, 1, 0);
  134. /* SSI */
  135. sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
  136. /* FSUSB */
  137. sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
  138. /* L4 */
  139. sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
  140. /* L3 */
  141. sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
  142. /* GFX */
  143. sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
  144. /* RESET MGR */
  145. sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
  146. /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
  147. sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);
  148. /* LOCK MODE */
  149. sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
  150. wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
  151. LDELAY);
  152. } else if (is_running_in_flash()) {
  153. /*
  154. * if running from flash, jump to small relocated code
  155. * area in SRAM.
  156. */
  157. f_lock_pll = (void *) (SRAM_CLK_CODE);
  158. p0 = readl(&prcm_base->clken_pll);
  159. sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
  160. /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
  161. sr32(&p0, 4, 4, ptr->fsel);
  162. p1 = readl(&prcm_base->clksel1_pll);
  163. /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
  164. sr32(&p1, 27, 5, ptr->m2);
  165. /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
  166. sr32(&p1, 16, 11, ptr->m);
  167. /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
  168. sr32(&p1, 8, 7, ptr->n);
  169. /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
  170. sr32(&p1, 6, 1, 0);
  171. p2 = readl(&prcm_base->clksel_core);
  172. /* SSI */
  173. sr32(&p2, 8, 4, CORE_SSI_DIV);
  174. /* FSUSB */
  175. sr32(&p2, 4, 2, CORE_FUSB_DIV);
  176. /* L4 */
  177. sr32(&p2, 2, 2, CORE_L4_DIV);
  178. /* L3 */
  179. sr32(&p2, 0, 2, CORE_L3_DIV);
  180. p3 = (u32)&prcm_base->idlest_ckgen;
  181. (*f_lock_pll) (p0, p1, p2, p3);
  182. }
  183. }
  184. static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
  185. {
  186. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  187. dpll_param *ptr = (dpll_param *) get_per_dpll_param();
  188. /* Moving it to the right sysclk base */
  189. ptr = ptr + clk_index;
  190. /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
  191. sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
  192. wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
  193. /*
  194. * Errata 1.50 Workaround for OMAP3 ES1.0 only
  195. * If using default divisors, write default divisor + 1
  196. * and then the actual divisor value
  197. */
  198. /* M6 */
  199. sr32(&prcm_base->clksel1_emu, 24, 5, (PER_M6X2 + 1));
  200. sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2);
  201. /* M5 */
  202. sr32(&prcm_base->clksel_cam, 0, 5, (PER_M5X2 + 1));
  203. sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2);
  204. /* M4 */
  205. sr32(&prcm_base->clksel_dss, 0, 5, (PER_M4X2 + 1));
  206. sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2);
  207. /* M3 */
  208. sr32(&prcm_base->clksel_dss, 8, 5, (PER_M3X2 + 1));
  209. sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2);
  210. /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
  211. sr32(&prcm_base->clksel3_pll, 0, 5, (ptr->m2 + 1));
  212. sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
  213. /* Workaround end */
  214. /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
  215. sr32(&prcm_base->clksel2_pll, 8, 11, ptr->m);
  216. /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
  217. sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
  218. /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
  219. sr32(&prcm_base->clken_pll, 20, 4, ptr->fsel);
  220. /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
  221. sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
  222. wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
  223. }
  224. static void dpll5_init_34xx(u32 sil_index, u32 clk_index)
  225. {
  226. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  227. dpll_param *ptr = (dpll_param *) get_per2_dpll_param();
  228. /* Moving it to the right sysclk base */
  229. ptr = ptr + clk_index;
  230. /* PER2 DPLL (DPLL5) */
  231. sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP);
  232. wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
  233. sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */
  234. sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */
  235. sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/
  236. sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel); /* FREQSEL */
  237. sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK); /* lock mode */
  238. wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
  239. }
  240. static void mpu_init_34xx(u32 sil_index, u32 clk_index)
  241. {
  242. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  243. dpll_param *ptr = (dpll_param *) get_mpu_dpll_param();
  244. /* Moving to the right sysclk and ES rev base */
  245. ptr = ptr + (3 * clk_index) + sil_index;
  246. /* MPU DPLL (unlocked already) */
  247. /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
  248. sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
  249. /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
  250. sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
  251. /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
  252. sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
  253. /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
  254. sr32(&prcm_base->clken_pll_mpu, 4, 4, ptr->fsel);
  255. }
  256. static void iva_init_34xx(u32 sil_index, u32 clk_index)
  257. {
  258. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  259. dpll_param *ptr = (dpll_param *) get_iva_dpll_param();
  260. /* Moving to the right sysclk and ES rev base */
  261. ptr = ptr + (3 * clk_index) + sil_index;
  262. /* IVA DPLL */
  263. /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
  264. sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
  265. wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
  266. /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
  267. sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
  268. /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
  269. sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
  270. /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
  271. sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
  272. /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
  273. sr32(&prcm_base->clken_pll_iva2, 4, 4, ptr->fsel);
  274. /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
  275. sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
  276. wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
  277. }
  278. /*
  279. * OMAP3630 specific functions
  280. */
  281. static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
  282. {
  283. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  284. dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param();
  285. void (*f_lock_pll) (u32, u32, u32, u32);
  286. int xip_safe, p0, p1, p2, p3;
  287. xip_safe = is_running_in_sram();
  288. /* Moving it to the right sysclk base */
  289. ptr += clk_index;
  290. if (xip_safe) {
  291. /* CORE DPLL */
  292. /* Select relock bypass: CM_CLKEN_PLL[0:2] */
  293. sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
  294. wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
  295. LDELAY);
  296. /* CM_CLKSEL1_EMU[DIV_DPLL3] */
  297. sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
  298. /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
  299. sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
  300. /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
  301. sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
  302. /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
  303. sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
  304. /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
  305. sr32(&prcm_base->clksel1_pll, 6, 1, 0);
  306. /* SSI */
  307. sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
  308. /* FSUSB */
  309. sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
  310. /* L4 */
  311. sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
  312. /* L3 */
  313. sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
  314. /* GFX */
  315. sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV_36X);
  316. /* RESET MGR */
  317. sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
  318. /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
  319. sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);
  320. /* LOCK MODE */
  321. sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
  322. wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
  323. LDELAY);
  324. } else if (is_running_in_flash()) {
  325. /*
  326. * if running from flash, jump to small relocated code
  327. * area in SRAM.
  328. */
  329. f_lock_pll = (void *) (SRAM_CLK_CODE);
  330. p0 = readl(&prcm_base->clken_pll);
  331. sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
  332. /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
  333. sr32(&p0, 4, 4, ptr->fsel);
  334. p1 = readl(&prcm_base->clksel1_pll);
  335. /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
  336. sr32(&p1, 27, 5, ptr->m2);
  337. /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
  338. sr32(&p1, 16, 11, ptr->m);
  339. /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
  340. sr32(&p1, 8, 7, ptr->n);
  341. /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
  342. sr32(&p1, 6, 1, 0);
  343. p2 = readl(&prcm_base->clksel_core);
  344. /* SSI */
  345. sr32(&p2, 8, 4, CORE_SSI_DIV);
  346. /* FSUSB */
  347. sr32(&p2, 4, 2, CORE_FUSB_DIV);
  348. /* L4 */
  349. sr32(&p2, 2, 2, CORE_L4_DIV);
  350. /* L3 */
  351. sr32(&p2, 0, 2, CORE_L3_DIV);
  352. p3 = (u32)&prcm_base->idlest_ckgen;
  353. (*f_lock_pll) (p0, p1, p2, p3);
  354. }
  355. }
  356. static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
  357. {
  358. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  359. struct dpll_per_36x_param *ptr;
  360. ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();
  361. /* Moving it to the right sysclk base */
  362. ptr += clk_index;
  363. /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
  364. sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
  365. wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
  366. /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
  367. sr32(&prcm_base->clksel1_emu, 24, 6, ptr->m6);
  368. /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
  369. sr32(&prcm_base->clksel_cam, 0, 6, ptr->m5);
  370. /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
  371. sr32(&prcm_base->clksel_dss, 0, 6, ptr->m4);
  372. /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
  373. sr32(&prcm_base->clksel_dss, 8, 6, ptr->m3);
  374. /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
  375. sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
  376. /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
  377. sr32(&prcm_base->clksel2_pll, 8, 12, ptr->m);
  378. /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
  379. sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
  380. /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
  381. sr32(&prcm_base->clksel_core, 12, 2, ptr->m2div);
  382. /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
  383. sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
  384. wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
  385. }
  386. static void dpll5_init_36xx(u32 sil_index, u32 clk_index)
  387. {
  388. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  389. dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param();
  390. /* Moving it to the right sysclk base */
  391. ptr = ptr + clk_index;
  392. /* PER2 DPLL (DPLL5) */
  393. sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP);
  394. wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
  395. sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */
  396. sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */
  397. sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/
  398. sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK); /* lock mode */
  399. wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
  400. }
  401. static void mpu_init_36xx(u32 sil_index, u32 clk_index)
  402. {
  403. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  404. dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param();
  405. /* Moving to the right sysclk */
  406. ptr += clk_index;
  407. /* MPU DPLL (unlocked already */
  408. /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
  409. sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
  410. /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
  411. sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
  412. /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
  413. sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
  414. }
  415. static void iva_init_36xx(u32 sil_index, u32 clk_index)
  416. {
  417. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  418. dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param();
  419. /* Moving to the right sysclk */
  420. ptr += clk_index;
  421. /* IVA DPLL */
  422. /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
  423. sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
  424. wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
  425. /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
  426. sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
  427. /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
  428. sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
  429. /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
  430. sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
  431. /* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
  432. sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
  433. wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
  434. }
  435. /******************************************************************************
  436. * prcm_init() - inits clocks for PRCM as defined in clocks.h
  437. * called from SRAM, or Flash (using temp SRAM stack).
  438. *****************************************************************************/
  439. void prcm_init(void)
  440. {
  441. u32 osc_clk = 0, sys_clkin_sel;
  442. u32 clk_index, sil_index = 0;
  443. struct prm *prm_base = (struct prm *)PRM_BASE;
  444. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  445. /*
  446. * Gauge the input clock speed and find out the sys_clkin_sel
  447. * value corresponding to the input clock.
  448. */
  449. osc_clk = get_osc_clk_speed();
  450. get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
  451. /* set input crystal speed */
  452. sr32(&prm_base->clksel, 0, 3, sys_clkin_sel);
  453. /* If the input clock is greater than 19.2M always divide/2 */
  454. if (sys_clkin_sel > 2) {
  455. /* input clock divider */
  456. sr32(&prm_base->clksrc_ctrl, 6, 2, 2);
  457. clk_index = sys_clkin_sel / 2;
  458. } else {
  459. /* input clock divider */
  460. sr32(&prm_base->clksrc_ctrl, 6, 2, 1);
  461. clk_index = sys_clkin_sel;
  462. }
  463. if (get_cpu_family() == CPU_OMAP36XX) {
  464. /*
  465. * In warm reset conditions on OMAP36xx/AM/DM37xx
  466. * the rom code incorrectly sets the DPLL4 clock
  467. * input divider to /6.5. Section 3.5.3.3.3.2.1 of
  468. * the AM/DM37x TRM explains that the /6.5 divider
  469. * is used only when the input clock is 13MHz.
  470. *
  471. * If the part is in this cpu family *and* the input
  472. * clock *is not* 13 MHz, then reset the DPLL4 clock
  473. * input divider to /1 as it should never set to /6.5
  474. * in this case.
  475. */
  476. if (sys_clkin_sel != 1) /* 13 MHz */
  477. /* Bit 8: DPLL4_CLKINP_DIV */
  478. sr32(&prm_base->clksrc_ctrl, 8, 1, 0);
  479. /* Unlock MPU DPLL (slows things down, and needed later) */
  480. sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
  481. wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
  482. LDELAY);
  483. dpll3_init_36xx(0, clk_index);
  484. dpll4_init_36xx(0, clk_index);
  485. dpll5_init_36xx(0, clk_index);
  486. iva_init_36xx(0, clk_index);
  487. mpu_init_36xx(0, clk_index);
  488. /* Lock MPU DPLL to set frequency */
  489. sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
  490. wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
  491. LDELAY);
  492. } else {
  493. /*
  494. * The DPLL tables are defined according to sysclk value and
  495. * silicon revision. The clk_index value will be used to get
  496. * the values for that input sysclk from the DPLL param table
  497. * and sil_index will get the values for that SysClk for the
  498. * appropriate silicon rev.
  499. */
  500. if (((get_cpu_family() == CPU_OMAP34XX)
  501. && (get_cpu_rev() >= CPU_3XX_ES20)) ||
  502. (get_cpu_family() == CPU_AM35XX))
  503. sil_index = 1;
  504. /* Unlock MPU DPLL (slows things down, and needed later) */
  505. sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
  506. wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
  507. LDELAY);
  508. dpll3_init_34xx(sil_index, clk_index);
  509. dpll4_init_34xx(sil_index, clk_index);
  510. dpll5_init_34xx(sil_index, clk_index);
  511. if (get_cpu_family() != CPU_AM35XX)
  512. iva_init_34xx(sil_index, clk_index);
  513. mpu_init_34xx(sil_index, clk_index);
  514. /* Lock MPU DPLL to set frequency */
  515. sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
  516. wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
  517. LDELAY);
  518. }
  519. /* Set up GPTimers to sys_clk source only */
  520. sr32(&prcm_base->clksel_per, 0, 8, 0xff);
  521. sr32(&prcm_base->clksel_wkup, 0, 1, 1);
  522. sdelay(5000);
  523. }
  524. /*
  525. * Enable usb ehci uhh, tll clocks
  526. */
  527. void ehci_clocks_enable(void)
  528. {
  529. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  530. /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
  531. sr32(&prcm_base->iclken_usbhost, 0, 1, 1);
  532. /*
  533. * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
  534. * and USBHOST_120M_FCLK (USBHOST_FCLK2)
  535. */
  536. sr32(&prcm_base->fclken_usbhost, 0, 2, 3);
  537. /* Enable USBTTL_ICLK */
  538. sr32(&prcm_base->iclken3_core, 2, 1, 1);
  539. /* Enable USBTTL_FCLK */
  540. sr32(&prcm_base->fclken3_core, 2, 1, 1);
  541. }
  542. /******************************************************************************
  543. * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
  544. *****************************************************************************/
  545. void per_clocks_enable(void)
  546. {
  547. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  548. /* Enable GP2 timer. */
  549. sr32(&prcm_base->clksel_per, 0, 1, 0x1); /* GPT2 = sys clk */
  550. sr32(&prcm_base->iclken_per, 3, 1, 0x1); /* ICKen GPT2 */
  551. sr32(&prcm_base->fclken_per, 3, 1, 0x1); /* FCKen GPT2 */
  552. #ifdef CONFIG_SYS_NS16550
  553. /* Enable UART1 clocks */
  554. sr32(&prcm_base->fclken1_core, 13, 1, 0x1);
  555. sr32(&prcm_base->iclken1_core, 13, 1, 0x1);
  556. /* UART 3 Clocks */
  557. sr32(&prcm_base->fclken_per, 11, 1, 0x1);
  558. sr32(&prcm_base->iclken_per, 11, 1, 0x1);
  559. #endif
  560. #ifdef CONFIG_OMAP3_GPIO_2
  561. sr32(&prcm_base->fclken_per, 13, 1, 1);
  562. sr32(&prcm_base->iclken_per, 13, 1, 1);
  563. #endif
  564. #ifdef CONFIG_OMAP3_GPIO_3
  565. sr32(&prcm_base->fclken_per, 14, 1, 1);
  566. sr32(&prcm_base->iclken_per, 14, 1, 1);
  567. #endif
  568. #ifdef CONFIG_OMAP3_GPIO_4
  569. sr32(&prcm_base->fclken_per, 15, 1, 1);
  570. sr32(&prcm_base->iclken_per, 15, 1, 1);
  571. #endif
  572. #ifdef CONFIG_OMAP3_GPIO_5
  573. sr32(&prcm_base->fclken_per, 16, 1, 1);
  574. sr32(&prcm_base->iclken_per, 16, 1, 1);
  575. #endif
  576. #ifdef CONFIG_OMAP3_GPIO_6
  577. sr32(&prcm_base->fclken_per, 17, 1, 1);
  578. sr32(&prcm_base->iclken_per, 17, 1, 1);
  579. #endif
  580. #ifdef CONFIG_DRIVER_OMAP34XX_I2C
  581. /* Turn on all 3 I2C clocks */
  582. sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
  583. sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */
  584. #endif
  585. /* Enable the ICLK for 32K Sync Timer as its used in udelay */
  586. sr32(&prcm_base->iclken_wkup, 2, 1, 0x1);
  587. if (get_cpu_family() != CPU_AM35XX)
  588. sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
  589. sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON);
  590. sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON);
  591. sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON);
  592. sr32(&prcm_base->fclken_wkup, 0, 32, FCK_WKUP_ON);
  593. sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON);
  594. sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON);
  595. sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON);
  596. if (get_cpu_family() != CPU_AM35XX) {
  597. sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
  598. sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
  599. }
  600. sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
  601. sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);
  602. sdelay(1000);
  603. }