soc.c 7.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285
  1. /*
  2. * (C) Copyright 2007
  3. * Sascha Hauer, Pengutronix
  4. *
  5. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <asm/errno.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/imx-common/boot_mode.h>
  16. #include <asm/imx-common/dma.h>
  17. #include <stdbool.h>
  18. #include <asm/arch/mxc_hdmi.h>
  19. #include <asm/arch/crm_regs.h>
  20. struct scu_regs {
  21. u32 ctrl;
  22. u32 config;
  23. u32 status;
  24. u32 invalidate;
  25. u32 fpga_rev;
  26. };
  27. u32 get_cpu_rev(void)
  28. {
  29. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  30. u32 reg = readl(&anatop->digprog_sololite);
  31. u32 type = ((reg >> 16) & 0xff);
  32. if (type != MXC_CPU_MX6SL) {
  33. reg = readl(&anatop->digprog);
  34. type = ((reg >> 16) & 0xff);
  35. if (type == MXC_CPU_MX6DL) {
  36. struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  37. u32 cfg = readl(&scu->config) & 3;
  38. if (!cfg)
  39. type = MXC_CPU_MX6SOLO;
  40. }
  41. }
  42. reg &= 0xff; /* mx6 silicon revision */
  43. return (type << 12) | (reg + 0x10);
  44. }
  45. #ifdef CONFIG_REVISION_TAG
  46. u32 __weak get_board_rev(void)
  47. {
  48. u32 cpurev = get_cpu_rev();
  49. u32 type = ((cpurev >> 12) & 0xff);
  50. if (type == MXC_CPU_MX6SOLO)
  51. cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
  52. return cpurev;
  53. }
  54. #endif
  55. void init_aips(void)
  56. {
  57. struct aipstz_regs *aips1, *aips2;
  58. aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
  59. aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
  60. /*
  61. * Set all MPROTx to be non-bufferable, trusted for R/W,
  62. * not forced to user-mode.
  63. */
  64. writel(0x77777777, &aips1->mprot0);
  65. writel(0x77777777, &aips1->mprot1);
  66. writel(0x77777777, &aips2->mprot0);
  67. writel(0x77777777, &aips2->mprot1);
  68. /*
  69. * Set all OPACRx to be non-bufferable, not require
  70. * supervisor privilege level for access,allow for
  71. * write access and untrusted master access.
  72. */
  73. writel(0x00000000, &aips1->opacr0);
  74. writel(0x00000000, &aips1->opacr1);
  75. writel(0x00000000, &aips1->opacr2);
  76. writel(0x00000000, &aips1->opacr3);
  77. writel(0x00000000, &aips1->opacr4);
  78. writel(0x00000000, &aips2->opacr0);
  79. writel(0x00000000, &aips2->opacr1);
  80. writel(0x00000000, &aips2->opacr2);
  81. writel(0x00000000, &aips2->opacr3);
  82. writel(0x00000000, &aips2->opacr4);
  83. }
  84. /*
  85. * Set the VDDSOC
  86. *
  87. * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
  88. * them to the specified millivolt level.
  89. * Possible values are from 0.725V to 1.450V in steps of
  90. * 0.025V (25mV).
  91. */
  92. void set_vddsoc(u32 mv)
  93. {
  94. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  95. u32 val, reg = readl(&anatop->reg_core);
  96. if (mv < 725)
  97. val = 0x00; /* Power gated off */
  98. else if (mv > 1450)
  99. val = 0x1F; /* Power FET switched full on. No regulation */
  100. else
  101. val = (mv - 700) / 25;
  102. /*
  103. * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
  104. * and set them to the calculated value (0.7V + val * 0.25V)
  105. */
  106. reg = (reg & ~(0x1F << 18)) | (val << 18);
  107. writel(reg, &anatop->reg_core);
  108. }
  109. static void imx_set_wdog_powerdown(bool enable)
  110. {
  111. struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
  112. struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
  113. /* Write to the PDE (Power Down Enable) bit */
  114. writew(enable, &wdog1->wmcr);
  115. writew(enable, &wdog2->wmcr);
  116. }
  117. int arch_cpu_init(void)
  118. {
  119. init_aips();
  120. set_vddsoc(1200); /* Set VDDSOC to 1.2V */
  121. imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
  122. #ifdef CONFIG_APBH_DMA
  123. /* Start APBH DMA */
  124. mxs_dma_init();
  125. #endif
  126. return 0;
  127. }
  128. #ifndef CONFIG_SYS_DCACHE_OFF
  129. void enable_caches(void)
  130. {
  131. /* Enable D-cache. I-cache is already enabled in start.S */
  132. dcache_enable();
  133. }
  134. #endif
  135. #if defined(CONFIG_FEC_MXC)
  136. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  137. {
  138. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  139. struct fuse_bank *bank = &ocotp->bank[4];
  140. struct fuse_bank4_regs *fuse =
  141. (struct fuse_bank4_regs *)bank->fuse_regs;
  142. u32 value = readl(&fuse->mac_addr_high);
  143. mac[0] = (value >> 8);
  144. mac[1] = value ;
  145. value = readl(&fuse->mac_addr_low);
  146. mac[2] = value >> 24 ;
  147. mac[3] = value >> 16 ;
  148. mac[4] = value >> 8 ;
  149. mac[5] = value ;
  150. }
  151. #endif
  152. void boot_mode_apply(unsigned cfg_val)
  153. {
  154. unsigned reg;
  155. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  156. writel(cfg_val, &psrc->gpr9);
  157. reg = readl(&psrc->gpr10);
  158. if (cfg_val)
  159. reg |= 1 << 28;
  160. else
  161. reg &= ~(1 << 28);
  162. writel(reg, &psrc->gpr10);
  163. }
  164. /*
  165. * cfg_val will be used for
  166. * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
  167. * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
  168. * to SBMR1, which will determine the boot device.
  169. */
  170. const struct boot_mode soc_boot_modes[] = {
  171. {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
  172. /* reserved value should start rom usb */
  173. {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
  174. {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
  175. {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
  176. {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
  177. {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
  178. {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
  179. /* 4 bit bus width */
  180. {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
  181. {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  182. {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  183. {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
  184. {NULL, 0},
  185. };
  186. void s_init(void)
  187. {
  188. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  189. int is_6q = is_cpu_type(MXC_CPU_MX6Q);
  190. u32 mask480;
  191. u32 mask528;
  192. /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
  193. * to make sure PFD is working right, otherwise, PFDs may
  194. * not output clock after reset, MX6DL and MX6SL have added 396M pfd
  195. * workaround in ROM code, as bus clock need it
  196. */
  197. mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
  198. ANATOP_PFD_CLKGATE_MASK(1) |
  199. ANATOP_PFD_CLKGATE_MASK(2) |
  200. ANATOP_PFD_CLKGATE_MASK(3);
  201. mask528 = ANATOP_PFD_CLKGATE_MASK(0) |
  202. ANATOP_PFD_CLKGATE_MASK(1) |
  203. ANATOP_PFD_CLKGATE_MASK(3);
  204. /*
  205. * Don't reset PFD2 on DL/S
  206. */
  207. if (is_6q)
  208. mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
  209. writel(mask480, &anatop->pfd_480_set);
  210. writel(mask528, &anatop->pfd_528_set);
  211. writel(mask480, &anatop->pfd_480_clr);
  212. writel(mask528, &anatop->pfd_528_clr);
  213. }
  214. #ifdef CONFIG_IMX_HDMI
  215. void imx_enable_hdmi_phy(void)
  216. {
  217. struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
  218. u8 reg;
  219. reg = readb(&hdmi->phy_conf0);
  220. reg |= HDMI_PHY_CONF0_PDZ_MASK;
  221. writeb(reg, &hdmi->phy_conf0);
  222. udelay(3000);
  223. reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
  224. writeb(reg, &hdmi->phy_conf0);
  225. udelay(3000);
  226. reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
  227. writeb(reg, &hdmi->phy_conf0);
  228. writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
  229. }
  230. void imx_setup_hdmi(void)
  231. {
  232. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  233. struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
  234. int reg;
  235. /* Turn on HDMI PHY clock */
  236. reg = readl(&mxc_ccm->CCGR2);
  237. reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
  238. MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
  239. writel(reg, &mxc_ccm->CCGR2);
  240. writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
  241. reg = readl(&mxc_ccm->chsccdr);
  242. reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
  243. MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
  244. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
  245. reg |= (CHSCCDR_PODF_DIVIDE_BY_3
  246. << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
  247. |(CHSCCDR_IPU_PRE_CLK_540M_PFD
  248. << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
  249. writel(reg, &mxc_ccm->chsccdr);
  250. }
  251. #endif