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- /*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
- #include <common.h>
- #include <asm/errno.h>
- #include <asm/io.h>
- #include <asm/arch/imx-regs.h>
- #include <asm/arch/clock.h>
- #include <asm/arch/sys_proto.h>
- #include <asm/imx-common/boot_mode.h>
- #include <asm/imx-common/dma.h>
- #include <stdbool.h>
- #include <asm/arch/mxc_hdmi.h>
- #include <asm/arch/crm_regs.h>
- struct scu_regs {
- u32 ctrl;
- u32 config;
- u32 status;
- u32 invalidate;
- u32 fpga_rev;
- };
- u32 get_cpu_rev(void)
- {
- struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- u32 reg = readl(&anatop->digprog_sololite);
- u32 type = ((reg >> 16) & 0xff);
- if (type != MXC_CPU_MX6SL) {
- reg = readl(&anatop->digprog);
- type = ((reg >> 16) & 0xff);
- if (type == MXC_CPU_MX6DL) {
- struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
- u32 cfg = readl(&scu->config) & 3;
- if (!cfg)
- type = MXC_CPU_MX6SOLO;
- }
- }
- reg &= 0xff; /* mx6 silicon revision */
- return (type << 12) | (reg + 0x10);
- }
- #ifdef CONFIG_REVISION_TAG
- u32 __weak get_board_rev(void)
- {
- u32 cpurev = get_cpu_rev();
- u32 type = ((cpurev >> 12) & 0xff);
- if (type == MXC_CPU_MX6SOLO)
- cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
- return cpurev;
- }
- #endif
- void init_aips(void)
- {
- struct aipstz_regs *aips1, *aips2;
- aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
- aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
- /*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- writel(0x77777777, &aips1->mprot0);
- writel(0x77777777, &aips1->mprot1);
- writel(0x77777777, &aips2->mprot0);
- writel(0x77777777, &aips2->mprot1);
- /*
- * Set all OPACRx to be non-bufferable, not require
- * supervisor privilege level for access,allow for
- * write access and untrusted master access.
- */
- writel(0x00000000, &aips1->opacr0);
- writel(0x00000000, &aips1->opacr1);
- writel(0x00000000, &aips1->opacr2);
- writel(0x00000000, &aips1->opacr3);
- writel(0x00000000, &aips1->opacr4);
- writel(0x00000000, &aips2->opacr0);
- writel(0x00000000, &aips2->opacr1);
- writel(0x00000000, &aips2->opacr2);
- writel(0x00000000, &aips2->opacr3);
- writel(0x00000000, &aips2->opacr4);
- }
- /*
- * Set the VDDSOC
- *
- * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
- * them to the specified millivolt level.
- * Possible values are from 0.725V to 1.450V in steps of
- * 0.025V (25mV).
- */
- void set_vddsoc(u32 mv)
- {
- struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- u32 val, reg = readl(&anatop->reg_core);
- if (mv < 725)
- val = 0x00; /* Power gated off */
- else if (mv > 1450)
- val = 0x1F; /* Power FET switched full on. No regulation */
- else
- val = (mv - 700) / 25;
- /*
- * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
- * and set them to the calculated value (0.7V + val * 0.25V)
- */
- reg = (reg & ~(0x1F << 18)) | (val << 18);
- writel(reg, &anatop->reg_core);
- }
- static void imx_set_wdog_powerdown(bool enable)
- {
- struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
- struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
- /* Write to the PDE (Power Down Enable) bit */
- writew(enable, &wdog1->wmcr);
- writew(enable, &wdog2->wmcr);
- }
- int arch_cpu_init(void)
- {
- init_aips();
- set_vddsoc(1200); /* Set VDDSOC to 1.2V */
- imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
- #ifdef CONFIG_APBH_DMA
- /* Start APBH DMA */
- mxs_dma_init();
- #endif
- return 0;
- }
- #ifndef CONFIG_SYS_DCACHE_OFF
- void enable_caches(void)
- {
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
- }
- #endif
- #if defined(CONFIG_FEC_MXC)
- void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
- {
- struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- struct fuse_bank *bank = &ocotp->bank[4];
- struct fuse_bank4_regs *fuse =
- (struct fuse_bank4_regs *)bank->fuse_regs;
- u32 value = readl(&fuse->mac_addr_high);
- mac[0] = (value >> 8);
- mac[1] = value ;
- value = readl(&fuse->mac_addr_low);
- mac[2] = value >> 24 ;
- mac[3] = value >> 16 ;
- mac[4] = value >> 8 ;
- mac[5] = value ;
- }
- #endif
- void boot_mode_apply(unsigned cfg_val)
- {
- unsigned reg;
- struct src *psrc = (struct src *)SRC_BASE_ADDR;
- writel(cfg_val, &psrc->gpr9);
- reg = readl(&psrc->gpr10);
- if (cfg_val)
- reg |= 1 << 28;
- else
- reg &= ~(1 << 28);
- writel(reg, &psrc->gpr10);
- }
- /*
- * cfg_val will be used for
- * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
- * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
- * to SBMR1, which will determine the boot device.
- */
- const struct boot_mode soc_boot_modes[] = {
- {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
- /* reserved value should start rom usb */
- {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
- {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
- {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
- {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
- {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
- {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
- /* 4 bit bus width */
- {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
- {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
- {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
- {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
- {NULL, 0},
- };
- void s_init(void)
- {
- struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- int is_6q = is_cpu_type(MXC_CPU_MX6Q);
- u32 mask480;
- u32 mask528;
- /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
- * to make sure PFD is working right, otherwise, PFDs may
- * not output clock after reset, MX6DL and MX6SL have added 396M pfd
- * workaround in ROM code, as bus clock need it
- */
- mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
- ANATOP_PFD_CLKGATE_MASK(1) |
- ANATOP_PFD_CLKGATE_MASK(2) |
- ANATOP_PFD_CLKGATE_MASK(3);
- mask528 = ANATOP_PFD_CLKGATE_MASK(0) |
- ANATOP_PFD_CLKGATE_MASK(1) |
- ANATOP_PFD_CLKGATE_MASK(3);
- /*
- * Don't reset PFD2 on DL/S
- */
- if (is_6q)
- mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
- writel(mask480, &anatop->pfd_480_set);
- writel(mask528, &anatop->pfd_528_set);
- writel(mask480, &anatop->pfd_480_clr);
- writel(mask528, &anatop->pfd_528_clr);
- }
- #ifdef CONFIG_IMX_HDMI
- void imx_enable_hdmi_phy(void)
- {
- struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
- u8 reg;
- reg = readb(&hdmi->phy_conf0);
- reg |= HDMI_PHY_CONF0_PDZ_MASK;
- writeb(reg, &hdmi->phy_conf0);
- udelay(3000);
- reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
- writeb(reg, &hdmi->phy_conf0);
- udelay(3000);
- reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
- writeb(reg, &hdmi->phy_conf0);
- writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
- }
- void imx_setup_hdmi(void)
- {
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
- int reg;
- /* Turn on HDMI PHY clock */
- reg = readl(&mxc_ccm->CCGR2);
- reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
- MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
- writel(reg, &mxc_ccm->CCGR2);
- writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
- reg = readl(&mxc_ccm->chsccdr);
- reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
- MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
- MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
- reg |= (CHSCCDR_PODF_DIVIDE_BY_3
- << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
- |(CHSCCDR_IPU_PRE_CLK_540M_PFD
- << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
- writel(reg, &mxc_ccm->chsccdr);
- }
- #endif
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