e1000.c 154 KB

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  1. /**************************************************************************
  2. Intel Pro 1000 for ppcboot/das-u-boot
  3. Drivers are port from Intel's Linux driver e1000-4.3.15
  4. and from Etherboot pro 1000 driver by mrakes at vivato dot net
  5. tested on both gig copper and gig fiber boards
  6. ***************************************************************************/
  7. /*******************************************************************************
  8. Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
  9. This program is free software; you can redistribute it and/or modify it
  10. under the terms of the GNU General Public License as published by the Free
  11. Software Foundation; either version 2 of the License, or (at your option)
  12. any later version.
  13. This program is distributed in the hope that it will be useful, but WITHOUT
  14. ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15. FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  16. more details.
  17. You should have received a copy of the GNU General Public License along with
  18. this program; if not, write to the Free Software Foundation, Inc., 59
  19. Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20. The full GNU General Public License is included in this distribution in the
  21. file called LICENSE.
  22. Contact Information:
  23. Linux NICS <linux.nics@intel.com>
  24. Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25. *******************************************************************************/
  26. /*
  27. * Copyright (C) Archway Digital Solutions.
  28. *
  29. * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
  30. * 2/9/2002
  31. *
  32. * Copyright (C) Linux Networx.
  33. * Massive upgrade to work with the new intel gigabit NICs.
  34. * <ebiederman at lnxi dot com>
  35. *
  36. * Copyright 2011 Freescale Semiconductor, Inc.
  37. */
  38. #include "e1000.h"
  39. #define TOUT_LOOP 100000
  40. #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
  41. #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
  42. #define E1000_DEFAULT_PCI_PBA 0x00000030
  43. #define E1000_DEFAULT_PCIE_PBA 0x000a0026
  44. /* NIC specific static variables go here */
  45. static char tx_pool[128 + 16];
  46. static char rx_pool[128 + 16];
  47. static char packet[2096];
  48. static struct e1000_tx_desc *tx_base;
  49. static struct e1000_rx_desc *rx_base;
  50. static int tx_tail;
  51. static int rx_tail, rx_last;
  52. static struct pci_device_id e1000_supported[] = {
  53. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542},
  54. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER},
  55. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER},
  56. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER},
  57. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER},
  58. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER},
  59. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM},
  60. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM},
  61. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER},
  62. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER},
  63. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
  64. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
  65. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
  66. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER},
  67. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
  68. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
  69. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
  70. /* E1000 PCIe card */
  71. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER},
  72. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER },
  73. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES },
  74. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER},
  75. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER},
  76. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER},
  77. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE},
  78. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL},
  79. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD},
  80. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER},
  81. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER},
  82. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES},
  83. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI},
  84. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E},
  85. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT},
  86. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L},
  87. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L},
  88. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3},
  89. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT},
  90. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
  91. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
  92. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
  93. {}
  94. };
  95. /* Function forward declarations */
  96. static int e1000_setup_link(struct eth_device *nic);
  97. static int e1000_setup_fiber_link(struct eth_device *nic);
  98. static int e1000_setup_copper_link(struct eth_device *nic);
  99. static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
  100. static void e1000_config_collision_dist(struct e1000_hw *hw);
  101. static int e1000_config_mac_to_phy(struct e1000_hw *hw);
  102. static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
  103. static int e1000_check_for_link(struct eth_device *nic);
  104. static int e1000_wait_autoneg(struct e1000_hw *hw);
  105. static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
  106. uint16_t * duplex);
  107. static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
  108. uint16_t * phy_data);
  109. static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
  110. uint16_t phy_data);
  111. static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
  112. static int e1000_phy_reset(struct e1000_hw *hw);
  113. static int e1000_detect_gig_phy(struct e1000_hw *hw);
  114. static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
  115. static void e1000_set_media_type(struct e1000_hw *hw);
  116. static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
  117. static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
  118. static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
  119. uint16_t words,
  120. uint16_t *data);
  121. /******************************************************************************
  122. * Raises the EEPROM's clock input.
  123. *
  124. * hw - Struct containing variables accessed by shared code
  125. * eecd - EECD's current value
  126. *****************************************************************************/
  127. void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
  128. {
  129. /* Raise the clock input to the EEPROM (by setting the SK bit), and then
  130. * wait 50 microseconds.
  131. */
  132. *eecd = *eecd | E1000_EECD_SK;
  133. E1000_WRITE_REG(hw, EECD, *eecd);
  134. E1000_WRITE_FLUSH(hw);
  135. udelay(50);
  136. }
  137. /******************************************************************************
  138. * Lowers the EEPROM's clock input.
  139. *
  140. * hw - Struct containing variables accessed by shared code
  141. * eecd - EECD's current value
  142. *****************************************************************************/
  143. void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
  144. {
  145. /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
  146. * wait 50 microseconds.
  147. */
  148. *eecd = *eecd & ~E1000_EECD_SK;
  149. E1000_WRITE_REG(hw, EECD, *eecd);
  150. E1000_WRITE_FLUSH(hw);
  151. udelay(50);
  152. }
  153. /******************************************************************************
  154. * Shift data bits out to the EEPROM.
  155. *
  156. * hw - Struct containing variables accessed by shared code
  157. * data - data to send to the EEPROM
  158. * count - number of bits to shift out
  159. *****************************************************************************/
  160. static void
  161. e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
  162. {
  163. uint32_t eecd;
  164. uint32_t mask;
  165. /* We need to shift "count" bits out to the EEPROM. So, value in the
  166. * "data" parameter will be shifted out to the EEPROM one bit at a time.
  167. * In order to do this, "data" must be broken down into bits.
  168. */
  169. mask = 0x01 << (count - 1);
  170. eecd = E1000_READ_REG(hw, EECD);
  171. eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
  172. do {
  173. /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
  174. * and then raising and then lowering the clock (the SK bit controls
  175. * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
  176. * by setting "DI" to "0" and then raising and then lowering the clock.
  177. */
  178. eecd &= ~E1000_EECD_DI;
  179. if (data & mask)
  180. eecd |= E1000_EECD_DI;
  181. E1000_WRITE_REG(hw, EECD, eecd);
  182. E1000_WRITE_FLUSH(hw);
  183. udelay(50);
  184. e1000_raise_ee_clk(hw, &eecd);
  185. e1000_lower_ee_clk(hw, &eecd);
  186. mask = mask >> 1;
  187. } while (mask);
  188. /* We leave the "DI" bit set to "0" when we leave this routine. */
  189. eecd &= ~E1000_EECD_DI;
  190. E1000_WRITE_REG(hw, EECD, eecd);
  191. }
  192. /******************************************************************************
  193. * Shift data bits in from the EEPROM
  194. *
  195. * hw - Struct containing variables accessed by shared code
  196. *****************************************************************************/
  197. static uint16_t
  198. e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
  199. {
  200. uint32_t eecd;
  201. uint32_t i;
  202. uint16_t data;
  203. /* In order to read a register from the EEPROM, we need to shift 'count'
  204. * bits in from the EEPROM. Bits are "shifted in" by raising the clock
  205. * input to the EEPROM (setting the SK bit), and then reading the
  206. * value of the "DO" bit. During this "shifting in" process the
  207. * "DI" bit should always be clear.
  208. */
  209. eecd = E1000_READ_REG(hw, EECD);
  210. eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
  211. data = 0;
  212. for (i = 0; i < count; i++) {
  213. data = data << 1;
  214. e1000_raise_ee_clk(hw, &eecd);
  215. eecd = E1000_READ_REG(hw, EECD);
  216. eecd &= ~(E1000_EECD_DI);
  217. if (eecd & E1000_EECD_DO)
  218. data |= 1;
  219. e1000_lower_ee_clk(hw, &eecd);
  220. }
  221. return data;
  222. }
  223. /******************************************************************************
  224. * Returns EEPROM to a "standby" state
  225. *
  226. * hw - Struct containing variables accessed by shared code
  227. *****************************************************************************/
  228. void e1000_standby_eeprom(struct e1000_hw *hw)
  229. {
  230. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  231. uint32_t eecd;
  232. eecd = E1000_READ_REG(hw, EECD);
  233. if (eeprom->type == e1000_eeprom_microwire) {
  234. eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
  235. E1000_WRITE_REG(hw, EECD, eecd);
  236. E1000_WRITE_FLUSH(hw);
  237. udelay(eeprom->delay_usec);
  238. /* Clock high */
  239. eecd |= E1000_EECD_SK;
  240. E1000_WRITE_REG(hw, EECD, eecd);
  241. E1000_WRITE_FLUSH(hw);
  242. udelay(eeprom->delay_usec);
  243. /* Select EEPROM */
  244. eecd |= E1000_EECD_CS;
  245. E1000_WRITE_REG(hw, EECD, eecd);
  246. E1000_WRITE_FLUSH(hw);
  247. udelay(eeprom->delay_usec);
  248. /* Clock low */
  249. eecd &= ~E1000_EECD_SK;
  250. E1000_WRITE_REG(hw, EECD, eecd);
  251. E1000_WRITE_FLUSH(hw);
  252. udelay(eeprom->delay_usec);
  253. } else if (eeprom->type == e1000_eeprom_spi) {
  254. /* Toggle CS to flush commands */
  255. eecd |= E1000_EECD_CS;
  256. E1000_WRITE_REG(hw, EECD, eecd);
  257. E1000_WRITE_FLUSH(hw);
  258. udelay(eeprom->delay_usec);
  259. eecd &= ~E1000_EECD_CS;
  260. E1000_WRITE_REG(hw, EECD, eecd);
  261. E1000_WRITE_FLUSH(hw);
  262. udelay(eeprom->delay_usec);
  263. }
  264. }
  265. /***************************************************************************
  266. * Description: Determines if the onboard NVM is FLASH or EEPROM.
  267. *
  268. * hw - Struct containing variables accessed by shared code
  269. ****************************************************************************/
  270. static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
  271. {
  272. uint32_t eecd = 0;
  273. DEBUGFUNC();
  274. if (hw->mac_type == e1000_ich8lan)
  275. return false;
  276. if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
  277. eecd = E1000_READ_REG(hw, EECD);
  278. /* Isolate bits 15 & 16 */
  279. eecd = ((eecd >> 15) & 0x03);
  280. /* If both bits are set, device is Flash type */
  281. if (eecd == 0x03)
  282. return false;
  283. }
  284. return true;
  285. }
  286. /******************************************************************************
  287. * Prepares EEPROM for access
  288. *
  289. * hw - Struct containing variables accessed by shared code
  290. *
  291. * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
  292. * function should be called before issuing a command to the EEPROM.
  293. *****************************************************************************/
  294. int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
  295. {
  296. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  297. uint32_t eecd, i = 0;
  298. DEBUGFUNC();
  299. if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
  300. return -E1000_ERR_SWFW_SYNC;
  301. eecd = E1000_READ_REG(hw, EECD);
  302. if (hw->mac_type != e1000_82573 || hw->mac_type != e1000_82574) {
  303. /* Request EEPROM Access */
  304. if (hw->mac_type > e1000_82544) {
  305. eecd |= E1000_EECD_REQ;
  306. E1000_WRITE_REG(hw, EECD, eecd);
  307. eecd = E1000_READ_REG(hw, EECD);
  308. while ((!(eecd & E1000_EECD_GNT)) &&
  309. (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
  310. i++;
  311. udelay(5);
  312. eecd = E1000_READ_REG(hw, EECD);
  313. }
  314. if (!(eecd & E1000_EECD_GNT)) {
  315. eecd &= ~E1000_EECD_REQ;
  316. E1000_WRITE_REG(hw, EECD, eecd);
  317. DEBUGOUT("Could not acquire EEPROM grant\n");
  318. return -E1000_ERR_EEPROM;
  319. }
  320. }
  321. }
  322. /* Setup EEPROM for Read/Write */
  323. if (eeprom->type == e1000_eeprom_microwire) {
  324. /* Clear SK and DI */
  325. eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
  326. E1000_WRITE_REG(hw, EECD, eecd);
  327. /* Set CS */
  328. eecd |= E1000_EECD_CS;
  329. E1000_WRITE_REG(hw, EECD, eecd);
  330. } else if (eeprom->type == e1000_eeprom_spi) {
  331. /* Clear SK and CS */
  332. eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
  333. E1000_WRITE_REG(hw, EECD, eecd);
  334. udelay(1);
  335. }
  336. return E1000_SUCCESS;
  337. }
  338. /******************************************************************************
  339. * Sets up eeprom variables in the hw struct. Must be called after mac_type
  340. * is configured. Additionally, if this is ICH8, the flash controller GbE
  341. * registers must be mapped, or this will crash.
  342. *
  343. * hw - Struct containing variables accessed by shared code
  344. *****************************************************************************/
  345. static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
  346. {
  347. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  348. uint32_t eecd = E1000_READ_REG(hw, EECD);
  349. int32_t ret_val = E1000_SUCCESS;
  350. uint16_t eeprom_size;
  351. DEBUGFUNC();
  352. switch (hw->mac_type) {
  353. case e1000_82542_rev2_0:
  354. case e1000_82542_rev2_1:
  355. case e1000_82543:
  356. case e1000_82544:
  357. eeprom->type = e1000_eeprom_microwire;
  358. eeprom->word_size = 64;
  359. eeprom->opcode_bits = 3;
  360. eeprom->address_bits = 6;
  361. eeprom->delay_usec = 50;
  362. eeprom->use_eerd = false;
  363. eeprom->use_eewr = false;
  364. break;
  365. case e1000_82540:
  366. case e1000_82545:
  367. case e1000_82545_rev_3:
  368. case e1000_82546:
  369. case e1000_82546_rev_3:
  370. eeprom->type = e1000_eeprom_microwire;
  371. eeprom->opcode_bits = 3;
  372. eeprom->delay_usec = 50;
  373. if (eecd & E1000_EECD_SIZE) {
  374. eeprom->word_size = 256;
  375. eeprom->address_bits = 8;
  376. } else {
  377. eeprom->word_size = 64;
  378. eeprom->address_bits = 6;
  379. }
  380. eeprom->use_eerd = false;
  381. eeprom->use_eewr = false;
  382. break;
  383. case e1000_82541:
  384. case e1000_82541_rev_2:
  385. case e1000_82547:
  386. case e1000_82547_rev_2:
  387. if (eecd & E1000_EECD_TYPE) {
  388. eeprom->type = e1000_eeprom_spi;
  389. eeprom->opcode_bits = 8;
  390. eeprom->delay_usec = 1;
  391. if (eecd & E1000_EECD_ADDR_BITS) {
  392. eeprom->page_size = 32;
  393. eeprom->address_bits = 16;
  394. } else {
  395. eeprom->page_size = 8;
  396. eeprom->address_bits = 8;
  397. }
  398. } else {
  399. eeprom->type = e1000_eeprom_microwire;
  400. eeprom->opcode_bits = 3;
  401. eeprom->delay_usec = 50;
  402. if (eecd & E1000_EECD_ADDR_BITS) {
  403. eeprom->word_size = 256;
  404. eeprom->address_bits = 8;
  405. } else {
  406. eeprom->word_size = 64;
  407. eeprom->address_bits = 6;
  408. }
  409. }
  410. eeprom->use_eerd = false;
  411. eeprom->use_eewr = false;
  412. break;
  413. case e1000_82571:
  414. case e1000_82572:
  415. eeprom->type = e1000_eeprom_spi;
  416. eeprom->opcode_bits = 8;
  417. eeprom->delay_usec = 1;
  418. if (eecd & E1000_EECD_ADDR_BITS) {
  419. eeprom->page_size = 32;
  420. eeprom->address_bits = 16;
  421. } else {
  422. eeprom->page_size = 8;
  423. eeprom->address_bits = 8;
  424. }
  425. eeprom->use_eerd = false;
  426. eeprom->use_eewr = false;
  427. break;
  428. case e1000_82573:
  429. case e1000_82574:
  430. eeprom->type = e1000_eeprom_spi;
  431. eeprom->opcode_bits = 8;
  432. eeprom->delay_usec = 1;
  433. if (eecd & E1000_EECD_ADDR_BITS) {
  434. eeprom->page_size = 32;
  435. eeprom->address_bits = 16;
  436. } else {
  437. eeprom->page_size = 8;
  438. eeprom->address_bits = 8;
  439. }
  440. eeprom->use_eerd = true;
  441. eeprom->use_eewr = true;
  442. if (e1000_is_onboard_nvm_eeprom(hw) == false) {
  443. eeprom->type = e1000_eeprom_flash;
  444. eeprom->word_size = 2048;
  445. /* Ensure that the Autonomous FLASH update bit is cleared due to
  446. * Flash update issue on parts which use a FLASH for NVM. */
  447. eecd &= ~E1000_EECD_AUPDEN;
  448. E1000_WRITE_REG(hw, EECD, eecd);
  449. }
  450. break;
  451. case e1000_80003es2lan:
  452. eeprom->type = e1000_eeprom_spi;
  453. eeprom->opcode_bits = 8;
  454. eeprom->delay_usec = 1;
  455. if (eecd & E1000_EECD_ADDR_BITS) {
  456. eeprom->page_size = 32;
  457. eeprom->address_bits = 16;
  458. } else {
  459. eeprom->page_size = 8;
  460. eeprom->address_bits = 8;
  461. }
  462. eeprom->use_eerd = true;
  463. eeprom->use_eewr = false;
  464. break;
  465. /* ich8lan does not support currently. if needed, please
  466. * add corresponding code and functions.
  467. */
  468. #if 0
  469. case e1000_ich8lan:
  470. {
  471. int32_t i = 0;
  472. eeprom->type = e1000_eeprom_ich8;
  473. eeprom->use_eerd = false;
  474. eeprom->use_eewr = false;
  475. eeprom->word_size = E1000_SHADOW_RAM_WORDS;
  476. uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
  477. ICH_FLASH_GFPREG);
  478. /* Zero the shadow RAM structure. But don't load it from NVM
  479. * so as to save time for driver init */
  480. if (hw->eeprom_shadow_ram != NULL) {
  481. for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
  482. hw->eeprom_shadow_ram[i].modified = false;
  483. hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
  484. }
  485. }
  486. hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
  487. ICH_FLASH_SECTOR_SIZE;
  488. hw->flash_bank_size = ((flash_size >> 16)
  489. & ICH_GFPREG_BASE_MASK) + 1;
  490. hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
  491. hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
  492. hw->flash_bank_size /= 2 * sizeof(uint16_t);
  493. break;
  494. }
  495. #endif
  496. default:
  497. break;
  498. }
  499. if (eeprom->type == e1000_eeprom_spi) {
  500. /* eeprom_size will be an enum [0..8] that maps
  501. * to eeprom sizes 128B to
  502. * 32KB (incremented by powers of 2).
  503. */
  504. if (hw->mac_type <= e1000_82547_rev_2) {
  505. /* Set to default value for initial eeprom read. */
  506. eeprom->word_size = 64;
  507. ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
  508. &eeprom_size);
  509. if (ret_val)
  510. return ret_val;
  511. eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
  512. >> EEPROM_SIZE_SHIFT;
  513. /* 256B eeprom size was not supported in earlier
  514. * hardware, so we bump eeprom_size up one to
  515. * ensure that "1" (which maps to 256B) is never
  516. * the result used in the shifting logic below. */
  517. if (eeprom_size)
  518. eeprom_size++;
  519. } else {
  520. eeprom_size = (uint16_t)((eecd &
  521. E1000_EECD_SIZE_EX_MASK) >>
  522. E1000_EECD_SIZE_EX_SHIFT);
  523. }
  524. eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
  525. }
  526. return ret_val;
  527. }
  528. /******************************************************************************
  529. * Polls the status bit (bit 1) of the EERD to determine when the read is done.
  530. *
  531. * hw - Struct containing variables accessed by shared code
  532. *****************************************************************************/
  533. static int32_t
  534. e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
  535. {
  536. uint32_t attempts = 100000;
  537. uint32_t i, reg = 0;
  538. int32_t done = E1000_ERR_EEPROM;
  539. for (i = 0; i < attempts; i++) {
  540. if (eerd == E1000_EEPROM_POLL_READ)
  541. reg = E1000_READ_REG(hw, EERD);
  542. else
  543. reg = E1000_READ_REG(hw, EEWR);
  544. if (reg & E1000_EEPROM_RW_REG_DONE) {
  545. done = E1000_SUCCESS;
  546. break;
  547. }
  548. udelay(5);
  549. }
  550. return done;
  551. }
  552. /******************************************************************************
  553. * Reads a 16 bit word from the EEPROM using the EERD register.
  554. *
  555. * hw - Struct containing variables accessed by shared code
  556. * offset - offset of word in the EEPROM to read
  557. * data - word read from the EEPROM
  558. * words - number of words to read
  559. *****************************************************************************/
  560. static int32_t
  561. e1000_read_eeprom_eerd(struct e1000_hw *hw,
  562. uint16_t offset,
  563. uint16_t words,
  564. uint16_t *data)
  565. {
  566. uint32_t i, eerd = 0;
  567. int32_t error = 0;
  568. for (i = 0; i < words; i++) {
  569. eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
  570. E1000_EEPROM_RW_REG_START;
  571. E1000_WRITE_REG(hw, EERD, eerd);
  572. error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
  573. if (error)
  574. break;
  575. data[i] = (E1000_READ_REG(hw, EERD) >>
  576. E1000_EEPROM_RW_REG_DATA);
  577. }
  578. return error;
  579. }
  580. void e1000_release_eeprom(struct e1000_hw *hw)
  581. {
  582. uint32_t eecd;
  583. DEBUGFUNC();
  584. eecd = E1000_READ_REG(hw, EECD);
  585. if (hw->eeprom.type == e1000_eeprom_spi) {
  586. eecd |= E1000_EECD_CS; /* Pull CS high */
  587. eecd &= ~E1000_EECD_SK; /* Lower SCK */
  588. E1000_WRITE_REG(hw, EECD, eecd);
  589. udelay(hw->eeprom.delay_usec);
  590. } else if (hw->eeprom.type == e1000_eeprom_microwire) {
  591. /* cleanup eeprom */
  592. /* CS on Microwire is active-high */
  593. eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
  594. E1000_WRITE_REG(hw, EECD, eecd);
  595. /* Rising edge of clock */
  596. eecd |= E1000_EECD_SK;
  597. E1000_WRITE_REG(hw, EECD, eecd);
  598. E1000_WRITE_FLUSH(hw);
  599. udelay(hw->eeprom.delay_usec);
  600. /* Falling edge of clock */
  601. eecd &= ~E1000_EECD_SK;
  602. E1000_WRITE_REG(hw, EECD, eecd);
  603. E1000_WRITE_FLUSH(hw);
  604. udelay(hw->eeprom.delay_usec);
  605. }
  606. /* Stop requesting EEPROM access */
  607. if (hw->mac_type > e1000_82544) {
  608. eecd &= ~E1000_EECD_REQ;
  609. E1000_WRITE_REG(hw, EECD, eecd);
  610. }
  611. }
  612. /******************************************************************************
  613. * Reads a 16 bit word from the EEPROM.
  614. *
  615. * hw - Struct containing variables accessed by shared code
  616. *****************************************************************************/
  617. static int32_t
  618. e1000_spi_eeprom_ready(struct e1000_hw *hw)
  619. {
  620. uint16_t retry_count = 0;
  621. uint8_t spi_stat_reg;
  622. DEBUGFUNC();
  623. /* Read "Status Register" repeatedly until the LSB is cleared. The
  624. * EEPROM will signal that the command has been completed by clearing
  625. * bit 0 of the internal status register. If it's not cleared within
  626. * 5 milliseconds, then error out.
  627. */
  628. retry_count = 0;
  629. do {
  630. e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
  631. hw->eeprom.opcode_bits);
  632. spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
  633. if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
  634. break;
  635. udelay(5);
  636. retry_count += 5;
  637. e1000_standby_eeprom(hw);
  638. } while (retry_count < EEPROM_MAX_RETRY_SPI);
  639. /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
  640. * only 0-5mSec on 5V devices)
  641. */
  642. if (retry_count >= EEPROM_MAX_RETRY_SPI) {
  643. DEBUGOUT("SPI EEPROM Status error\n");
  644. return -E1000_ERR_EEPROM;
  645. }
  646. return E1000_SUCCESS;
  647. }
  648. /******************************************************************************
  649. * Reads a 16 bit word from the EEPROM.
  650. *
  651. * hw - Struct containing variables accessed by shared code
  652. * offset - offset of word in the EEPROM to read
  653. * data - word read from the EEPROM
  654. *****************************************************************************/
  655. static int32_t
  656. e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
  657. uint16_t words, uint16_t *data)
  658. {
  659. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  660. uint32_t i = 0;
  661. DEBUGFUNC();
  662. /* If eeprom is not yet detected, do so now */
  663. if (eeprom->word_size == 0)
  664. e1000_init_eeprom_params(hw);
  665. /* A check for invalid values: offset too large, too many words,
  666. * and not enough words.
  667. */
  668. if ((offset >= eeprom->word_size) ||
  669. (words > eeprom->word_size - offset) ||
  670. (words == 0)) {
  671. DEBUGOUT("\"words\" parameter out of bounds."
  672. "Words = %d, size = %d\n", offset, eeprom->word_size);
  673. return -E1000_ERR_EEPROM;
  674. }
  675. /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
  676. * directly. In this case, we need to acquire the EEPROM so that
  677. * FW or other port software does not interrupt.
  678. */
  679. if (e1000_is_onboard_nvm_eeprom(hw) == true &&
  680. hw->eeprom.use_eerd == false) {
  681. /* Prepare the EEPROM for bit-bang reading */
  682. if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
  683. return -E1000_ERR_EEPROM;
  684. }
  685. /* Eerd register EEPROM access requires no eeprom aquire/release */
  686. if (eeprom->use_eerd == true)
  687. return e1000_read_eeprom_eerd(hw, offset, words, data);
  688. /* ich8lan does not support currently. if needed, please
  689. * add corresponding code and functions.
  690. */
  691. #if 0
  692. /* ICH EEPROM access is done via the ICH flash controller */
  693. if (eeprom->type == e1000_eeprom_ich8)
  694. return e1000_read_eeprom_ich8(hw, offset, words, data);
  695. #endif
  696. /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
  697. * acquired the EEPROM at this point, so any returns should relase it */
  698. if (eeprom->type == e1000_eeprom_spi) {
  699. uint16_t word_in;
  700. uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
  701. if (e1000_spi_eeprom_ready(hw)) {
  702. e1000_release_eeprom(hw);
  703. return -E1000_ERR_EEPROM;
  704. }
  705. e1000_standby_eeprom(hw);
  706. /* Some SPI eeproms use the 8th address bit embedded in
  707. * the opcode */
  708. if ((eeprom->address_bits == 8) && (offset >= 128))
  709. read_opcode |= EEPROM_A8_OPCODE_SPI;
  710. /* Send the READ command (opcode + addr) */
  711. e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
  712. e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
  713. eeprom->address_bits);
  714. /* Read the data. The address of the eeprom internally
  715. * increments with each byte (spi) being read, saving on the
  716. * overhead of eeprom setup and tear-down. The address
  717. * counter will roll over if reading beyond the size of
  718. * the eeprom, thus allowing the entire memory to be read
  719. * starting from any offset. */
  720. for (i = 0; i < words; i++) {
  721. word_in = e1000_shift_in_ee_bits(hw, 16);
  722. data[i] = (word_in >> 8) | (word_in << 8);
  723. }
  724. } else if (eeprom->type == e1000_eeprom_microwire) {
  725. for (i = 0; i < words; i++) {
  726. /* Send the READ command (opcode + addr) */
  727. e1000_shift_out_ee_bits(hw,
  728. EEPROM_READ_OPCODE_MICROWIRE,
  729. eeprom->opcode_bits);
  730. e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
  731. eeprom->address_bits);
  732. /* Read the data. For microwire, each word requires
  733. * the overhead of eeprom setup and tear-down. */
  734. data[i] = e1000_shift_in_ee_bits(hw, 16);
  735. e1000_standby_eeprom(hw);
  736. }
  737. }
  738. /* End this read operation */
  739. e1000_release_eeprom(hw);
  740. return E1000_SUCCESS;
  741. }
  742. /******************************************************************************
  743. * Verifies that the EEPROM has a valid checksum
  744. *
  745. * hw - Struct containing variables accessed by shared code
  746. *
  747. * Reads the first 64 16 bit words of the EEPROM and sums the values read.
  748. * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
  749. * valid.
  750. *****************************************************************************/
  751. static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
  752. {
  753. uint16_t i, checksum, checksum_reg, *buf;
  754. DEBUGFUNC();
  755. /* Allocate a temporary buffer */
  756. buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
  757. if (!buf) {
  758. E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n");
  759. return -E1000_ERR_EEPROM;
  760. }
  761. /* Read the EEPROM */
  762. if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
  763. E1000_ERR(hw->nic, "Unable to read EEPROM!\n");
  764. return -E1000_ERR_EEPROM;
  765. }
  766. /* Compute the checksum */
  767. checksum = 0;
  768. for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
  769. checksum += buf[i];
  770. checksum = ((uint16_t)EEPROM_SUM) - checksum;
  771. checksum_reg = buf[i];
  772. /* Verify it! */
  773. if (checksum == checksum_reg)
  774. return 0;
  775. /* Hrm, verification failed, print an error */
  776. E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n");
  777. E1000_ERR(hw->nic, " ...register was 0x%04hx, calculated 0x%04hx\n",
  778. checksum_reg, checksum);
  779. return -E1000_ERR_EEPROM;
  780. }
  781. /*****************************************************************************
  782. * Set PHY to class A mode
  783. * Assumes the following operations will follow to enable the new class mode.
  784. * 1. Do a PHY soft reset
  785. * 2. Restart auto-negotiation or force link.
  786. *
  787. * hw - Struct containing variables accessed by shared code
  788. ****************************************************************************/
  789. static int32_t
  790. e1000_set_phy_mode(struct e1000_hw *hw)
  791. {
  792. int32_t ret_val;
  793. uint16_t eeprom_data;
  794. DEBUGFUNC();
  795. if ((hw->mac_type == e1000_82545_rev_3) &&
  796. (hw->media_type == e1000_media_type_copper)) {
  797. ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
  798. 1, &eeprom_data);
  799. if (ret_val)
  800. return ret_val;
  801. if ((eeprom_data != EEPROM_RESERVED_WORD) &&
  802. (eeprom_data & EEPROM_PHY_CLASS_A)) {
  803. ret_val = e1000_write_phy_reg(hw,
  804. M88E1000_PHY_PAGE_SELECT, 0x000B);
  805. if (ret_val)
  806. return ret_val;
  807. ret_val = e1000_write_phy_reg(hw,
  808. M88E1000_PHY_GEN_CONTROL, 0x8104);
  809. if (ret_val)
  810. return ret_val;
  811. hw->phy_reset_disable = false;
  812. }
  813. }
  814. return E1000_SUCCESS;
  815. }
  816. /***************************************************************************
  817. *
  818. * Obtaining software semaphore bit (SMBI) before resetting PHY.
  819. *
  820. * hw: Struct containing variables accessed by shared code
  821. *
  822. * returns: - E1000_ERR_RESET if fail to obtain semaphore.
  823. * E1000_SUCCESS at any other case.
  824. *
  825. ***************************************************************************/
  826. static int32_t
  827. e1000_get_software_semaphore(struct e1000_hw *hw)
  828. {
  829. int32_t timeout = hw->eeprom.word_size + 1;
  830. uint32_t swsm;
  831. DEBUGFUNC();
  832. if (hw->mac_type != e1000_80003es2lan)
  833. return E1000_SUCCESS;
  834. while (timeout) {
  835. swsm = E1000_READ_REG(hw, SWSM);
  836. /* If SMBI bit cleared, it is now set and we hold
  837. * the semaphore */
  838. if (!(swsm & E1000_SWSM_SMBI))
  839. break;
  840. mdelay(1);
  841. timeout--;
  842. }
  843. if (!timeout) {
  844. DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
  845. return -E1000_ERR_RESET;
  846. }
  847. return E1000_SUCCESS;
  848. }
  849. /***************************************************************************
  850. * This function clears HW semaphore bits.
  851. *
  852. * hw: Struct containing variables accessed by shared code
  853. *
  854. * returns: - None.
  855. *
  856. ***************************************************************************/
  857. static void
  858. e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
  859. {
  860. uint32_t swsm;
  861. DEBUGFUNC();
  862. if (!hw->eeprom_semaphore_present)
  863. return;
  864. swsm = E1000_READ_REG(hw, SWSM);
  865. if (hw->mac_type == e1000_80003es2lan) {
  866. /* Release both semaphores. */
  867. swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
  868. } else
  869. swsm &= ~(E1000_SWSM_SWESMBI);
  870. E1000_WRITE_REG(hw, SWSM, swsm);
  871. }
  872. /***************************************************************************
  873. *
  874. * Using the combination of SMBI and SWESMBI semaphore bits when resetting
  875. * adapter or Eeprom access.
  876. *
  877. * hw: Struct containing variables accessed by shared code
  878. *
  879. * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
  880. * E1000_SUCCESS at any other case.
  881. *
  882. ***************************************************************************/
  883. static int32_t
  884. e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
  885. {
  886. int32_t timeout;
  887. uint32_t swsm;
  888. DEBUGFUNC();
  889. if (!hw->eeprom_semaphore_present)
  890. return E1000_SUCCESS;
  891. if (hw->mac_type == e1000_80003es2lan) {
  892. /* Get the SW semaphore. */
  893. if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
  894. return -E1000_ERR_EEPROM;
  895. }
  896. /* Get the FW semaphore. */
  897. timeout = hw->eeprom.word_size + 1;
  898. while (timeout) {
  899. swsm = E1000_READ_REG(hw, SWSM);
  900. swsm |= E1000_SWSM_SWESMBI;
  901. E1000_WRITE_REG(hw, SWSM, swsm);
  902. /* if we managed to set the bit we got the semaphore. */
  903. swsm = E1000_READ_REG(hw, SWSM);
  904. if (swsm & E1000_SWSM_SWESMBI)
  905. break;
  906. udelay(50);
  907. timeout--;
  908. }
  909. if (!timeout) {
  910. /* Release semaphores */
  911. e1000_put_hw_eeprom_semaphore(hw);
  912. DEBUGOUT("Driver can't access the Eeprom - "
  913. "SWESMBI bit is set.\n");
  914. return -E1000_ERR_EEPROM;
  915. }
  916. return E1000_SUCCESS;
  917. }
  918. static int32_t
  919. e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
  920. {
  921. uint32_t swfw_sync = 0;
  922. uint32_t swmask = mask;
  923. uint32_t fwmask = mask << 16;
  924. int32_t timeout = 200;
  925. DEBUGFUNC();
  926. while (timeout) {
  927. if (e1000_get_hw_eeprom_semaphore(hw))
  928. return -E1000_ERR_SWFW_SYNC;
  929. swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
  930. if (!(swfw_sync & (fwmask | swmask)))
  931. break;
  932. /* firmware currently using resource (fwmask) */
  933. /* or other software thread currently using resource (swmask) */
  934. e1000_put_hw_eeprom_semaphore(hw);
  935. mdelay(5);
  936. timeout--;
  937. }
  938. if (!timeout) {
  939. DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
  940. return -E1000_ERR_SWFW_SYNC;
  941. }
  942. swfw_sync |= swmask;
  943. E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
  944. e1000_put_hw_eeprom_semaphore(hw);
  945. return E1000_SUCCESS;
  946. }
  947. static bool e1000_is_second_port(struct e1000_hw *hw)
  948. {
  949. switch (hw->mac_type) {
  950. case e1000_80003es2lan:
  951. case e1000_82546:
  952. case e1000_82571:
  953. if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
  954. return true;
  955. /* Fallthrough */
  956. default:
  957. return false;
  958. }
  959. }
  960. /******************************************************************************
  961. * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
  962. * second function of dual function devices
  963. *
  964. * nic - Struct containing variables accessed by shared code
  965. *****************************************************************************/
  966. static int
  967. e1000_read_mac_addr(struct eth_device *nic)
  968. {
  969. struct e1000_hw *hw = nic->priv;
  970. uint16_t offset;
  971. uint16_t eeprom_data;
  972. int i;
  973. DEBUGFUNC();
  974. for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
  975. offset = i >> 1;
  976. if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
  977. DEBUGOUT("EEPROM Read Error\n");
  978. return -E1000_ERR_EEPROM;
  979. }
  980. nic->enetaddr[i] = eeprom_data & 0xff;
  981. nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
  982. }
  983. /* Invert the last bit if this is the second device */
  984. if (e1000_is_second_port(hw))
  985. nic->enetaddr[5] ^= 1;
  986. #ifdef CONFIG_E1000_FALLBACK_MAC
  987. if (!is_valid_ether_addr(nic->enetaddr)) {
  988. unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
  989. memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
  990. }
  991. #endif
  992. return 0;
  993. }
  994. /******************************************************************************
  995. * Initializes receive address filters.
  996. *
  997. * hw - Struct containing variables accessed by shared code
  998. *
  999. * Places the MAC address in receive address register 0 and clears the rest
  1000. * of the receive addresss registers. Clears the multicast table. Assumes
  1001. * the receiver is in reset when the routine is called.
  1002. *****************************************************************************/
  1003. static void
  1004. e1000_init_rx_addrs(struct eth_device *nic)
  1005. {
  1006. struct e1000_hw *hw = nic->priv;
  1007. uint32_t i;
  1008. uint32_t addr_low;
  1009. uint32_t addr_high;
  1010. DEBUGFUNC();
  1011. /* Setup the receive address. */
  1012. DEBUGOUT("Programming MAC Address into RAR[0]\n");
  1013. addr_low = (nic->enetaddr[0] |
  1014. (nic->enetaddr[1] << 8) |
  1015. (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24));
  1016. addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV);
  1017. E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
  1018. E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
  1019. /* Zero out the other 15 receive addresses. */
  1020. DEBUGOUT("Clearing RAR[1-15]\n");
  1021. for (i = 1; i < E1000_RAR_ENTRIES; i++) {
  1022. E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
  1023. E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
  1024. }
  1025. }
  1026. /******************************************************************************
  1027. * Clears the VLAN filer table
  1028. *
  1029. * hw - Struct containing variables accessed by shared code
  1030. *****************************************************************************/
  1031. static void
  1032. e1000_clear_vfta(struct e1000_hw *hw)
  1033. {
  1034. uint32_t offset;
  1035. for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
  1036. E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
  1037. }
  1038. /******************************************************************************
  1039. * Set the mac type member in the hw struct.
  1040. *
  1041. * hw - Struct containing variables accessed by shared code
  1042. *****************************************************************************/
  1043. int32_t
  1044. e1000_set_mac_type(struct e1000_hw *hw)
  1045. {
  1046. DEBUGFUNC();
  1047. switch (hw->device_id) {
  1048. case E1000_DEV_ID_82542:
  1049. switch (hw->revision_id) {
  1050. case E1000_82542_2_0_REV_ID:
  1051. hw->mac_type = e1000_82542_rev2_0;
  1052. break;
  1053. case E1000_82542_2_1_REV_ID:
  1054. hw->mac_type = e1000_82542_rev2_1;
  1055. break;
  1056. default:
  1057. /* Invalid 82542 revision ID */
  1058. return -E1000_ERR_MAC_TYPE;
  1059. }
  1060. break;
  1061. case E1000_DEV_ID_82543GC_FIBER:
  1062. case E1000_DEV_ID_82543GC_COPPER:
  1063. hw->mac_type = e1000_82543;
  1064. break;
  1065. case E1000_DEV_ID_82544EI_COPPER:
  1066. case E1000_DEV_ID_82544EI_FIBER:
  1067. case E1000_DEV_ID_82544GC_COPPER:
  1068. case E1000_DEV_ID_82544GC_LOM:
  1069. hw->mac_type = e1000_82544;
  1070. break;
  1071. case E1000_DEV_ID_82540EM:
  1072. case E1000_DEV_ID_82540EM_LOM:
  1073. case E1000_DEV_ID_82540EP:
  1074. case E1000_DEV_ID_82540EP_LOM:
  1075. case E1000_DEV_ID_82540EP_LP:
  1076. hw->mac_type = e1000_82540;
  1077. break;
  1078. case E1000_DEV_ID_82545EM_COPPER:
  1079. case E1000_DEV_ID_82545EM_FIBER:
  1080. hw->mac_type = e1000_82545;
  1081. break;
  1082. case E1000_DEV_ID_82545GM_COPPER:
  1083. case E1000_DEV_ID_82545GM_FIBER:
  1084. case E1000_DEV_ID_82545GM_SERDES:
  1085. hw->mac_type = e1000_82545_rev_3;
  1086. break;
  1087. case E1000_DEV_ID_82546EB_COPPER:
  1088. case E1000_DEV_ID_82546EB_FIBER:
  1089. case E1000_DEV_ID_82546EB_QUAD_COPPER:
  1090. hw->mac_type = e1000_82546;
  1091. break;
  1092. case E1000_DEV_ID_82546GB_COPPER:
  1093. case E1000_DEV_ID_82546GB_FIBER:
  1094. case E1000_DEV_ID_82546GB_SERDES:
  1095. case E1000_DEV_ID_82546GB_PCIE:
  1096. case E1000_DEV_ID_82546GB_QUAD_COPPER:
  1097. case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
  1098. hw->mac_type = e1000_82546_rev_3;
  1099. break;
  1100. case E1000_DEV_ID_82541EI:
  1101. case E1000_DEV_ID_82541EI_MOBILE:
  1102. case E1000_DEV_ID_82541ER_LOM:
  1103. hw->mac_type = e1000_82541;
  1104. break;
  1105. case E1000_DEV_ID_82541ER:
  1106. case E1000_DEV_ID_82541GI:
  1107. case E1000_DEV_ID_82541GI_LF:
  1108. case E1000_DEV_ID_82541GI_MOBILE:
  1109. hw->mac_type = e1000_82541_rev_2;
  1110. break;
  1111. case E1000_DEV_ID_82547EI:
  1112. case E1000_DEV_ID_82547EI_MOBILE:
  1113. hw->mac_type = e1000_82547;
  1114. break;
  1115. case E1000_DEV_ID_82547GI:
  1116. hw->mac_type = e1000_82547_rev_2;
  1117. break;
  1118. case E1000_DEV_ID_82571EB_COPPER:
  1119. case E1000_DEV_ID_82571EB_FIBER:
  1120. case E1000_DEV_ID_82571EB_SERDES:
  1121. case E1000_DEV_ID_82571EB_SERDES_DUAL:
  1122. case E1000_DEV_ID_82571EB_SERDES_QUAD:
  1123. case E1000_DEV_ID_82571EB_QUAD_COPPER:
  1124. case E1000_DEV_ID_82571PT_QUAD_COPPER:
  1125. case E1000_DEV_ID_82571EB_QUAD_FIBER:
  1126. case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
  1127. hw->mac_type = e1000_82571;
  1128. break;
  1129. case E1000_DEV_ID_82572EI_COPPER:
  1130. case E1000_DEV_ID_82572EI_FIBER:
  1131. case E1000_DEV_ID_82572EI_SERDES:
  1132. case E1000_DEV_ID_82572EI:
  1133. hw->mac_type = e1000_82572;
  1134. break;
  1135. case E1000_DEV_ID_82573E:
  1136. case E1000_DEV_ID_82573E_IAMT:
  1137. case E1000_DEV_ID_82573L:
  1138. hw->mac_type = e1000_82573;
  1139. break;
  1140. case E1000_DEV_ID_82574L:
  1141. hw->mac_type = e1000_82574;
  1142. break;
  1143. case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
  1144. case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
  1145. case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
  1146. case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
  1147. hw->mac_type = e1000_80003es2lan;
  1148. break;
  1149. case E1000_DEV_ID_ICH8_IGP_M_AMT:
  1150. case E1000_DEV_ID_ICH8_IGP_AMT:
  1151. case E1000_DEV_ID_ICH8_IGP_C:
  1152. case E1000_DEV_ID_ICH8_IFE:
  1153. case E1000_DEV_ID_ICH8_IFE_GT:
  1154. case E1000_DEV_ID_ICH8_IFE_G:
  1155. case E1000_DEV_ID_ICH8_IGP_M:
  1156. hw->mac_type = e1000_ich8lan;
  1157. break;
  1158. default:
  1159. /* Should never have loaded on this device */
  1160. return -E1000_ERR_MAC_TYPE;
  1161. }
  1162. return E1000_SUCCESS;
  1163. }
  1164. /******************************************************************************
  1165. * Reset the transmit and receive units; mask and clear all interrupts.
  1166. *
  1167. * hw - Struct containing variables accessed by shared code
  1168. *****************************************************************************/
  1169. void
  1170. e1000_reset_hw(struct e1000_hw *hw)
  1171. {
  1172. uint32_t ctrl;
  1173. uint32_t ctrl_ext;
  1174. uint32_t manc;
  1175. uint32_t pba = 0;
  1176. DEBUGFUNC();
  1177. /* get the correct pba value for both PCI and PCIe*/
  1178. if (hw->mac_type < e1000_82571)
  1179. pba = E1000_DEFAULT_PCI_PBA;
  1180. else
  1181. pba = E1000_DEFAULT_PCIE_PBA;
  1182. /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
  1183. if (hw->mac_type == e1000_82542_rev2_0) {
  1184. DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
  1185. pci_write_config_word(hw->pdev, PCI_COMMAND,
  1186. hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
  1187. }
  1188. /* Clear interrupt mask to stop board from generating interrupts */
  1189. DEBUGOUT("Masking off all interrupts\n");
  1190. E1000_WRITE_REG(hw, IMC, 0xffffffff);
  1191. /* Disable the Transmit and Receive units. Then delay to allow
  1192. * any pending transactions to complete before we hit the MAC with
  1193. * the global reset.
  1194. */
  1195. E1000_WRITE_REG(hw, RCTL, 0);
  1196. E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
  1197. E1000_WRITE_FLUSH(hw);
  1198. /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
  1199. hw->tbi_compatibility_on = false;
  1200. /* Delay to allow any outstanding PCI transactions to complete before
  1201. * resetting the device
  1202. */
  1203. mdelay(10);
  1204. /* Issue a global reset to the MAC. This will reset the chip's
  1205. * transmit, receive, DMA, and link units. It will not effect
  1206. * the current PCI configuration. The global reset bit is self-
  1207. * clearing, and should clear within a microsecond.
  1208. */
  1209. DEBUGOUT("Issuing a global reset to MAC\n");
  1210. ctrl = E1000_READ_REG(hw, CTRL);
  1211. E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
  1212. /* Force a reload from the EEPROM if necessary */
  1213. if (hw->mac_type < e1000_82540) {
  1214. /* Wait for reset to complete */
  1215. udelay(10);
  1216. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1217. ctrl_ext |= E1000_CTRL_EXT_EE_RST;
  1218. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  1219. E1000_WRITE_FLUSH(hw);
  1220. /* Wait for EEPROM reload */
  1221. mdelay(2);
  1222. } else {
  1223. /* Wait for EEPROM reload (it happens automatically) */
  1224. mdelay(4);
  1225. /* Dissable HW ARPs on ASF enabled adapters */
  1226. manc = E1000_READ_REG(hw, MANC);
  1227. manc &= ~(E1000_MANC_ARP_EN);
  1228. E1000_WRITE_REG(hw, MANC, manc);
  1229. }
  1230. /* Clear interrupt mask to stop board from generating interrupts */
  1231. DEBUGOUT("Masking off all interrupts\n");
  1232. E1000_WRITE_REG(hw, IMC, 0xffffffff);
  1233. /* Clear any pending interrupt events. */
  1234. E1000_READ_REG(hw, ICR);
  1235. /* If MWI was previously enabled, reenable it. */
  1236. if (hw->mac_type == e1000_82542_rev2_0) {
  1237. pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
  1238. }
  1239. E1000_WRITE_REG(hw, PBA, pba);
  1240. }
  1241. /******************************************************************************
  1242. *
  1243. * Initialize a number of hardware-dependent bits
  1244. *
  1245. * hw: Struct containing variables accessed by shared code
  1246. *
  1247. * This function contains hardware limitation workarounds for PCI-E adapters
  1248. *
  1249. *****************************************************************************/
  1250. static void
  1251. e1000_initialize_hardware_bits(struct e1000_hw *hw)
  1252. {
  1253. if ((hw->mac_type >= e1000_82571) &&
  1254. (!hw->initialize_hw_bits_disable)) {
  1255. /* Settings common to all PCI-express silicon */
  1256. uint32_t reg_ctrl, reg_ctrl_ext;
  1257. uint32_t reg_tarc0, reg_tarc1;
  1258. uint32_t reg_tctl;
  1259. uint32_t reg_txdctl, reg_txdctl1;
  1260. /* link autonegotiation/sync workarounds */
  1261. reg_tarc0 = E1000_READ_REG(hw, TARC0);
  1262. reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
  1263. /* Enable not-done TX descriptor counting */
  1264. reg_txdctl = E1000_READ_REG(hw, TXDCTL);
  1265. reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
  1266. E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
  1267. reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
  1268. reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
  1269. E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
  1270. switch (hw->mac_type) {
  1271. case e1000_82571:
  1272. case e1000_82572:
  1273. /* Clear PHY TX compatible mode bits */
  1274. reg_tarc1 = E1000_READ_REG(hw, TARC1);
  1275. reg_tarc1 &= ~((1 << 30)|(1 << 29));
  1276. /* link autonegotiation/sync workarounds */
  1277. reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
  1278. /* TX ring control fixes */
  1279. reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
  1280. /* Multiple read bit is reversed polarity */
  1281. reg_tctl = E1000_READ_REG(hw, TCTL);
  1282. if (reg_tctl & E1000_TCTL_MULR)
  1283. reg_tarc1 &= ~(1 << 28);
  1284. else
  1285. reg_tarc1 |= (1 << 28);
  1286. E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  1287. break;
  1288. case e1000_82573:
  1289. case e1000_82574:
  1290. reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1291. reg_ctrl_ext &= ~(1 << 23);
  1292. reg_ctrl_ext |= (1 << 22);
  1293. /* TX byte count fix */
  1294. reg_ctrl = E1000_READ_REG(hw, CTRL);
  1295. reg_ctrl &= ~(1 << 29);
  1296. E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
  1297. E1000_WRITE_REG(hw, CTRL, reg_ctrl);
  1298. break;
  1299. case e1000_80003es2lan:
  1300. /* improve small packet performace for fiber/serdes */
  1301. if ((hw->media_type == e1000_media_type_fiber)
  1302. || (hw->media_type ==
  1303. e1000_media_type_internal_serdes)) {
  1304. reg_tarc0 &= ~(1 << 20);
  1305. }
  1306. /* Multiple read bit is reversed polarity */
  1307. reg_tctl = E1000_READ_REG(hw, TCTL);
  1308. reg_tarc1 = E1000_READ_REG(hw, TARC1);
  1309. if (reg_tctl & E1000_TCTL_MULR)
  1310. reg_tarc1 &= ~(1 << 28);
  1311. else
  1312. reg_tarc1 |= (1 << 28);
  1313. E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  1314. break;
  1315. case e1000_ich8lan:
  1316. /* Reduce concurrent DMA requests to 3 from 4 */
  1317. if ((hw->revision_id < 3) ||
  1318. ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
  1319. (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
  1320. reg_tarc0 |= ((1 << 29)|(1 << 28));
  1321. reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1322. reg_ctrl_ext |= (1 << 22);
  1323. E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
  1324. /* workaround TX hang with TSO=on */
  1325. reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
  1326. /* Multiple read bit is reversed polarity */
  1327. reg_tctl = E1000_READ_REG(hw, TCTL);
  1328. reg_tarc1 = E1000_READ_REG(hw, TARC1);
  1329. if (reg_tctl & E1000_TCTL_MULR)
  1330. reg_tarc1 &= ~(1 << 28);
  1331. else
  1332. reg_tarc1 |= (1 << 28);
  1333. /* workaround TX hang with TSO=on */
  1334. reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
  1335. E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  1336. break;
  1337. default:
  1338. break;
  1339. }
  1340. E1000_WRITE_REG(hw, TARC0, reg_tarc0);
  1341. }
  1342. }
  1343. /******************************************************************************
  1344. * Performs basic configuration of the adapter.
  1345. *
  1346. * hw - Struct containing variables accessed by shared code
  1347. *
  1348. * Assumes that the controller has previously been reset and is in a
  1349. * post-reset uninitialized state. Initializes the receive address registers,
  1350. * multicast table, and VLAN filter table. Calls routines to setup link
  1351. * configuration and flow control settings. Clears all on-chip counters. Leaves
  1352. * the transmit and receive units disabled and uninitialized.
  1353. *****************************************************************************/
  1354. static int
  1355. e1000_init_hw(struct eth_device *nic)
  1356. {
  1357. struct e1000_hw *hw = nic->priv;
  1358. uint32_t ctrl;
  1359. uint32_t i;
  1360. int32_t ret_val;
  1361. uint16_t pcix_cmd_word;
  1362. uint16_t pcix_stat_hi_word;
  1363. uint16_t cmd_mmrbc;
  1364. uint16_t stat_mmrbc;
  1365. uint32_t mta_size;
  1366. uint32_t reg_data;
  1367. uint32_t ctrl_ext;
  1368. DEBUGFUNC();
  1369. /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
  1370. if ((hw->mac_type == e1000_ich8lan) &&
  1371. ((hw->revision_id < 3) ||
  1372. ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
  1373. (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
  1374. reg_data = E1000_READ_REG(hw, STATUS);
  1375. reg_data &= ~0x80000000;
  1376. E1000_WRITE_REG(hw, STATUS, reg_data);
  1377. }
  1378. /* Do not need initialize Identification LED */
  1379. /* Set the media type and TBI compatibility */
  1380. e1000_set_media_type(hw);
  1381. /* Must be called after e1000_set_media_type
  1382. * because media_type is used */
  1383. e1000_initialize_hardware_bits(hw);
  1384. /* Disabling VLAN filtering. */
  1385. DEBUGOUT("Initializing the IEEE VLAN\n");
  1386. /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
  1387. if (hw->mac_type != e1000_ich8lan) {
  1388. if (hw->mac_type < e1000_82545_rev_3)
  1389. E1000_WRITE_REG(hw, VET, 0);
  1390. e1000_clear_vfta(hw);
  1391. }
  1392. /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
  1393. if (hw->mac_type == e1000_82542_rev2_0) {
  1394. DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
  1395. pci_write_config_word(hw->pdev, PCI_COMMAND,
  1396. hw->
  1397. pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
  1398. E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
  1399. E1000_WRITE_FLUSH(hw);
  1400. mdelay(5);
  1401. }
  1402. /* Setup the receive address. This involves initializing all of the Receive
  1403. * Address Registers (RARs 0 - 15).
  1404. */
  1405. e1000_init_rx_addrs(nic);
  1406. /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
  1407. if (hw->mac_type == e1000_82542_rev2_0) {
  1408. E1000_WRITE_REG(hw, RCTL, 0);
  1409. E1000_WRITE_FLUSH(hw);
  1410. mdelay(1);
  1411. pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
  1412. }
  1413. /* Zero out the Multicast HASH table */
  1414. DEBUGOUT("Zeroing the MTA\n");
  1415. mta_size = E1000_MC_TBL_SIZE;
  1416. if (hw->mac_type == e1000_ich8lan)
  1417. mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
  1418. for (i = 0; i < mta_size; i++) {
  1419. E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
  1420. /* use write flush to prevent Memory Write Block (MWB) from
  1421. * occuring when accessing our register space */
  1422. E1000_WRITE_FLUSH(hw);
  1423. }
  1424. #if 0
  1425. /* Set the PCI priority bit correctly in the CTRL register. This
  1426. * determines if the adapter gives priority to receives, or if it
  1427. * gives equal priority to transmits and receives. Valid only on
  1428. * 82542 and 82543 silicon.
  1429. */
  1430. if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
  1431. ctrl = E1000_READ_REG(hw, CTRL);
  1432. E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
  1433. }
  1434. #endif
  1435. switch (hw->mac_type) {
  1436. case e1000_82545_rev_3:
  1437. case e1000_82546_rev_3:
  1438. break;
  1439. default:
  1440. /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
  1441. if (hw->bus_type == e1000_bus_type_pcix) {
  1442. pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
  1443. &pcix_cmd_word);
  1444. pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
  1445. &pcix_stat_hi_word);
  1446. cmd_mmrbc =
  1447. (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
  1448. PCIX_COMMAND_MMRBC_SHIFT;
  1449. stat_mmrbc =
  1450. (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
  1451. PCIX_STATUS_HI_MMRBC_SHIFT;
  1452. if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
  1453. stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
  1454. if (cmd_mmrbc > stat_mmrbc) {
  1455. pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
  1456. pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
  1457. pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
  1458. pcix_cmd_word);
  1459. }
  1460. }
  1461. break;
  1462. }
  1463. /* More time needed for PHY to initialize */
  1464. if (hw->mac_type == e1000_ich8lan)
  1465. mdelay(15);
  1466. /* Call a subroutine to configure the link and setup flow control. */
  1467. ret_val = e1000_setup_link(nic);
  1468. /* Set the transmit descriptor write-back policy */
  1469. if (hw->mac_type > e1000_82544) {
  1470. ctrl = E1000_READ_REG(hw, TXDCTL);
  1471. ctrl =
  1472. (ctrl & ~E1000_TXDCTL_WTHRESH) |
  1473. E1000_TXDCTL_FULL_TX_DESC_WB;
  1474. E1000_WRITE_REG(hw, TXDCTL, ctrl);
  1475. }
  1476. /* Set the receive descriptor write back policy */
  1477. if (hw->mac_type >= e1000_82571) {
  1478. ctrl = E1000_READ_REG(hw, RXDCTL);
  1479. ctrl =
  1480. (ctrl & ~E1000_RXDCTL_WTHRESH) |
  1481. E1000_RXDCTL_FULL_RX_DESC_WB;
  1482. E1000_WRITE_REG(hw, RXDCTL, ctrl);
  1483. }
  1484. switch (hw->mac_type) {
  1485. default:
  1486. break;
  1487. case e1000_80003es2lan:
  1488. /* Enable retransmit on late collisions */
  1489. reg_data = E1000_READ_REG(hw, TCTL);
  1490. reg_data |= E1000_TCTL_RTLC;
  1491. E1000_WRITE_REG(hw, TCTL, reg_data);
  1492. /* Configure Gigabit Carry Extend Padding */
  1493. reg_data = E1000_READ_REG(hw, TCTL_EXT);
  1494. reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
  1495. reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
  1496. E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
  1497. /* Configure Transmit Inter-Packet Gap */
  1498. reg_data = E1000_READ_REG(hw, TIPG);
  1499. reg_data &= ~E1000_TIPG_IPGT_MASK;
  1500. reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
  1501. E1000_WRITE_REG(hw, TIPG, reg_data);
  1502. reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
  1503. reg_data &= ~0x00100000;
  1504. E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
  1505. /* Fall through */
  1506. case e1000_82571:
  1507. case e1000_82572:
  1508. case e1000_ich8lan:
  1509. ctrl = E1000_READ_REG(hw, TXDCTL1);
  1510. ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
  1511. | E1000_TXDCTL_FULL_TX_DESC_WB;
  1512. E1000_WRITE_REG(hw, TXDCTL1, ctrl);
  1513. break;
  1514. case e1000_82573:
  1515. case e1000_82574:
  1516. reg_data = E1000_READ_REG(hw, GCR);
  1517. reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
  1518. E1000_WRITE_REG(hw, GCR, reg_data);
  1519. }
  1520. #if 0
  1521. /* Clear all of the statistics registers (clear on read). It is
  1522. * important that we do this after we have tried to establish link
  1523. * because the symbol error count will increment wildly if there
  1524. * is no link.
  1525. */
  1526. e1000_clear_hw_cntrs(hw);
  1527. /* ICH8 No-snoop bits are opposite polarity.
  1528. * Set to snoop by default after reset. */
  1529. if (hw->mac_type == e1000_ich8lan)
  1530. e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
  1531. #endif
  1532. if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
  1533. hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
  1534. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1535. /* Relaxed ordering must be disabled to avoid a parity
  1536. * error crash in a PCI slot. */
  1537. ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
  1538. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  1539. }
  1540. return ret_val;
  1541. }
  1542. /******************************************************************************
  1543. * Configures flow control and link settings.
  1544. *
  1545. * hw - Struct containing variables accessed by shared code
  1546. *
  1547. * Determines which flow control settings to use. Calls the apropriate media-
  1548. * specific link configuration function. Configures the flow control settings.
  1549. * Assuming the adapter has a valid link partner, a valid link should be
  1550. * established. Assumes the hardware has previously been reset and the
  1551. * transmitter and receiver are not enabled.
  1552. *****************************************************************************/
  1553. static int
  1554. e1000_setup_link(struct eth_device *nic)
  1555. {
  1556. struct e1000_hw *hw = nic->priv;
  1557. uint32_t ctrl_ext;
  1558. int32_t ret_val;
  1559. uint16_t eeprom_data;
  1560. DEBUGFUNC();
  1561. /* In the case of the phy reset being blocked, we already have a link.
  1562. * We do not have to set it up again. */
  1563. if (e1000_check_phy_reset_block(hw))
  1564. return E1000_SUCCESS;
  1565. /* Read and store word 0x0F of the EEPROM. This word contains bits
  1566. * that determine the hardware's default PAUSE (flow control) mode,
  1567. * a bit that determines whether the HW defaults to enabling or
  1568. * disabling auto-negotiation, and the direction of the
  1569. * SW defined pins. If there is no SW over-ride of the flow
  1570. * control setting, then the variable hw->fc will
  1571. * be initialized based on a value in the EEPROM.
  1572. */
  1573. if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
  1574. &eeprom_data) < 0) {
  1575. DEBUGOUT("EEPROM Read Error\n");
  1576. return -E1000_ERR_EEPROM;
  1577. }
  1578. if (hw->fc == e1000_fc_default) {
  1579. switch (hw->mac_type) {
  1580. case e1000_ich8lan:
  1581. case e1000_82573:
  1582. case e1000_82574:
  1583. hw->fc = e1000_fc_full;
  1584. break;
  1585. default:
  1586. ret_val = e1000_read_eeprom(hw,
  1587. EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
  1588. if (ret_val) {
  1589. DEBUGOUT("EEPROM Read Error\n");
  1590. return -E1000_ERR_EEPROM;
  1591. }
  1592. if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
  1593. hw->fc = e1000_fc_none;
  1594. else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
  1595. EEPROM_WORD0F_ASM_DIR)
  1596. hw->fc = e1000_fc_tx_pause;
  1597. else
  1598. hw->fc = e1000_fc_full;
  1599. break;
  1600. }
  1601. }
  1602. /* We want to save off the original Flow Control configuration just
  1603. * in case we get disconnected and then reconnected into a different
  1604. * hub or switch with different Flow Control capabilities.
  1605. */
  1606. if (hw->mac_type == e1000_82542_rev2_0)
  1607. hw->fc &= (~e1000_fc_tx_pause);
  1608. if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
  1609. hw->fc &= (~e1000_fc_rx_pause);
  1610. hw->original_fc = hw->fc;
  1611. DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
  1612. /* Take the 4 bits from EEPROM word 0x0F that determine the initial
  1613. * polarity value for the SW controlled pins, and setup the
  1614. * Extended Device Control reg with that info.
  1615. * This is needed because one of the SW controlled pins is used for
  1616. * signal detection. So this should be done before e1000_setup_pcs_link()
  1617. * or e1000_phy_setup() is called.
  1618. */
  1619. if (hw->mac_type == e1000_82543) {
  1620. ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
  1621. SWDPIO__EXT_SHIFT);
  1622. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  1623. }
  1624. /* Call the necessary subroutine to configure the link. */
  1625. ret_val = (hw->media_type == e1000_media_type_fiber) ?
  1626. e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic);
  1627. if (ret_val < 0) {
  1628. return ret_val;
  1629. }
  1630. /* Initialize the flow control address, type, and PAUSE timer
  1631. * registers to their default values. This is done even if flow
  1632. * control is disabled, because it does not hurt anything to
  1633. * initialize these registers.
  1634. */
  1635. DEBUGOUT("Initializing the Flow Control address, type"
  1636. "and timer regs\n");
  1637. /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
  1638. if (hw->mac_type != e1000_ich8lan) {
  1639. E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
  1640. E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
  1641. E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
  1642. }
  1643. E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
  1644. /* Set the flow control receive threshold registers. Normally,
  1645. * these registers will be set to a default threshold that may be
  1646. * adjusted later by the driver's runtime code. However, if the
  1647. * ability to transmit pause frames in not enabled, then these
  1648. * registers will be set to 0.
  1649. */
  1650. if (!(hw->fc & e1000_fc_tx_pause)) {
  1651. E1000_WRITE_REG(hw, FCRTL, 0);
  1652. E1000_WRITE_REG(hw, FCRTH, 0);
  1653. } else {
  1654. /* We need to set up the Receive Threshold high and low water marks
  1655. * as well as (optionally) enabling the transmission of XON frames.
  1656. */
  1657. if (hw->fc_send_xon) {
  1658. E1000_WRITE_REG(hw, FCRTL,
  1659. (hw->fc_low_water | E1000_FCRTL_XONE));
  1660. E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
  1661. } else {
  1662. E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
  1663. E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
  1664. }
  1665. }
  1666. return ret_val;
  1667. }
  1668. /******************************************************************************
  1669. * Sets up link for a fiber based adapter
  1670. *
  1671. * hw - Struct containing variables accessed by shared code
  1672. *
  1673. * Manipulates Physical Coding Sublayer functions in order to configure
  1674. * link. Assumes the hardware has been previously reset and the transmitter
  1675. * and receiver are not enabled.
  1676. *****************************************************************************/
  1677. static int
  1678. e1000_setup_fiber_link(struct eth_device *nic)
  1679. {
  1680. struct e1000_hw *hw = nic->priv;
  1681. uint32_t ctrl;
  1682. uint32_t status;
  1683. uint32_t txcw = 0;
  1684. uint32_t i;
  1685. uint32_t signal;
  1686. int32_t ret_val;
  1687. DEBUGFUNC();
  1688. /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
  1689. * set when the optics detect a signal. On older adapters, it will be
  1690. * cleared when there is a signal
  1691. */
  1692. ctrl = E1000_READ_REG(hw, CTRL);
  1693. if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
  1694. signal = E1000_CTRL_SWDPIN1;
  1695. else
  1696. signal = 0;
  1697. printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal,
  1698. ctrl);
  1699. /* Take the link out of reset */
  1700. ctrl &= ~(E1000_CTRL_LRST);
  1701. e1000_config_collision_dist(hw);
  1702. /* Check for a software override of the flow control settings, and setup
  1703. * the device accordingly. If auto-negotiation is enabled, then software
  1704. * will have to set the "PAUSE" bits to the correct value in the Tranmsit
  1705. * Config Word Register (TXCW) and re-start auto-negotiation. However, if
  1706. * auto-negotiation is disabled, then software will have to manually
  1707. * configure the two flow control enable bits in the CTRL register.
  1708. *
  1709. * The possible values of the "fc" parameter are:
  1710. * 0: Flow control is completely disabled
  1711. * 1: Rx flow control is enabled (we can receive pause frames, but
  1712. * not send pause frames).
  1713. * 2: Tx flow control is enabled (we can send pause frames but we do
  1714. * not support receiving pause frames).
  1715. * 3: Both Rx and TX flow control (symmetric) are enabled.
  1716. */
  1717. switch (hw->fc) {
  1718. case e1000_fc_none:
  1719. /* Flow control is completely disabled by a software over-ride. */
  1720. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
  1721. break;
  1722. case e1000_fc_rx_pause:
  1723. /* RX Flow control is enabled and TX Flow control is disabled by a
  1724. * software over-ride. Since there really isn't a way to advertise
  1725. * that we are capable of RX Pause ONLY, we will advertise that we
  1726. * support both symmetric and asymmetric RX PAUSE. Later, we will
  1727. * disable the adapter's ability to send PAUSE frames.
  1728. */
  1729. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
  1730. break;
  1731. case e1000_fc_tx_pause:
  1732. /* TX Flow control is enabled, and RX Flow control is disabled, by a
  1733. * software over-ride.
  1734. */
  1735. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
  1736. break;
  1737. case e1000_fc_full:
  1738. /* Flow control (both RX and TX) is enabled by a software over-ride. */
  1739. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
  1740. break;
  1741. default:
  1742. DEBUGOUT("Flow control param set incorrectly\n");
  1743. return -E1000_ERR_CONFIG;
  1744. break;
  1745. }
  1746. /* Since auto-negotiation is enabled, take the link out of reset (the link
  1747. * will be in reset, because we previously reset the chip). This will
  1748. * restart auto-negotiation. If auto-neogtiation is successful then the
  1749. * link-up status bit will be set and the flow control enable bits (RFCE
  1750. * and TFCE) will be set according to their negotiated value.
  1751. */
  1752. DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
  1753. E1000_WRITE_REG(hw, TXCW, txcw);
  1754. E1000_WRITE_REG(hw, CTRL, ctrl);
  1755. E1000_WRITE_FLUSH(hw);
  1756. hw->txcw = txcw;
  1757. mdelay(1);
  1758. /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
  1759. * indication in the Device Status Register. Time-out if a link isn't
  1760. * seen in 500 milliseconds seconds (Auto-negotiation should complete in
  1761. * less than 500 milliseconds even if the other end is doing it in SW).
  1762. */
  1763. if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
  1764. DEBUGOUT("Looking for Link\n");
  1765. for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
  1766. mdelay(10);
  1767. status = E1000_READ_REG(hw, STATUS);
  1768. if (status & E1000_STATUS_LU)
  1769. break;
  1770. }
  1771. if (i == (LINK_UP_TIMEOUT / 10)) {
  1772. /* AutoNeg failed to achieve a link, so we'll call
  1773. * e1000_check_for_link. This routine will force the link up if we
  1774. * detect a signal. This will allow us to communicate with
  1775. * non-autonegotiating link partners.
  1776. */
  1777. DEBUGOUT("Never got a valid link from auto-neg!!!\n");
  1778. hw->autoneg_failed = 1;
  1779. ret_val = e1000_check_for_link(nic);
  1780. if (ret_val < 0) {
  1781. DEBUGOUT("Error while checking for link\n");
  1782. return ret_val;
  1783. }
  1784. hw->autoneg_failed = 0;
  1785. } else {
  1786. hw->autoneg_failed = 0;
  1787. DEBUGOUT("Valid Link Found\n");
  1788. }
  1789. } else {
  1790. DEBUGOUT("No Signal Detected\n");
  1791. return -E1000_ERR_NOLINK;
  1792. }
  1793. return 0;
  1794. }
  1795. /******************************************************************************
  1796. * Make sure we have a valid PHY and change PHY mode before link setup.
  1797. *
  1798. * hw - Struct containing variables accessed by shared code
  1799. ******************************************************************************/
  1800. static int32_t
  1801. e1000_copper_link_preconfig(struct e1000_hw *hw)
  1802. {
  1803. uint32_t ctrl;
  1804. int32_t ret_val;
  1805. uint16_t phy_data;
  1806. DEBUGFUNC();
  1807. ctrl = E1000_READ_REG(hw, CTRL);
  1808. /* With 82543, we need to force speed and duplex on the MAC equal to what
  1809. * the PHY speed and duplex configuration is. In addition, we need to
  1810. * perform a hardware reset on the PHY to take it out of reset.
  1811. */
  1812. if (hw->mac_type > e1000_82543) {
  1813. ctrl |= E1000_CTRL_SLU;
  1814. ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  1815. E1000_WRITE_REG(hw, CTRL, ctrl);
  1816. } else {
  1817. ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
  1818. | E1000_CTRL_SLU);
  1819. E1000_WRITE_REG(hw, CTRL, ctrl);
  1820. ret_val = e1000_phy_hw_reset(hw);
  1821. if (ret_val)
  1822. return ret_val;
  1823. }
  1824. /* Make sure we have a valid PHY */
  1825. ret_val = e1000_detect_gig_phy(hw);
  1826. if (ret_val) {
  1827. DEBUGOUT("Error, did not detect valid phy.\n");
  1828. return ret_val;
  1829. }
  1830. DEBUGOUT("Phy ID = %x \n", hw->phy_id);
  1831. /* Set PHY to class A mode (if necessary) */
  1832. ret_val = e1000_set_phy_mode(hw);
  1833. if (ret_val)
  1834. return ret_val;
  1835. if ((hw->mac_type == e1000_82545_rev_3) ||
  1836. (hw->mac_type == e1000_82546_rev_3)) {
  1837. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  1838. &phy_data);
  1839. phy_data |= 0x00000008;
  1840. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  1841. phy_data);
  1842. }
  1843. if (hw->mac_type <= e1000_82543 ||
  1844. hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
  1845. hw->mac_type == e1000_82541_rev_2
  1846. || hw->mac_type == e1000_82547_rev_2)
  1847. hw->phy_reset_disable = false;
  1848. return E1000_SUCCESS;
  1849. }
  1850. /*****************************************************************************
  1851. *
  1852. * This function sets the lplu state according to the active flag. When
  1853. * activating lplu this function also disables smart speed and vise versa.
  1854. * lplu will not be activated unless the device autonegotiation advertisment
  1855. * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
  1856. * hw: Struct containing variables accessed by shared code
  1857. * active - true to enable lplu false to disable lplu.
  1858. *
  1859. * returns: - E1000_ERR_PHY if fail to read/write the PHY
  1860. * E1000_SUCCESS at any other case.
  1861. *
  1862. ****************************************************************************/
  1863. static int32_t
  1864. e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
  1865. {
  1866. uint32_t phy_ctrl = 0;
  1867. int32_t ret_val;
  1868. uint16_t phy_data;
  1869. DEBUGFUNC();
  1870. if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
  1871. && hw->phy_type != e1000_phy_igp_3)
  1872. return E1000_SUCCESS;
  1873. /* During driver activity LPLU should not be used or it will attain link
  1874. * from the lowest speeds starting from 10Mbps. The capability is used
  1875. * for Dx transitions and states */
  1876. if (hw->mac_type == e1000_82541_rev_2
  1877. || hw->mac_type == e1000_82547_rev_2) {
  1878. ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
  1879. &phy_data);
  1880. if (ret_val)
  1881. return ret_val;
  1882. } else if (hw->mac_type == e1000_ich8lan) {
  1883. /* MAC writes into PHY register based on the state transition
  1884. * and start auto-negotiation. SW driver can overwrite the
  1885. * settings in CSR PHY power control E1000_PHY_CTRL register. */
  1886. phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
  1887. } else {
  1888. ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
  1889. &phy_data);
  1890. if (ret_val)
  1891. return ret_val;
  1892. }
  1893. if (!active) {
  1894. if (hw->mac_type == e1000_82541_rev_2 ||
  1895. hw->mac_type == e1000_82547_rev_2) {
  1896. phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
  1897. ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
  1898. phy_data);
  1899. if (ret_val)
  1900. return ret_val;
  1901. } else {
  1902. if (hw->mac_type == e1000_ich8lan) {
  1903. phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
  1904. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  1905. } else {
  1906. phy_data &= ~IGP02E1000_PM_D3_LPLU;
  1907. ret_val = e1000_write_phy_reg(hw,
  1908. IGP02E1000_PHY_POWER_MGMT, phy_data);
  1909. if (ret_val)
  1910. return ret_val;
  1911. }
  1912. }
  1913. /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
  1914. * Dx states where the power conservation is most important. During
  1915. * driver activity we should enable SmartSpeed, so performance is
  1916. * maintained. */
  1917. if (hw->smart_speed == e1000_smart_speed_on) {
  1918. ret_val = e1000_read_phy_reg(hw,
  1919. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  1920. if (ret_val)
  1921. return ret_val;
  1922. phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
  1923. ret_val = e1000_write_phy_reg(hw,
  1924. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  1925. if (ret_val)
  1926. return ret_val;
  1927. } else if (hw->smart_speed == e1000_smart_speed_off) {
  1928. ret_val = e1000_read_phy_reg(hw,
  1929. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  1930. if (ret_val)
  1931. return ret_val;
  1932. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  1933. ret_val = e1000_write_phy_reg(hw,
  1934. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  1935. if (ret_val)
  1936. return ret_val;
  1937. }
  1938. } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
  1939. || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
  1940. (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
  1941. if (hw->mac_type == e1000_82541_rev_2 ||
  1942. hw->mac_type == e1000_82547_rev_2) {
  1943. phy_data |= IGP01E1000_GMII_FLEX_SPD;
  1944. ret_val = e1000_write_phy_reg(hw,
  1945. IGP01E1000_GMII_FIFO, phy_data);
  1946. if (ret_val)
  1947. return ret_val;
  1948. } else {
  1949. if (hw->mac_type == e1000_ich8lan) {
  1950. phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
  1951. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  1952. } else {
  1953. phy_data |= IGP02E1000_PM_D3_LPLU;
  1954. ret_val = e1000_write_phy_reg(hw,
  1955. IGP02E1000_PHY_POWER_MGMT, phy_data);
  1956. if (ret_val)
  1957. return ret_val;
  1958. }
  1959. }
  1960. /* When LPLU is enabled we should disable SmartSpeed */
  1961. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  1962. &phy_data);
  1963. if (ret_val)
  1964. return ret_val;
  1965. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  1966. ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  1967. phy_data);
  1968. if (ret_val)
  1969. return ret_val;
  1970. }
  1971. return E1000_SUCCESS;
  1972. }
  1973. /*****************************************************************************
  1974. *
  1975. * This function sets the lplu d0 state according to the active flag. When
  1976. * activating lplu this function also disables smart speed and vise versa.
  1977. * lplu will not be activated unless the device autonegotiation advertisment
  1978. * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
  1979. * hw: Struct containing variables accessed by shared code
  1980. * active - true to enable lplu false to disable lplu.
  1981. *
  1982. * returns: - E1000_ERR_PHY if fail to read/write the PHY
  1983. * E1000_SUCCESS at any other case.
  1984. *
  1985. ****************************************************************************/
  1986. static int32_t
  1987. e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
  1988. {
  1989. uint32_t phy_ctrl = 0;
  1990. int32_t ret_val;
  1991. uint16_t phy_data;
  1992. DEBUGFUNC();
  1993. if (hw->mac_type <= e1000_82547_rev_2)
  1994. return E1000_SUCCESS;
  1995. if (hw->mac_type == e1000_ich8lan) {
  1996. phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
  1997. } else {
  1998. ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
  1999. &phy_data);
  2000. if (ret_val)
  2001. return ret_val;
  2002. }
  2003. if (!active) {
  2004. if (hw->mac_type == e1000_ich8lan) {
  2005. phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
  2006. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  2007. } else {
  2008. phy_data &= ~IGP02E1000_PM_D0_LPLU;
  2009. ret_val = e1000_write_phy_reg(hw,
  2010. IGP02E1000_PHY_POWER_MGMT, phy_data);
  2011. if (ret_val)
  2012. return ret_val;
  2013. }
  2014. /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
  2015. * Dx states where the power conservation is most important. During
  2016. * driver activity we should enable SmartSpeed, so performance is
  2017. * maintained. */
  2018. if (hw->smart_speed == e1000_smart_speed_on) {
  2019. ret_val = e1000_read_phy_reg(hw,
  2020. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2021. if (ret_val)
  2022. return ret_val;
  2023. phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
  2024. ret_val = e1000_write_phy_reg(hw,
  2025. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2026. if (ret_val)
  2027. return ret_val;
  2028. } else if (hw->smart_speed == e1000_smart_speed_off) {
  2029. ret_val = e1000_read_phy_reg(hw,
  2030. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2031. if (ret_val)
  2032. return ret_val;
  2033. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2034. ret_val = e1000_write_phy_reg(hw,
  2035. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2036. if (ret_val)
  2037. return ret_val;
  2038. }
  2039. } else {
  2040. if (hw->mac_type == e1000_ich8lan) {
  2041. phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
  2042. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  2043. } else {
  2044. phy_data |= IGP02E1000_PM_D0_LPLU;
  2045. ret_val = e1000_write_phy_reg(hw,
  2046. IGP02E1000_PHY_POWER_MGMT, phy_data);
  2047. if (ret_val)
  2048. return ret_val;
  2049. }
  2050. /* When LPLU is enabled we should disable SmartSpeed */
  2051. ret_val = e1000_read_phy_reg(hw,
  2052. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2053. if (ret_val)
  2054. return ret_val;
  2055. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2056. ret_val = e1000_write_phy_reg(hw,
  2057. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2058. if (ret_val)
  2059. return ret_val;
  2060. }
  2061. return E1000_SUCCESS;
  2062. }
  2063. /********************************************************************
  2064. * Copper link setup for e1000_phy_igp series.
  2065. *
  2066. * hw - Struct containing variables accessed by shared code
  2067. *********************************************************************/
  2068. static int32_t
  2069. e1000_copper_link_igp_setup(struct e1000_hw *hw)
  2070. {
  2071. uint32_t led_ctrl;
  2072. int32_t ret_val;
  2073. uint16_t phy_data;
  2074. DEBUGFUNC();
  2075. if (hw->phy_reset_disable)
  2076. return E1000_SUCCESS;
  2077. ret_val = e1000_phy_reset(hw);
  2078. if (ret_val) {
  2079. DEBUGOUT("Error Resetting the PHY\n");
  2080. return ret_val;
  2081. }
  2082. /* Wait 15ms for MAC to configure PHY from eeprom settings */
  2083. mdelay(15);
  2084. if (hw->mac_type != e1000_ich8lan) {
  2085. /* Configure activity LED after PHY reset */
  2086. led_ctrl = E1000_READ_REG(hw, LEDCTL);
  2087. led_ctrl &= IGP_ACTIVITY_LED_MASK;
  2088. led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
  2089. E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
  2090. }
  2091. /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
  2092. if (hw->phy_type == e1000_phy_igp) {
  2093. /* disable lplu d3 during driver init */
  2094. ret_val = e1000_set_d3_lplu_state(hw, false);
  2095. if (ret_val) {
  2096. DEBUGOUT("Error Disabling LPLU D3\n");
  2097. return ret_val;
  2098. }
  2099. }
  2100. /* disable lplu d0 during driver init */
  2101. ret_val = e1000_set_d0_lplu_state(hw, false);
  2102. if (ret_val) {
  2103. DEBUGOUT("Error Disabling LPLU D0\n");
  2104. return ret_val;
  2105. }
  2106. /* Configure mdi-mdix settings */
  2107. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
  2108. if (ret_val)
  2109. return ret_val;
  2110. if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
  2111. hw->dsp_config_state = e1000_dsp_config_disabled;
  2112. /* Force MDI for earlier revs of the IGP PHY */
  2113. phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
  2114. | IGP01E1000_PSCR_FORCE_MDI_MDIX);
  2115. hw->mdix = 1;
  2116. } else {
  2117. hw->dsp_config_state = e1000_dsp_config_enabled;
  2118. phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
  2119. switch (hw->mdix) {
  2120. case 1:
  2121. phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
  2122. break;
  2123. case 2:
  2124. phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
  2125. break;
  2126. case 0:
  2127. default:
  2128. phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
  2129. break;
  2130. }
  2131. }
  2132. ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
  2133. if (ret_val)
  2134. return ret_val;
  2135. /* set auto-master slave resolution settings */
  2136. if (hw->autoneg) {
  2137. e1000_ms_type phy_ms_setting = hw->master_slave;
  2138. if (hw->ffe_config_state == e1000_ffe_config_active)
  2139. hw->ffe_config_state = e1000_ffe_config_enabled;
  2140. if (hw->dsp_config_state == e1000_dsp_config_activated)
  2141. hw->dsp_config_state = e1000_dsp_config_enabled;
  2142. /* when autonegotiation advertisment is only 1000Mbps then we
  2143. * should disable SmartSpeed and enable Auto MasterSlave
  2144. * resolution as hardware default. */
  2145. if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
  2146. /* Disable SmartSpeed */
  2147. ret_val = e1000_read_phy_reg(hw,
  2148. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2149. if (ret_val)
  2150. return ret_val;
  2151. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2152. ret_val = e1000_write_phy_reg(hw,
  2153. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2154. if (ret_val)
  2155. return ret_val;
  2156. /* Set auto Master/Slave resolution process */
  2157. ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
  2158. &phy_data);
  2159. if (ret_val)
  2160. return ret_val;
  2161. phy_data &= ~CR_1000T_MS_ENABLE;
  2162. ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
  2163. phy_data);
  2164. if (ret_val)
  2165. return ret_val;
  2166. }
  2167. ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
  2168. if (ret_val)
  2169. return ret_val;
  2170. /* load defaults for future use */
  2171. hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
  2172. ((phy_data & CR_1000T_MS_VALUE) ?
  2173. e1000_ms_force_master :
  2174. e1000_ms_force_slave) :
  2175. e1000_ms_auto;
  2176. switch (phy_ms_setting) {
  2177. case e1000_ms_force_master:
  2178. phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
  2179. break;
  2180. case e1000_ms_force_slave:
  2181. phy_data |= CR_1000T_MS_ENABLE;
  2182. phy_data &= ~(CR_1000T_MS_VALUE);
  2183. break;
  2184. case e1000_ms_auto:
  2185. phy_data &= ~CR_1000T_MS_ENABLE;
  2186. default:
  2187. break;
  2188. }
  2189. ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
  2190. if (ret_val)
  2191. return ret_val;
  2192. }
  2193. return E1000_SUCCESS;
  2194. }
  2195. /*****************************************************************************
  2196. * This function checks the mode of the firmware.
  2197. *
  2198. * returns - true when the mode is IAMT or false.
  2199. ****************************************************************************/
  2200. bool
  2201. e1000_check_mng_mode(struct e1000_hw *hw)
  2202. {
  2203. uint32_t fwsm;
  2204. DEBUGFUNC();
  2205. fwsm = E1000_READ_REG(hw, FWSM);
  2206. if (hw->mac_type == e1000_ich8lan) {
  2207. if ((fwsm & E1000_FWSM_MODE_MASK) ==
  2208. (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
  2209. return true;
  2210. } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
  2211. (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
  2212. return true;
  2213. return false;
  2214. }
  2215. static int32_t
  2216. e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
  2217. {
  2218. uint16_t swfw = E1000_SWFW_PHY0_SM;
  2219. uint32_t reg_val;
  2220. DEBUGFUNC();
  2221. if (e1000_is_second_port(hw))
  2222. swfw = E1000_SWFW_PHY1_SM;
  2223. if (e1000_swfw_sync_acquire(hw, swfw))
  2224. return -E1000_ERR_SWFW_SYNC;
  2225. reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
  2226. & E1000_KUMCTRLSTA_OFFSET) | data;
  2227. E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
  2228. udelay(2);
  2229. return E1000_SUCCESS;
  2230. }
  2231. static int32_t
  2232. e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
  2233. {
  2234. uint16_t swfw = E1000_SWFW_PHY0_SM;
  2235. uint32_t reg_val;
  2236. DEBUGFUNC();
  2237. if (e1000_is_second_port(hw))
  2238. swfw = E1000_SWFW_PHY1_SM;
  2239. if (e1000_swfw_sync_acquire(hw, swfw))
  2240. return -E1000_ERR_SWFW_SYNC;
  2241. /* Write register address */
  2242. reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
  2243. E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
  2244. E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
  2245. udelay(2);
  2246. /* Read the data returned */
  2247. reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
  2248. *data = (uint16_t)reg_val;
  2249. return E1000_SUCCESS;
  2250. }
  2251. /********************************************************************
  2252. * Copper link setup for e1000_phy_gg82563 series.
  2253. *
  2254. * hw - Struct containing variables accessed by shared code
  2255. *********************************************************************/
  2256. static int32_t
  2257. e1000_copper_link_ggp_setup(struct e1000_hw *hw)
  2258. {
  2259. int32_t ret_val;
  2260. uint16_t phy_data;
  2261. uint32_t reg_data;
  2262. DEBUGFUNC();
  2263. if (!hw->phy_reset_disable) {
  2264. /* Enable CRS on TX for half-duplex operation. */
  2265. ret_val = e1000_read_phy_reg(hw,
  2266. GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
  2267. if (ret_val)
  2268. return ret_val;
  2269. phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
  2270. /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
  2271. phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
  2272. ret_val = e1000_write_phy_reg(hw,
  2273. GG82563_PHY_MAC_SPEC_CTRL, phy_data);
  2274. if (ret_val)
  2275. return ret_val;
  2276. /* Options:
  2277. * MDI/MDI-X = 0 (default)
  2278. * 0 - Auto for all speeds
  2279. * 1 - MDI mode
  2280. * 2 - MDI-X mode
  2281. * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
  2282. */
  2283. ret_val = e1000_read_phy_reg(hw,
  2284. GG82563_PHY_SPEC_CTRL, &phy_data);
  2285. if (ret_val)
  2286. return ret_val;
  2287. phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
  2288. switch (hw->mdix) {
  2289. case 1:
  2290. phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
  2291. break;
  2292. case 2:
  2293. phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
  2294. break;
  2295. case 0:
  2296. default:
  2297. phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
  2298. break;
  2299. }
  2300. /* Options:
  2301. * disable_polarity_correction = 0 (default)
  2302. * Automatic Correction for Reversed Cable Polarity
  2303. * 0 - Disabled
  2304. * 1 - Enabled
  2305. */
  2306. phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
  2307. ret_val = e1000_write_phy_reg(hw,
  2308. GG82563_PHY_SPEC_CTRL, phy_data);
  2309. if (ret_val)
  2310. return ret_val;
  2311. /* SW Reset the PHY so all changes take effect */
  2312. ret_val = e1000_phy_reset(hw);
  2313. if (ret_val) {
  2314. DEBUGOUT("Error Resetting the PHY\n");
  2315. return ret_val;
  2316. }
  2317. } /* phy_reset_disable */
  2318. if (hw->mac_type == e1000_80003es2lan) {
  2319. /* Bypass RX and TX FIFO's */
  2320. ret_val = e1000_write_kmrn_reg(hw,
  2321. E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
  2322. E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
  2323. | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
  2324. if (ret_val)
  2325. return ret_val;
  2326. ret_val = e1000_read_phy_reg(hw,
  2327. GG82563_PHY_SPEC_CTRL_2, &phy_data);
  2328. if (ret_val)
  2329. return ret_val;
  2330. phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
  2331. ret_val = e1000_write_phy_reg(hw,
  2332. GG82563_PHY_SPEC_CTRL_2, phy_data);
  2333. if (ret_val)
  2334. return ret_val;
  2335. reg_data = E1000_READ_REG(hw, CTRL_EXT);
  2336. reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
  2337. E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
  2338. ret_val = e1000_read_phy_reg(hw,
  2339. GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
  2340. if (ret_val)
  2341. return ret_val;
  2342. /* Do not init these registers when the HW is in IAMT mode, since the
  2343. * firmware will have already initialized them. We only initialize
  2344. * them if the HW is not in IAMT mode.
  2345. */
  2346. if (e1000_check_mng_mode(hw) == false) {
  2347. /* Enable Electrical Idle on the PHY */
  2348. phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
  2349. ret_val = e1000_write_phy_reg(hw,
  2350. GG82563_PHY_PWR_MGMT_CTRL, phy_data);
  2351. if (ret_val)
  2352. return ret_val;
  2353. ret_val = e1000_read_phy_reg(hw,
  2354. GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
  2355. if (ret_val)
  2356. return ret_val;
  2357. phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  2358. ret_val = e1000_write_phy_reg(hw,
  2359. GG82563_PHY_KMRN_MODE_CTRL, phy_data);
  2360. if (ret_val)
  2361. return ret_val;
  2362. }
  2363. /* Workaround: Disable padding in Kumeran interface in the MAC
  2364. * and in the PHY to avoid CRC errors.
  2365. */
  2366. ret_val = e1000_read_phy_reg(hw,
  2367. GG82563_PHY_INBAND_CTRL, &phy_data);
  2368. if (ret_val)
  2369. return ret_val;
  2370. phy_data |= GG82563_ICR_DIS_PADDING;
  2371. ret_val = e1000_write_phy_reg(hw,
  2372. GG82563_PHY_INBAND_CTRL, phy_data);
  2373. if (ret_val)
  2374. return ret_val;
  2375. }
  2376. return E1000_SUCCESS;
  2377. }
  2378. /********************************************************************
  2379. * Copper link setup for e1000_phy_m88 series.
  2380. *
  2381. * hw - Struct containing variables accessed by shared code
  2382. *********************************************************************/
  2383. static int32_t
  2384. e1000_copper_link_mgp_setup(struct e1000_hw *hw)
  2385. {
  2386. int32_t ret_val;
  2387. uint16_t phy_data;
  2388. DEBUGFUNC();
  2389. if (hw->phy_reset_disable)
  2390. return E1000_SUCCESS;
  2391. /* Enable CRS on TX. This must be set for half-duplex operation. */
  2392. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
  2393. if (ret_val)
  2394. return ret_val;
  2395. phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
  2396. /* Options:
  2397. * MDI/MDI-X = 0 (default)
  2398. * 0 - Auto for all speeds
  2399. * 1 - MDI mode
  2400. * 2 - MDI-X mode
  2401. * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
  2402. */
  2403. phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
  2404. switch (hw->mdix) {
  2405. case 1:
  2406. phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
  2407. break;
  2408. case 2:
  2409. phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
  2410. break;
  2411. case 3:
  2412. phy_data |= M88E1000_PSCR_AUTO_X_1000T;
  2413. break;
  2414. case 0:
  2415. default:
  2416. phy_data |= M88E1000_PSCR_AUTO_X_MODE;
  2417. break;
  2418. }
  2419. /* Options:
  2420. * disable_polarity_correction = 0 (default)
  2421. * Automatic Correction for Reversed Cable Polarity
  2422. * 0 - Disabled
  2423. * 1 - Enabled
  2424. */
  2425. phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
  2426. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
  2427. if (ret_val)
  2428. return ret_val;
  2429. if (hw->phy_revision < M88E1011_I_REV_4) {
  2430. /* Force TX_CLK in the Extended PHY Specific Control Register
  2431. * to 25MHz clock.
  2432. */
  2433. ret_val = e1000_read_phy_reg(hw,
  2434. M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
  2435. if (ret_val)
  2436. return ret_val;
  2437. phy_data |= M88E1000_EPSCR_TX_CLK_25;
  2438. if ((hw->phy_revision == E1000_REVISION_2) &&
  2439. (hw->phy_id == M88E1111_I_PHY_ID)) {
  2440. /* Vidalia Phy, set the downshift counter to 5x */
  2441. phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
  2442. phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
  2443. ret_val = e1000_write_phy_reg(hw,
  2444. M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
  2445. if (ret_val)
  2446. return ret_val;
  2447. } else {
  2448. /* Configure Master and Slave downshift values */
  2449. phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
  2450. | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
  2451. phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
  2452. | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
  2453. ret_val = e1000_write_phy_reg(hw,
  2454. M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
  2455. if (ret_val)
  2456. return ret_val;
  2457. }
  2458. }
  2459. /* SW Reset the PHY so all changes take effect */
  2460. ret_val = e1000_phy_reset(hw);
  2461. if (ret_val) {
  2462. DEBUGOUT("Error Resetting the PHY\n");
  2463. return ret_val;
  2464. }
  2465. return E1000_SUCCESS;
  2466. }
  2467. /********************************************************************
  2468. * Setup auto-negotiation and flow control advertisements,
  2469. * and then perform auto-negotiation.
  2470. *
  2471. * hw - Struct containing variables accessed by shared code
  2472. *********************************************************************/
  2473. static int32_t
  2474. e1000_copper_link_autoneg(struct e1000_hw *hw)
  2475. {
  2476. int32_t ret_val;
  2477. uint16_t phy_data;
  2478. DEBUGFUNC();
  2479. /* Perform some bounds checking on the hw->autoneg_advertised
  2480. * parameter. If this variable is zero, then set it to the default.
  2481. */
  2482. hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
  2483. /* If autoneg_advertised is zero, we assume it was not defaulted
  2484. * by the calling code so we set to advertise full capability.
  2485. */
  2486. if (hw->autoneg_advertised == 0)
  2487. hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  2488. /* IFE phy only supports 10/100 */
  2489. if (hw->phy_type == e1000_phy_ife)
  2490. hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
  2491. DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
  2492. ret_val = e1000_phy_setup_autoneg(hw);
  2493. if (ret_val) {
  2494. DEBUGOUT("Error Setting up Auto-Negotiation\n");
  2495. return ret_val;
  2496. }
  2497. DEBUGOUT("Restarting Auto-Neg\n");
  2498. /* Restart auto-negotiation by setting the Auto Neg Enable bit and
  2499. * the Auto Neg Restart bit in the PHY control register.
  2500. */
  2501. ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
  2502. if (ret_val)
  2503. return ret_val;
  2504. phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
  2505. ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
  2506. if (ret_val)
  2507. return ret_val;
  2508. /* Does the user want to wait for Auto-Neg to complete here, or
  2509. * check at a later time (for example, callback routine).
  2510. */
  2511. /* If we do not wait for autonegtation to complete I
  2512. * do not see a valid link status.
  2513. * wait_autoneg_complete = 1 .
  2514. */
  2515. if (hw->wait_autoneg_complete) {
  2516. ret_val = e1000_wait_autoneg(hw);
  2517. if (ret_val) {
  2518. DEBUGOUT("Error while waiting for autoneg"
  2519. "to complete\n");
  2520. return ret_val;
  2521. }
  2522. }
  2523. hw->get_link_status = true;
  2524. return E1000_SUCCESS;
  2525. }
  2526. /******************************************************************************
  2527. * Config the MAC and the PHY after link is up.
  2528. * 1) Set up the MAC to the current PHY speed/duplex
  2529. * if we are on 82543. If we
  2530. * are on newer silicon, we only need to configure
  2531. * collision distance in the Transmit Control Register.
  2532. * 2) Set up flow control on the MAC to that established with
  2533. * the link partner.
  2534. * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
  2535. *
  2536. * hw - Struct containing variables accessed by shared code
  2537. ******************************************************************************/
  2538. static int32_t
  2539. e1000_copper_link_postconfig(struct e1000_hw *hw)
  2540. {
  2541. int32_t ret_val;
  2542. DEBUGFUNC();
  2543. if (hw->mac_type >= e1000_82544) {
  2544. e1000_config_collision_dist(hw);
  2545. } else {
  2546. ret_val = e1000_config_mac_to_phy(hw);
  2547. if (ret_val) {
  2548. DEBUGOUT("Error configuring MAC to PHY settings\n");
  2549. return ret_val;
  2550. }
  2551. }
  2552. ret_val = e1000_config_fc_after_link_up(hw);
  2553. if (ret_val) {
  2554. DEBUGOUT("Error Configuring Flow Control\n");
  2555. return ret_val;
  2556. }
  2557. return E1000_SUCCESS;
  2558. }
  2559. /******************************************************************************
  2560. * Detects which PHY is present and setup the speed and duplex
  2561. *
  2562. * hw - Struct containing variables accessed by shared code
  2563. ******************************************************************************/
  2564. static int
  2565. e1000_setup_copper_link(struct eth_device *nic)
  2566. {
  2567. struct e1000_hw *hw = nic->priv;
  2568. int32_t ret_val;
  2569. uint16_t i;
  2570. uint16_t phy_data;
  2571. uint16_t reg_data;
  2572. DEBUGFUNC();
  2573. switch (hw->mac_type) {
  2574. case e1000_80003es2lan:
  2575. case e1000_ich8lan:
  2576. /* Set the mac to wait the maximum time between each
  2577. * iteration and increase the max iterations when
  2578. * polling the phy; this fixes erroneous timeouts at 10Mbps. */
  2579. ret_val = e1000_write_kmrn_reg(hw,
  2580. GG82563_REG(0x34, 4), 0xFFFF);
  2581. if (ret_val)
  2582. return ret_val;
  2583. ret_val = e1000_read_kmrn_reg(hw,
  2584. GG82563_REG(0x34, 9), &reg_data);
  2585. if (ret_val)
  2586. return ret_val;
  2587. reg_data |= 0x3F;
  2588. ret_val = e1000_write_kmrn_reg(hw,
  2589. GG82563_REG(0x34, 9), reg_data);
  2590. if (ret_val)
  2591. return ret_val;
  2592. default:
  2593. break;
  2594. }
  2595. /* Check if it is a valid PHY and set PHY mode if necessary. */
  2596. ret_val = e1000_copper_link_preconfig(hw);
  2597. if (ret_val)
  2598. return ret_val;
  2599. switch (hw->mac_type) {
  2600. case e1000_80003es2lan:
  2601. /* Kumeran registers are written-only */
  2602. reg_data =
  2603. E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
  2604. reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
  2605. ret_val = e1000_write_kmrn_reg(hw,
  2606. E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
  2607. if (ret_val)
  2608. return ret_val;
  2609. break;
  2610. default:
  2611. break;
  2612. }
  2613. if (hw->phy_type == e1000_phy_igp ||
  2614. hw->phy_type == e1000_phy_igp_3 ||
  2615. hw->phy_type == e1000_phy_igp_2) {
  2616. ret_val = e1000_copper_link_igp_setup(hw);
  2617. if (ret_val)
  2618. return ret_val;
  2619. } else if (hw->phy_type == e1000_phy_m88) {
  2620. ret_val = e1000_copper_link_mgp_setup(hw);
  2621. if (ret_val)
  2622. return ret_val;
  2623. } else if (hw->phy_type == e1000_phy_gg82563) {
  2624. ret_val = e1000_copper_link_ggp_setup(hw);
  2625. if (ret_val)
  2626. return ret_val;
  2627. }
  2628. /* always auto */
  2629. /* Setup autoneg and flow control advertisement
  2630. * and perform autonegotiation */
  2631. ret_val = e1000_copper_link_autoneg(hw);
  2632. if (ret_val)
  2633. return ret_val;
  2634. /* Check link status. Wait up to 100 microseconds for link to become
  2635. * valid.
  2636. */
  2637. for (i = 0; i < 10; i++) {
  2638. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
  2639. if (ret_val)
  2640. return ret_val;
  2641. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
  2642. if (ret_val)
  2643. return ret_val;
  2644. if (phy_data & MII_SR_LINK_STATUS) {
  2645. /* Config the MAC and PHY after link is up */
  2646. ret_val = e1000_copper_link_postconfig(hw);
  2647. if (ret_val)
  2648. return ret_val;
  2649. DEBUGOUT("Valid link established!!!\n");
  2650. return E1000_SUCCESS;
  2651. }
  2652. udelay(10);
  2653. }
  2654. DEBUGOUT("Unable to establish link!!!\n");
  2655. return E1000_SUCCESS;
  2656. }
  2657. /******************************************************************************
  2658. * Configures PHY autoneg and flow control advertisement settings
  2659. *
  2660. * hw - Struct containing variables accessed by shared code
  2661. ******************************************************************************/
  2662. int32_t
  2663. e1000_phy_setup_autoneg(struct e1000_hw *hw)
  2664. {
  2665. int32_t ret_val;
  2666. uint16_t mii_autoneg_adv_reg;
  2667. uint16_t mii_1000t_ctrl_reg;
  2668. DEBUGFUNC();
  2669. /* Read the MII Auto-Neg Advertisement Register (Address 4). */
  2670. ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
  2671. if (ret_val)
  2672. return ret_val;
  2673. if (hw->phy_type != e1000_phy_ife) {
  2674. /* Read the MII 1000Base-T Control Register (Address 9). */
  2675. ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
  2676. &mii_1000t_ctrl_reg);
  2677. if (ret_val)
  2678. return ret_val;
  2679. } else
  2680. mii_1000t_ctrl_reg = 0;
  2681. /* Need to parse both autoneg_advertised and fc and set up
  2682. * the appropriate PHY registers. First we will parse for
  2683. * autoneg_advertised software override. Since we can advertise
  2684. * a plethora of combinations, we need to check each bit
  2685. * individually.
  2686. */
  2687. /* First we clear all the 10/100 mb speed bits in the Auto-Neg
  2688. * Advertisement Register (Address 4) and the 1000 mb speed bits in
  2689. * the 1000Base-T Control Register (Address 9).
  2690. */
  2691. mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
  2692. mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
  2693. DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
  2694. /* Do we want to advertise 10 Mb Half Duplex? */
  2695. if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
  2696. DEBUGOUT("Advertise 10mb Half duplex\n");
  2697. mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
  2698. }
  2699. /* Do we want to advertise 10 Mb Full Duplex? */
  2700. if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
  2701. DEBUGOUT("Advertise 10mb Full duplex\n");
  2702. mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
  2703. }
  2704. /* Do we want to advertise 100 Mb Half Duplex? */
  2705. if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
  2706. DEBUGOUT("Advertise 100mb Half duplex\n");
  2707. mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
  2708. }
  2709. /* Do we want to advertise 100 Mb Full Duplex? */
  2710. if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
  2711. DEBUGOUT("Advertise 100mb Full duplex\n");
  2712. mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
  2713. }
  2714. /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
  2715. if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
  2716. DEBUGOUT
  2717. ("Advertise 1000mb Half duplex requested, request denied!\n");
  2718. }
  2719. /* Do we want to advertise 1000 Mb Full Duplex? */
  2720. if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
  2721. DEBUGOUT("Advertise 1000mb Full duplex\n");
  2722. mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
  2723. }
  2724. /* Check for a software override of the flow control settings, and
  2725. * setup the PHY advertisement registers accordingly. If
  2726. * auto-negotiation is enabled, then software will have to set the
  2727. * "PAUSE" bits to the correct value in the Auto-Negotiation
  2728. * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
  2729. *
  2730. * The possible values of the "fc" parameter are:
  2731. * 0: Flow control is completely disabled
  2732. * 1: Rx flow control is enabled (we can receive pause frames
  2733. * but not send pause frames).
  2734. * 2: Tx flow control is enabled (we can send pause frames
  2735. * but we do not support receiving pause frames).
  2736. * 3: Both Rx and TX flow control (symmetric) are enabled.
  2737. * other: No software override. The flow control configuration
  2738. * in the EEPROM is used.
  2739. */
  2740. switch (hw->fc) {
  2741. case e1000_fc_none: /* 0 */
  2742. /* Flow control (RX & TX) is completely disabled by a
  2743. * software over-ride.
  2744. */
  2745. mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  2746. break;
  2747. case e1000_fc_rx_pause: /* 1 */
  2748. /* RX Flow control is enabled, and TX Flow control is
  2749. * disabled, by a software over-ride.
  2750. */
  2751. /* Since there really isn't a way to advertise that we are
  2752. * capable of RX Pause ONLY, we will advertise that we
  2753. * support both symmetric and asymmetric RX PAUSE. Later
  2754. * (in e1000_config_fc_after_link_up) we will disable the
  2755. *hw's ability to send PAUSE frames.
  2756. */
  2757. mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  2758. break;
  2759. case e1000_fc_tx_pause: /* 2 */
  2760. /* TX Flow control is enabled, and RX Flow control is
  2761. * disabled, by a software over-ride.
  2762. */
  2763. mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
  2764. mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
  2765. break;
  2766. case e1000_fc_full: /* 3 */
  2767. /* Flow control (both RX and TX) is enabled by a software
  2768. * over-ride.
  2769. */
  2770. mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  2771. break;
  2772. default:
  2773. DEBUGOUT("Flow control param set incorrectly\n");
  2774. return -E1000_ERR_CONFIG;
  2775. }
  2776. ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
  2777. if (ret_val)
  2778. return ret_val;
  2779. DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
  2780. if (hw->phy_type != e1000_phy_ife) {
  2781. ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
  2782. mii_1000t_ctrl_reg);
  2783. if (ret_val)
  2784. return ret_val;
  2785. }
  2786. return E1000_SUCCESS;
  2787. }
  2788. /******************************************************************************
  2789. * Sets the collision distance in the Transmit Control register
  2790. *
  2791. * hw - Struct containing variables accessed by shared code
  2792. *
  2793. * Link should have been established previously. Reads the speed and duplex
  2794. * information from the Device Status register.
  2795. ******************************************************************************/
  2796. static void
  2797. e1000_config_collision_dist(struct e1000_hw *hw)
  2798. {
  2799. uint32_t tctl, coll_dist;
  2800. DEBUGFUNC();
  2801. if (hw->mac_type < e1000_82543)
  2802. coll_dist = E1000_COLLISION_DISTANCE_82542;
  2803. else
  2804. coll_dist = E1000_COLLISION_DISTANCE;
  2805. tctl = E1000_READ_REG(hw, TCTL);
  2806. tctl &= ~E1000_TCTL_COLD;
  2807. tctl |= coll_dist << E1000_COLD_SHIFT;
  2808. E1000_WRITE_REG(hw, TCTL, tctl);
  2809. E1000_WRITE_FLUSH(hw);
  2810. }
  2811. /******************************************************************************
  2812. * Sets MAC speed and duplex settings to reflect the those in the PHY
  2813. *
  2814. * hw - Struct containing variables accessed by shared code
  2815. * mii_reg - data to write to the MII control register
  2816. *
  2817. * The contents of the PHY register containing the needed information need to
  2818. * be passed in.
  2819. ******************************************************************************/
  2820. static int
  2821. e1000_config_mac_to_phy(struct e1000_hw *hw)
  2822. {
  2823. uint32_t ctrl;
  2824. uint16_t phy_data;
  2825. DEBUGFUNC();
  2826. /* Read the Device Control Register and set the bits to Force Speed
  2827. * and Duplex.
  2828. */
  2829. ctrl = E1000_READ_REG(hw, CTRL);
  2830. ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  2831. ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
  2832. /* Set up duplex in the Device Control and Transmit Control
  2833. * registers depending on negotiated values.
  2834. */
  2835. if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
  2836. DEBUGOUT("PHY Read Error\n");
  2837. return -E1000_ERR_PHY;
  2838. }
  2839. if (phy_data & M88E1000_PSSR_DPLX)
  2840. ctrl |= E1000_CTRL_FD;
  2841. else
  2842. ctrl &= ~E1000_CTRL_FD;
  2843. e1000_config_collision_dist(hw);
  2844. /* Set up speed in the Device Control register depending on
  2845. * negotiated values.
  2846. */
  2847. if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
  2848. ctrl |= E1000_CTRL_SPD_1000;
  2849. else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
  2850. ctrl |= E1000_CTRL_SPD_100;
  2851. /* Write the configured values back to the Device Control Reg. */
  2852. E1000_WRITE_REG(hw, CTRL, ctrl);
  2853. return 0;
  2854. }
  2855. /******************************************************************************
  2856. * Forces the MAC's flow control settings.
  2857. *
  2858. * hw - Struct containing variables accessed by shared code
  2859. *
  2860. * Sets the TFCE and RFCE bits in the device control register to reflect
  2861. * the adapter settings. TFCE and RFCE need to be explicitly set by
  2862. * software when a Copper PHY is used because autonegotiation is managed
  2863. * by the PHY rather than the MAC. Software must also configure these
  2864. * bits when link is forced on a fiber connection.
  2865. *****************************************************************************/
  2866. static int
  2867. e1000_force_mac_fc(struct e1000_hw *hw)
  2868. {
  2869. uint32_t ctrl;
  2870. DEBUGFUNC();
  2871. /* Get the current configuration of the Device Control Register */
  2872. ctrl = E1000_READ_REG(hw, CTRL);
  2873. /* Because we didn't get link via the internal auto-negotiation
  2874. * mechanism (we either forced link or we got link via PHY
  2875. * auto-neg), we have to manually enable/disable transmit an
  2876. * receive flow control.
  2877. *
  2878. * The "Case" statement below enables/disable flow control
  2879. * according to the "hw->fc" parameter.
  2880. *
  2881. * The possible values of the "fc" parameter are:
  2882. * 0: Flow control is completely disabled
  2883. * 1: Rx flow control is enabled (we can receive pause
  2884. * frames but not send pause frames).
  2885. * 2: Tx flow control is enabled (we can send pause frames
  2886. * frames but we do not receive pause frames).
  2887. * 3: Both Rx and TX flow control (symmetric) is enabled.
  2888. * other: No other values should be possible at this point.
  2889. */
  2890. switch (hw->fc) {
  2891. case e1000_fc_none:
  2892. ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
  2893. break;
  2894. case e1000_fc_rx_pause:
  2895. ctrl &= (~E1000_CTRL_TFCE);
  2896. ctrl |= E1000_CTRL_RFCE;
  2897. break;
  2898. case e1000_fc_tx_pause:
  2899. ctrl &= (~E1000_CTRL_RFCE);
  2900. ctrl |= E1000_CTRL_TFCE;
  2901. break;
  2902. case e1000_fc_full:
  2903. ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
  2904. break;
  2905. default:
  2906. DEBUGOUT("Flow control param set incorrectly\n");
  2907. return -E1000_ERR_CONFIG;
  2908. }
  2909. /* Disable TX Flow Control for 82542 (rev 2.0) */
  2910. if (hw->mac_type == e1000_82542_rev2_0)
  2911. ctrl &= (~E1000_CTRL_TFCE);
  2912. E1000_WRITE_REG(hw, CTRL, ctrl);
  2913. return 0;
  2914. }
  2915. /******************************************************************************
  2916. * Configures flow control settings after link is established
  2917. *
  2918. * hw - Struct containing variables accessed by shared code
  2919. *
  2920. * Should be called immediately after a valid link has been established.
  2921. * Forces MAC flow control settings if link was forced. When in MII/GMII mode
  2922. * and autonegotiation is enabled, the MAC flow control settings will be set
  2923. * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
  2924. * and RFCE bits will be automaticaly set to the negotiated flow control mode.
  2925. *****************************************************************************/
  2926. static int32_t
  2927. e1000_config_fc_after_link_up(struct e1000_hw *hw)
  2928. {
  2929. int32_t ret_val;
  2930. uint16_t mii_status_reg;
  2931. uint16_t mii_nway_adv_reg;
  2932. uint16_t mii_nway_lp_ability_reg;
  2933. uint16_t speed;
  2934. uint16_t duplex;
  2935. DEBUGFUNC();
  2936. /* Check for the case where we have fiber media and auto-neg failed
  2937. * so we had to force link. In this case, we need to force the
  2938. * configuration of the MAC to match the "fc" parameter.
  2939. */
  2940. if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
  2941. || ((hw->media_type == e1000_media_type_internal_serdes)
  2942. && (hw->autoneg_failed))
  2943. || ((hw->media_type == e1000_media_type_copper)
  2944. && (!hw->autoneg))) {
  2945. ret_val = e1000_force_mac_fc(hw);
  2946. if (ret_val < 0) {
  2947. DEBUGOUT("Error forcing flow control settings\n");
  2948. return ret_val;
  2949. }
  2950. }
  2951. /* Check for the case where we have copper media and auto-neg is
  2952. * enabled. In this case, we need to check and see if Auto-Neg
  2953. * has completed, and if so, how the PHY and link partner has
  2954. * flow control configured.
  2955. */
  2956. if (hw->media_type == e1000_media_type_copper) {
  2957. /* Read the MII Status Register and check to see if AutoNeg
  2958. * has completed. We read this twice because this reg has
  2959. * some "sticky" (latched) bits.
  2960. */
  2961. if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  2962. DEBUGOUT("PHY Read Error \n");
  2963. return -E1000_ERR_PHY;
  2964. }
  2965. if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  2966. DEBUGOUT("PHY Read Error \n");
  2967. return -E1000_ERR_PHY;
  2968. }
  2969. if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
  2970. /* The AutoNeg process has completed, so we now need to
  2971. * read both the Auto Negotiation Advertisement Register
  2972. * (Address 4) and the Auto_Negotiation Base Page Ability
  2973. * Register (Address 5) to determine how flow control was
  2974. * negotiated.
  2975. */
  2976. if (e1000_read_phy_reg
  2977. (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
  2978. DEBUGOUT("PHY Read Error\n");
  2979. return -E1000_ERR_PHY;
  2980. }
  2981. if (e1000_read_phy_reg
  2982. (hw, PHY_LP_ABILITY,
  2983. &mii_nway_lp_ability_reg) < 0) {
  2984. DEBUGOUT("PHY Read Error\n");
  2985. return -E1000_ERR_PHY;
  2986. }
  2987. /* Two bits in the Auto Negotiation Advertisement Register
  2988. * (Address 4) and two bits in the Auto Negotiation Base
  2989. * Page Ability Register (Address 5) determine flow control
  2990. * for both the PHY and the link partner. The following
  2991. * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
  2992. * 1999, describes these PAUSE resolution bits and how flow
  2993. * control is determined based upon these settings.
  2994. * NOTE: DC = Don't Care
  2995. *
  2996. * LOCAL DEVICE | LINK PARTNER
  2997. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
  2998. *-------|---------|-------|---------|--------------------
  2999. * 0 | 0 | DC | DC | e1000_fc_none
  3000. * 0 | 1 | 0 | DC | e1000_fc_none
  3001. * 0 | 1 | 1 | 0 | e1000_fc_none
  3002. * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
  3003. * 1 | 0 | 0 | DC | e1000_fc_none
  3004. * 1 | DC | 1 | DC | e1000_fc_full
  3005. * 1 | 1 | 0 | 0 | e1000_fc_none
  3006. * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
  3007. *
  3008. */
  3009. /* Are both PAUSE bits set to 1? If so, this implies
  3010. * Symmetric Flow Control is enabled at both ends. The
  3011. * ASM_DIR bits are irrelevant per the spec.
  3012. *
  3013. * For Symmetric Flow Control:
  3014. *
  3015. * LOCAL DEVICE | LINK PARTNER
  3016. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  3017. *-------|---------|-------|---------|--------------------
  3018. * 1 | DC | 1 | DC | e1000_fc_full
  3019. *
  3020. */
  3021. if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  3022. (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
  3023. /* Now we need to check if the user selected RX ONLY
  3024. * of pause frames. In this case, we had to advertise
  3025. * FULL flow control because we could not advertise RX
  3026. * ONLY. Hence, we must now check to see if we need to
  3027. * turn OFF the TRANSMISSION of PAUSE frames.
  3028. */
  3029. if (hw->original_fc == e1000_fc_full) {
  3030. hw->fc = e1000_fc_full;
  3031. DEBUGOUT("Flow Control = FULL.\r\n");
  3032. } else {
  3033. hw->fc = e1000_fc_rx_pause;
  3034. DEBUGOUT
  3035. ("Flow Control = RX PAUSE frames only.\r\n");
  3036. }
  3037. }
  3038. /* For receiving PAUSE frames ONLY.
  3039. *
  3040. * LOCAL DEVICE | LINK PARTNER
  3041. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  3042. *-------|---------|-------|---------|--------------------
  3043. * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
  3044. *
  3045. */
  3046. else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  3047. (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
  3048. (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
  3049. (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
  3050. {
  3051. hw->fc = e1000_fc_tx_pause;
  3052. DEBUGOUT
  3053. ("Flow Control = TX PAUSE frames only.\r\n");
  3054. }
  3055. /* For transmitting PAUSE frames ONLY.
  3056. *
  3057. * LOCAL DEVICE | LINK PARTNER
  3058. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  3059. *-------|---------|-------|---------|--------------------
  3060. * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
  3061. *
  3062. */
  3063. else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  3064. (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
  3065. !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
  3066. (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
  3067. {
  3068. hw->fc = e1000_fc_rx_pause;
  3069. DEBUGOUT
  3070. ("Flow Control = RX PAUSE frames only.\r\n");
  3071. }
  3072. /* Per the IEEE spec, at this point flow control should be
  3073. * disabled. However, we want to consider that we could
  3074. * be connected to a legacy switch that doesn't advertise
  3075. * desired flow control, but can be forced on the link
  3076. * partner. So if we advertised no flow control, that is
  3077. * what we will resolve to. If we advertised some kind of
  3078. * receive capability (Rx Pause Only or Full Flow Control)
  3079. * and the link partner advertised none, we will configure
  3080. * ourselves to enable Rx Flow Control only. We can do
  3081. * this safely for two reasons: If the link partner really
  3082. * didn't want flow control enabled, and we enable Rx, no
  3083. * harm done since we won't be receiving any PAUSE frames
  3084. * anyway. If the intent on the link partner was to have
  3085. * flow control enabled, then by us enabling RX only, we
  3086. * can at least receive pause frames and process them.
  3087. * This is a good idea because in most cases, since we are
  3088. * predominantly a server NIC, more times than not we will
  3089. * be asked to delay transmission of packets than asking
  3090. * our link partner to pause transmission of frames.
  3091. */
  3092. else if (hw->original_fc == e1000_fc_none ||
  3093. hw->original_fc == e1000_fc_tx_pause) {
  3094. hw->fc = e1000_fc_none;
  3095. DEBUGOUT("Flow Control = NONE.\r\n");
  3096. } else {
  3097. hw->fc = e1000_fc_rx_pause;
  3098. DEBUGOUT
  3099. ("Flow Control = RX PAUSE frames only.\r\n");
  3100. }
  3101. /* Now we need to do one last check... If we auto-
  3102. * negotiated to HALF DUPLEX, flow control should not be
  3103. * enabled per IEEE 802.3 spec.
  3104. */
  3105. e1000_get_speed_and_duplex(hw, &speed, &duplex);
  3106. if (duplex == HALF_DUPLEX)
  3107. hw->fc = e1000_fc_none;
  3108. /* Now we call a subroutine to actually force the MAC
  3109. * controller to use the correct flow control settings.
  3110. */
  3111. ret_val = e1000_force_mac_fc(hw);
  3112. if (ret_val < 0) {
  3113. DEBUGOUT
  3114. ("Error forcing flow control settings\n");
  3115. return ret_val;
  3116. }
  3117. } else {
  3118. DEBUGOUT
  3119. ("Copper PHY and Auto Neg has not completed.\r\n");
  3120. }
  3121. }
  3122. return E1000_SUCCESS;
  3123. }
  3124. /******************************************************************************
  3125. * Checks to see if the link status of the hardware has changed.
  3126. *
  3127. * hw - Struct containing variables accessed by shared code
  3128. *
  3129. * Called by any function that needs to check the link status of the adapter.
  3130. *****************************************************************************/
  3131. static int
  3132. e1000_check_for_link(struct eth_device *nic)
  3133. {
  3134. struct e1000_hw *hw = nic->priv;
  3135. uint32_t rxcw;
  3136. uint32_t ctrl;
  3137. uint32_t status;
  3138. uint32_t rctl;
  3139. uint32_t signal;
  3140. int32_t ret_val;
  3141. uint16_t phy_data;
  3142. uint16_t lp_capability;
  3143. DEBUGFUNC();
  3144. /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
  3145. * set when the optics detect a signal. On older adapters, it will be
  3146. * cleared when there is a signal
  3147. */
  3148. ctrl = E1000_READ_REG(hw, CTRL);
  3149. if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
  3150. signal = E1000_CTRL_SWDPIN1;
  3151. else
  3152. signal = 0;
  3153. status = E1000_READ_REG(hw, STATUS);
  3154. rxcw = E1000_READ_REG(hw, RXCW);
  3155. DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
  3156. /* If we have a copper PHY then we only want to go out to the PHY
  3157. * registers to see if Auto-Neg has completed and/or if our link
  3158. * status has changed. The get_link_status flag will be set if we
  3159. * receive a Link Status Change interrupt or we have Rx Sequence
  3160. * Errors.
  3161. */
  3162. if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
  3163. /* First we want to see if the MII Status Register reports
  3164. * link. If so, then we want to get the current speed/duplex
  3165. * of the PHY.
  3166. * Read the register twice since the link bit is sticky.
  3167. */
  3168. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3169. DEBUGOUT("PHY Read Error\n");
  3170. return -E1000_ERR_PHY;
  3171. }
  3172. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3173. DEBUGOUT("PHY Read Error\n");
  3174. return -E1000_ERR_PHY;
  3175. }
  3176. if (phy_data & MII_SR_LINK_STATUS) {
  3177. hw->get_link_status = false;
  3178. } else {
  3179. /* No link detected */
  3180. return -E1000_ERR_NOLINK;
  3181. }
  3182. /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
  3183. * have Si on board that is 82544 or newer, Auto
  3184. * Speed Detection takes care of MAC speed/duplex
  3185. * configuration. So we only need to configure Collision
  3186. * Distance in the MAC. Otherwise, we need to force
  3187. * speed/duplex on the MAC to the current PHY speed/duplex
  3188. * settings.
  3189. */
  3190. if (hw->mac_type >= e1000_82544)
  3191. e1000_config_collision_dist(hw);
  3192. else {
  3193. ret_val = e1000_config_mac_to_phy(hw);
  3194. if (ret_val < 0) {
  3195. DEBUGOUT
  3196. ("Error configuring MAC to PHY settings\n");
  3197. return ret_val;
  3198. }
  3199. }
  3200. /* Configure Flow Control now that Auto-Neg has completed. First, we
  3201. * need to restore the desired flow control settings because we may
  3202. * have had to re-autoneg with a different link partner.
  3203. */
  3204. ret_val = e1000_config_fc_after_link_up(hw);
  3205. if (ret_val < 0) {
  3206. DEBUGOUT("Error configuring flow control\n");
  3207. return ret_val;
  3208. }
  3209. /* At this point we know that we are on copper and we have
  3210. * auto-negotiated link. These are conditions for checking the link
  3211. * parter capability register. We use the link partner capability to
  3212. * determine if TBI Compatibility needs to be turned on or off. If
  3213. * the link partner advertises any speed in addition to Gigabit, then
  3214. * we assume that they are GMII-based, and TBI compatibility is not
  3215. * needed. If no other speeds are advertised, we assume the link
  3216. * partner is TBI-based, and we turn on TBI Compatibility.
  3217. */
  3218. if (hw->tbi_compatibility_en) {
  3219. if (e1000_read_phy_reg
  3220. (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
  3221. DEBUGOUT("PHY Read Error\n");
  3222. return -E1000_ERR_PHY;
  3223. }
  3224. if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
  3225. NWAY_LPAR_10T_FD_CAPS |
  3226. NWAY_LPAR_100TX_HD_CAPS |
  3227. NWAY_LPAR_100TX_FD_CAPS |
  3228. NWAY_LPAR_100T4_CAPS)) {
  3229. /* If our link partner advertises anything in addition to
  3230. * gigabit, we do not need to enable TBI compatibility.
  3231. */
  3232. if (hw->tbi_compatibility_on) {
  3233. /* If we previously were in the mode, turn it off. */
  3234. rctl = E1000_READ_REG(hw, RCTL);
  3235. rctl &= ~E1000_RCTL_SBP;
  3236. E1000_WRITE_REG(hw, RCTL, rctl);
  3237. hw->tbi_compatibility_on = false;
  3238. }
  3239. } else {
  3240. /* If TBI compatibility is was previously off, turn it on. For
  3241. * compatibility with a TBI link partner, we will store bad
  3242. * packets. Some frames have an additional byte on the end and
  3243. * will look like CRC errors to to the hardware.
  3244. */
  3245. if (!hw->tbi_compatibility_on) {
  3246. hw->tbi_compatibility_on = true;
  3247. rctl = E1000_READ_REG(hw, RCTL);
  3248. rctl |= E1000_RCTL_SBP;
  3249. E1000_WRITE_REG(hw, RCTL, rctl);
  3250. }
  3251. }
  3252. }
  3253. }
  3254. /* If we don't have link (auto-negotiation failed or link partner cannot
  3255. * auto-negotiate), the cable is plugged in (we have signal), and our
  3256. * link partner is not trying to auto-negotiate with us (we are receiving
  3257. * idles or data), we need to force link up. We also need to give
  3258. * auto-negotiation time to complete, in case the cable was just plugged
  3259. * in. The autoneg_failed flag does this.
  3260. */
  3261. else if ((hw->media_type == e1000_media_type_fiber) &&
  3262. (!(status & E1000_STATUS_LU)) &&
  3263. ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
  3264. (!(rxcw & E1000_RXCW_C))) {
  3265. if (hw->autoneg_failed == 0) {
  3266. hw->autoneg_failed = 1;
  3267. return 0;
  3268. }
  3269. DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
  3270. /* Disable auto-negotiation in the TXCW register */
  3271. E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
  3272. /* Force link-up and also force full-duplex. */
  3273. ctrl = E1000_READ_REG(hw, CTRL);
  3274. ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
  3275. E1000_WRITE_REG(hw, CTRL, ctrl);
  3276. /* Configure Flow Control after forcing link up. */
  3277. ret_val = e1000_config_fc_after_link_up(hw);
  3278. if (ret_val < 0) {
  3279. DEBUGOUT("Error configuring flow control\n");
  3280. return ret_val;
  3281. }
  3282. }
  3283. /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
  3284. * auto-negotiation in the TXCW register and disable forced link in the
  3285. * Device Control register in an attempt to auto-negotiate with our link
  3286. * partner.
  3287. */
  3288. else if ((hw->media_type == e1000_media_type_fiber) &&
  3289. (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
  3290. DEBUGOUT
  3291. ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
  3292. E1000_WRITE_REG(hw, TXCW, hw->txcw);
  3293. E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
  3294. }
  3295. return 0;
  3296. }
  3297. /******************************************************************************
  3298. * Configure the MAC-to-PHY interface for 10/100Mbps
  3299. *
  3300. * hw - Struct containing variables accessed by shared code
  3301. ******************************************************************************/
  3302. static int32_t
  3303. e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
  3304. {
  3305. int32_t ret_val = E1000_SUCCESS;
  3306. uint32_t tipg;
  3307. uint16_t reg_data;
  3308. DEBUGFUNC();
  3309. reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
  3310. ret_val = e1000_write_kmrn_reg(hw,
  3311. E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
  3312. if (ret_val)
  3313. return ret_val;
  3314. /* Configure Transmit Inter-Packet Gap */
  3315. tipg = E1000_READ_REG(hw, TIPG);
  3316. tipg &= ~E1000_TIPG_IPGT_MASK;
  3317. tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
  3318. E1000_WRITE_REG(hw, TIPG, tipg);
  3319. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
  3320. if (ret_val)
  3321. return ret_val;
  3322. if (duplex == HALF_DUPLEX)
  3323. reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
  3324. else
  3325. reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  3326. ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
  3327. return ret_val;
  3328. }
  3329. static int32_t
  3330. e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
  3331. {
  3332. int32_t ret_val = E1000_SUCCESS;
  3333. uint16_t reg_data;
  3334. uint32_t tipg;
  3335. DEBUGFUNC();
  3336. reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
  3337. ret_val = e1000_write_kmrn_reg(hw,
  3338. E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
  3339. if (ret_val)
  3340. return ret_val;
  3341. /* Configure Transmit Inter-Packet Gap */
  3342. tipg = E1000_READ_REG(hw, TIPG);
  3343. tipg &= ~E1000_TIPG_IPGT_MASK;
  3344. tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
  3345. E1000_WRITE_REG(hw, TIPG, tipg);
  3346. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
  3347. if (ret_val)
  3348. return ret_val;
  3349. reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  3350. ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
  3351. return ret_val;
  3352. }
  3353. /******************************************************************************
  3354. * Detects the current speed and duplex settings of the hardware.
  3355. *
  3356. * hw - Struct containing variables accessed by shared code
  3357. * speed - Speed of the connection
  3358. * duplex - Duplex setting of the connection
  3359. *****************************************************************************/
  3360. static int
  3361. e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
  3362. uint16_t *duplex)
  3363. {
  3364. uint32_t status;
  3365. int32_t ret_val;
  3366. uint16_t phy_data;
  3367. DEBUGFUNC();
  3368. if (hw->mac_type >= e1000_82543) {
  3369. status = E1000_READ_REG(hw, STATUS);
  3370. if (status & E1000_STATUS_SPEED_1000) {
  3371. *speed = SPEED_1000;
  3372. DEBUGOUT("1000 Mbs, ");
  3373. } else if (status & E1000_STATUS_SPEED_100) {
  3374. *speed = SPEED_100;
  3375. DEBUGOUT("100 Mbs, ");
  3376. } else {
  3377. *speed = SPEED_10;
  3378. DEBUGOUT("10 Mbs, ");
  3379. }
  3380. if (status & E1000_STATUS_FD) {
  3381. *duplex = FULL_DUPLEX;
  3382. DEBUGOUT("Full Duplex\r\n");
  3383. } else {
  3384. *duplex = HALF_DUPLEX;
  3385. DEBUGOUT(" Half Duplex\r\n");
  3386. }
  3387. } else {
  3388. DEBUGOUT("1000 Mbs, Full Duplex\r\n");
  3389. *speed = SPEED_1000;
  3390. *duplex = FULL_DUPLEX;
  3391. }
  3392. /* IGP01 PHY may advertise full duplex operation after speed downgrade
  3393. * even if it is operating at half duplex. Here we set the duplex
  3394. * settings to match the duplex in the link partner's capabilities.
  3395. */
  3396. if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
  3397. ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
  3398. if (ret_val)
  3399. return ret_val;
  3400. if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
  3401. *duplex = HALF_DUPLEX;
  3402. else {
  3403. ret_val = e1000_read_phy_reg(hw,
  3404. PHY_LP_ABILITY, &phy_data);
  3405. if (ret_val)
  3406. return ret_val;
  3407. if ((*speed == SPEED_100 &&
  3408. !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
  3409. || (*speed == SPEED_10
  3410. && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
  3411. *duplex = HALF_DUPLEX;
  3412. }
  3413. }
  3414. if ((hw->mac_type == e1000_80003es2lan) &&
  3415. (hw->media_type == e1000_media_type_copper)) {
  3416. if (*speed == SPEED_1000)
  3417. ret_val = e1000_configure_kmrn_for_1000(hw);
  3418. else
  3419. ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
  3420. if (ret_val)
  3421. return ret_val;
  3422. }
  3423. return E1000_SUCCESS;
  3424. }
  3425. /******************************************************************************
  3426. * Blocks until autoneg completes or times out (~4.5 seconds)
  3427. *
  3428. * hw - Struct containing variables accessed by shared code
  3429. ******************************************************************************/
  3430. static int
  3431. e1000_wait_autoneg(struct e1000_hw *hw)
  3432. {
  3433. uint16_t i;
  3434. uint16_t phy_data;
  3435. DEBUGFUNC();
  3436. DEBUGOUT("Waiting for Auto-Neg to complete.\n");
  3437. /* We will wait for autoneg to complete or 4.5 seconds to expire. */
  3438. for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
  3439. /* Read the MII Status Register and wait for Auto-Neg
  3440. * Complete bit to be set.
  3441. */
  3442. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3443. DEBUGOUT("PHY Read Error\n");
  3444. return -E1000_ERR_PHY;
  3445. }
  3446. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3447. DEBUGOUT("PHY Read Error\n");
  3448. return -E1000_ERR_PHY;
  3449. }
  3450. if (phy_data & MII_SR_AUTONEG_COMPLETE) {
  3451. DEBUGOUT("Auto-Neg complete.\n");
  3452. return 0;
  3453. }
  3454. mdelay(100);
  3455. }
  3456. DEBUGOUT("Auto-Neg timedout.\n");
  3457. return -E1000_ERR_TIMEOUT;
  3458. }
  3459. /******************************************************************************
  3460. * Raises the Management Data Clock
  3461. *
  3462. * hw - Struct containing variables accessed by shared code
  3463. * ctrl - Device control register's current value
  3464. ******************************************************************************/
  3465. static void
  3466. e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
  3467. {
  3468. /* Raise the clock input to the Management Data Clock (by setting the MDC
  3469. * bit), and then delay 2 microseconds.
  3470. */
  3471. E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
  3472. E1000_WRITE_FLUSH(hw);
  3473. udelay(2);
  3474. }
  3475. /******************************************************************************
  3476. * Lowers the Management Data Clock
  3477. *
  3478. * hw - Struct containing variables accessed by shared code
  3479. * ctrl - Device control register's current value
  3480. ******************************************************************************/
  3481. static void
  3482. e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
  3483. {
  3484. /* Lower the clock input to the Management Data Clock (by clearing the MDC
  3485. * bit), and then delay 2 microseconds.
  3486. */
  3487. E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
  3488. E1000_WRITE_FLUSH(hw);
  3489. udelay(2);
  3490. }
  3491. /******************************************************************************
  3492. * Shifts data bits out to the PHY
  3493. *
  3494. * hw - Struct containing variables accessed by shared code
  3495. * data - Data to send out to the PHY
  3496. * count - Number of bits to shift out
  3497. *
  3498. * Bits are shifted out in MSB to LSB order.
  3499. ******************************************************************************/
  3500. static void
  3501. e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
  3502. {
  3503. uint32_t ctrl;
  3504. uint32_t mask;
  3505. /* We need to shift "count" number of bits out to the PHY. So, the value
  3506. * in the "data" parameter will be shifted out to the PHY one bit at a
  3507. * time. In order to do this, "data" must be broken down into bits.
  3508. */
  3509. mask = 0x01;
  3510. mask <<= (count - 1);
  3511. ctrl = E1000_READ_REG(hw, CTRL);
  3512. /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
  3513. ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
  3514. while (mask) {
  3515. /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
  3516. * then raising and lowering the Management Data Clock. A "0" is
  3517. * shifted out to the PHY by setting the MDIO bit to "0" and then
  3518. * raising and lowering the clock.
  3519. */
  3520. if (data & mask)
  3521. ctrl |= E1000_CTRL_MDIO;
  3522. else
  3523. ctrl &= ~E1000_CTRL_MDIO;
  3524. E1000_WRITE_REG(hw, CTRL, ctrl);
  3525. E1000_WRITE_FLUSH(hw);
  3526. udelay(2);
  3527. e1000_raise_mdi_clk(hw, &ctrl);
  3528. e1000_lower_mdi_clk(hw, &ctrl);
  3529. mask = mask >> 1;
  3530. }
  3531. }
  3532. /******************************************************************************
  3533. * Shifts data bits in from the PHY
  3534. *
  3535. * hw - Struct containing variables accessed by shared code
  3536. *
  3537. * Bits are shifted in in MSB to LSB order.
  3538. ******************************************************************************/
  3539. static uint16_t
  3540. e1000_shift_in_mdi_bits(struct e1000_hw *hw)
  3541. {
  3542. uint32_t ctrl;
  3543. uint16_t data = 0;
  3544. uint8_t i;
  3545. /* In order to read a register from the PHY, we need to shift in a total
  3546. * of 18 bits from the PHY. The first two bit (turnaround) times are used
  3547. * to avoid contention on the MDIO pin when a read operation is performed.
  3548. * These two bits are ignored by us and thrown away. Bits are "shifted in"
  3549. * by raising the input to the Management Data Clock (setting the MDC bit),
  3550. * and then reading the value of the MDIO bit.
  3551. */
  3552. ctrl = E1000_READ_REG(hw, CTRL);
  3553. /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
  3554. ctrl &= ~E1000_CTRL_MDIO_DIR;
  3555. ctrl &= ~E1000_CTRL_MDIO;
  3556. E1000_WRITE_REG(hw, CTRL, ctrl);
  3557. E1000_WRITE_FLUSH(hw);
  3558. /* Raise and Lower the clock before reading in the data. This accounts for
  3559. * the turnaround bits. The first clock occurred when we clocked out the
  3560. * last bit of the Register Address.
  3561. */
  3562. e1000_raise_mdi_clk(hw, &ctrl);
  3563. e1000_lower_mdi_clk(hw, &ctrl);
  3564. for (data = 0, i = 0; i < 16; i++) {
  3565. data = data << 1;
  3566. e1000_raise_mdi_clk(hw, &ctrl);
  3567. ctrl = E1000_READ_REG(hw, CTRL);
  3568. /* Check to see if we shifted in a "1". */
  3569. if (ctrl & E1000_CTRL_MDIO)
  3570. data |= 1;
  3571. e1000_lower_mdi_clk(hw, &ctrl);
  3572. }
  3573. e1000_raise_mdi_clk(hw, &ctrl);
  3574. e1000_lower_mdi_clk(hw, &ctrl);
  3575. return data;
  3576. }
  3577. /*****************************************************************************
  3578. * Reads the value from a PHY register
  3579. *
  3580. * hw - Struct containing variables accessed by shared code
  3581. * reg_addr - address of the PHY register to read
  3582. ******************************************************************************/
  3583. static int
  3584. e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
  3585. {
  3586. uint32_t i;
  3587. uint32_t mdic = 0;
  3588. const uint32_t phy_addr = 1;
  3589. if (reg_addr > MAX_PHY_REG_ADDRESS) {
  3590. DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
  3591. return -E1000_ERR_PARAM;
  3592. }
  3593. if (hw->mac_type > e1000_82543) {
  3594. /* Set up Op-code, Phy Address, and register address in the MDI
  3595. * Control register. The MAC will take care of interfacing with the
  3596. * PHY to retrieve the desired data.
  3597. */
  3598. mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
  3599. (phy_addr << E1000_MDIC_PHY_SHIFT) |
  3600. (E1000_MDIC_OP_READ));
  3601. E1000_WRITE_REG(hw, MDIC, mdic);
  3602. /* Poll the ready bit to see if the MDI read completed */
  3603. for (i = 0; i < 64; i++) {
  3604. udelay(10);
  3605. mdic = E1000_READ_REG(hw, MDIC);
  3606. if (mdic & E1000_MDIC_READY)
  3607. break;
  3608. }
  3609. if (!(mdic & E1000_MDIC_READY)) {
  3610. DEBUGOUT("MDI Read did not complete\n");
  3611. return -E1000_ERR_PHY;
  3612. }
  3613. if (mdic & E1000_MDIC_ERROR) {
  3614. DEBUGOUT("MDI Error\n");
  3615. return -E1000_ERR_PHY;
  3616. }
  3617. *phy_data = (uint16_t) mdic;
  3618. } else {
  3619. /* We must first send a preamble through the MDIO pin to signal the
  3620. * beginning of an MII instruction. This is done by sending 32
  3621. * consecutive "1" bits.
  3622. */
  3623. e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
  3624. /* Now combine the next few fields that are required for a read
  3625. * operation. We use this method instead of calling the
  3626. * e1000_shift_out_mdi_bits routine five different times. The format of
  3627. * a MII read instruction consists of a shift out of 14 bits and is
  3628. * defined as follows:
  3629. * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
  3630. * followed by a shift in of 18 bits. This first two bits shifted in
  3631. * are TurnAround bits used to avoid contention on the MDIO pin when a
  3632. * READ operation is performed. These two bits are thrown away
  3633. * followed by a shift in of 16 bits which contains the desired data.
  3634. */
  3635. mdic = ((reg_addr) | (phy_addr << 5) |
  3636. (PHY_OP_READ << 10) | (PHY_SOF << 12));
  3637. e1000_shift_out_mdi_bits(hw, mdic, 14);
  3638. /* Now that we've shifted out the read command to the MII, we need to
  3639. * "shift in" the 16-bit value (18 total bits) of the requested PHY
  3640. * register address.
  3641. */
  3642. *phy_data = e1000_shift_in_mdi_bits(hw);
  3643. }
  3644. return 0;
  3645. }
  3646. /******************************************************************************
  3647. * Writes a value to a PHY register
  3648. *
  3649. * hw - Struct containing variables accessed by shared code
  3650. * reg_addr - address of the PHY register to write
  3651. * data - data to write to the PHY
  3652. ******************************************************************************/
  3653. static int
  3654. e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
  3655. {
  3656. uint32_t i;
  3657. uint32_t mdic = 0;
  3658. const uint32_t phy_addr = 1;
  3659. if (reg_addr > MAX_PHY_REG_ADDRESS) {
  3660. DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
  3661. return -E1000_ERR_PARAM;
  3662. }
  3663. if (hw->mac_type > e1000_82543) {
  3664. /* Set up Op-code, Phy Address, register address, and data intended
  3665. * for the PHY register in the MDI Control register. The MAC will take
  3666. * care of interfacing with the PHY to send the desired data.
  3667. */
  3668. mdic = (((uint32_t) phy_data) |
  3669. (reg_addr << E1000_MDIC_REG_SHIFT) |
  3670. (phy_addr << E1000_MDIC_PHY_SHIFT) |
  3671. (E1000_MDIC_OP_WRITE));
  3672. E1000_WRITE_REG(hw, MDIC, mdic);
  3673. /* Poll the ready bit to see if the MDI read completed */
  3674. for (i = 0; i < 64; i++) {
  3675. udelay(10);
  3676. mdic = E1000_READ_REG(hw, MDIC);
  3677. if (mdic & E1000_MDIC_READY)
  3678. break;
  3679. }
  3680. if (!(mdic & E1000_MDIC_READY)) {
  3681. DEBUGOUT("MDI Write did not complete\n");
  3682. return -E1000_ERR_PHY;
  3683. }
  3684. } else {
  3685. /* We'll need to use the SW defined pins to shift the write command
  3686. * out to the PHY. We first send a preamble to the PHY to signal the
  3687. * beginning of the MII instruction. This is done by sending 32
  3688. * consecutive "1" bits.
  3689. */
  3690. e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
  3691. /* Now combine the remaining required fields that will indicate a
  3692. * write operation. We use this method instead of calling the
  3693. * e1000_shift_out_mdi_bits routine for each field in the command. The
  3694. * format of a MII write instruction is as follows:
  3695. * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
  3696. */
  3697. mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
  3698. (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
  3699. mdic <<= 16;
  3700. mdic |= (uint32_t) phy_data;
  3701. e1000_shift_out_mdi_bits(hw, mdic, 32);
  3702. }
  3703. return 0;
  3704. }
  3705. /******************************************************************************
  3706. * Checks if PHY reset is blocked due to SOL/IDER session, for example.
  3707. * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
  3708. * the caller to figure out how to deal with it.
  3709. *
  3710. * hw - Struct containing variables accessed by shared code
  3711. *
  3712. * returns: - E1000_BLK_PHY_RESET
  3713. * E1000_SUCCESS
  3714. *
  3715. *****************************************************************************/
  3716. int32_t
  3717. e1000_check_phy_reset_block(struct e1000_hw *hw)
  3718. {
  3719. uint32_t manc = 0;
  3720. uint32_t fwsm = 0;
  3721. if (hw->mac_type == e1000_ich8lan) {
  3722. fwsm = E1000_READ_REG(hw, FWSM);
  3723. return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
  3724. : E1000_BLK_PHY_RESET;
  3725. }
  3726. if (hw->mac_type > e1000_82547_rev_2)
  3727. manc = E1000_READ_REG(hw, MANC);
  3728. return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
  3729. E1000_BLK_PHY_RESET : E1000_SUCCESS;
  3730. }
  3731. /***************************************************************************
  3732. * Checks if the PHY configuration is done
  3733. *
  3734. * hw: Struct containing variables accessed by shared code
  3735. *
  3736. * returns: - E1000_ERR_RESET if fail to reset MAC
  3737. * E1000_SUCCESS at any other case.
  3738. *
  3739. ***************************************************************************/
  3740. static int32_t
  3741. e1000_get_phy_cfg_done(struct e1000_hw *hw)
  3742. {
  3743. int32_t timeout = PHY_CFG_TIMEOUT;
  3744. uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
  3745. DEBUGFUNC();
  3746. switch (hw->mac_type) {
  3747. default:
  3748. mdelay(10);
  3749. break;
  3750. case e1000_80003es2lan:
  3751. /* Separate *_CFG_DONE_* bit for each port */
  3752. if (e1000_is_second_port(hw))
  3753. cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
  3754. /* Fall Through */
  3755. case e1000_82571:
  3756. case e1000_82572:
  3757. while (timeout) {
  3758. if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
  3759. break;
  3760. else
  3761. mdelay(1);
  3762. timeout--;
  3763. }
  3764. if (!timeout) {
  3765. DEBUGOUT("MNG configuration cycle has not "
  3766. "completed.\n");
  3767. return -E1000_ERR_RESET;
  3768. }
  3769. break;
  3770. }
  3771. return E1000_SUCCESS;
  3772. }
  3773. /******************************************************************************
  3774. * Returns the PHY to the power-on reset state
  3775. *
  3776. * hw - Struct containing variables accessed by shared code
  3777. ******************************************************************************/
  3778. int32_t
  3779. e1000_phy_hw_reset(struct e1000_hw *hw)
  3780. {
  3781. uint16_t swfw = E1000_SWFW_PHY0_SM;
  3782. uint32_t ctrl, ctrl_ext;
  3783. uint32_t led_ctrl;
  3784. int32_t ret_val;
  3785. DEBUGFUNC();
  3786. /* In the case of the phy reset being blocked, it's not an error, we
  3787. * simply return success without performing the reset. */
  3788. ret_val = e1000_check_phy_reset_block(hw);
  3789. if (ret_val)
  3790. return E1000_SUCCESS;
  3791. DEBUGOUT("Resetting Phy...\n");
  3792. if (hw->mac_type > e1000_82543) {
  3793. if (e1000_is_second_port(hw))
  3794. swfw = E1000_SWFW_PHY1_SM;
  3795. if (e1000_swfw_sync_acquire(hw, swfw)) {
  3796. DEBUGOUT("Unable to acquire swfw sync\n");
  3797. return -E1000_ERR_SWFW_SYNC;
  3798. }
  3799. /* Read the device control register and assert the E1000_CTRL_PHY_RST
  3800. * bit. Then, take it out of reset.
  3801. */
  3802. ctrl = E1000_READ_REG(hw, CTRL);
  3803. E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
  3804. E1000_WRITE_FLUSH(hw);
  3805. if (hw->mac_type < e1000_82571)
  3806. udelay(10);
  3807. else
  3808. udelay(100);
  3809. E1000_WRITE_REG(hw, CTRL, ctrl);
  3810. E1000_WRITE_FLUSH(hw);
  3811. if (hw->mac_type >= e1000_82571)
  3812. mdelay(10);
  3813. } else {
  3814. /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
  3815. * bit to put the PHY into reset. Then, take it out of reset.
  3816. */
  3817. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  3818. ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
  3819. ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
  3820. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  3821. E1000_WRITE_FLUSH(hw);
  3822. mdelay(10);
  3823. ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
  3824. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  3825. E1000_WRITE_FLUSH(hw);
  3826. }
  3827. udelay(150);
  3828. if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
  3829. /* Configure activity LED after PHY reset */
  3830. led_ctrl = E1000_READ_REG(hw, LEDCTL);
  3831. led_ctrl &= IGP_ACTIVITY_LED_MASK;
  3832. led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
  3833. E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
  3834. }
  3835. /* Wait for FW to finish PHY configuration. */
  3836. ret_val = e1000_get_phy_cfg_done(hw);
  3837. if (ret_val != E1000_SUCCESS)
  3838. return ret_val;
  3839. return ret_val;
  3840. }
  3841. /******************************************************************************
  3842. * IGP phy init script - initializes the GbE PHY
  3843. *
  3844. * hw - Struct containing variables accessed by shared code
  3845. *****************************************************************************/
  3846. static void
  3847. e1000_phy_init_script(struct e1000_hw *hw)
  3848. {
  3849. uint32_t ret_val;
  3850. uint16_t phy_saved_data;
  3851. DEBUGFUNC();
  3852. if (hw->phy_init_script) {
  3853. mdelay(20);
  3854. /* Save off the current value of register 0x2F5B to be
  3855. * restored at the end of this routine. */
  3856. ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
  3857. /* Disabled the PHY transmitter */
  3858. e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
  3859. mdelay(20);
  3860. e1000_write_phy_reg(hw, 0x0000, 0x0140);
  3861. mdelay(5);
  3862. switch (hw->mac_type) {
  3863. case e1000_82541:
  3864. case e1000_82547:
  3865. e1000_write_phy_reg(hw, 0x1F95, 0x0001);
  3866. e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
  3867. e1000_write_phy_reg(hw, 0x1F79, 0x0018);
  3868. e1000_write_phy_reg(hw, 0x1F30, 0x1600);
  3869. e1000_write_phy_reg(hw, 0x1F31, 0x0014);
  3870. e1000_write_phy_reg(hw, 0x1F32, 0x161C);
  3871. e1000_write_phy_reg(hw, 0x1F94, 0x0003);
  3872. e1000_write_phy_reg(hw, 0x1F96, 0x003F);
  3873. e1000_write_phy_reg(hw, 0x2010, 0x0008);
  3874. break;
  3875. case e1000_82541_rev_2:
  3876. case e1000_82547_rev_2:
  3877. e1000_write_phy_reg(hw, 0x1F73, 0x0099);
  3878. break;
  3879. default:
  3880. break;
  3881. }
  3882. e1000_write_phy_reg(hw, 0x0000, 0x3300);
  3883. mdelay(20);
  3884. /* Now enable the transmitter */
  3885. if (!ret_val)
  3886. e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
  3887. if (hw->mac_type == e1000_82547) {
  3888. uint16_t fused, fine, coarse;
  3889. /* Move to analog registers page */
  3890. e1000_read_phy_reg(hw,
  3891. IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
  3892. if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
  3893. e1000_read_phy_reg(hw,
  3894. IGP01E1000_ANALOG_FUSE_STATUS, &fused);
  3895. fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
  3896. coarse = fused
  3897. & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
  3898. if (coarse >
  3899. IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
  3900. coarse -=
  3901. IGP01E1000_ANALOG_FUSE_COARSE_10;
  3902. fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
  3903. } else if (coarse
  3904. == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
  3905. fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
  3906. fused = (fused
  3907. & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
  3908. (fine
  3909. & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
  3910. (coarse
  3911. & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
  3912. e1000_write_phy_reg(hw,
  3913. IGP01E1000_ANALOG_FUSE_CONTROL, fused);
  3914. e1000_write_phy_reg(hw,
  3915. IGP01E1000_ANALOG_FUSE_BYPASS,
  3916. IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
  3917. }
  3918. }
  3919. }
  3920. }
  3921. /******************************************************************************
  3922. * Resets the PHY
  3923. *
  3924. * hw - Struct containing variables accessed by shared code
  3925. *
  3926. * Sets bit 15 of the MII Control register
  3927. ******************************************************************************/
  3928. int32_t
  3929. e1000_phy_reset(struct e1000_hw *hw)
  3930. {
  3931. int32_t ret_val;
  3932. uint16_t phy_data;
  3933. DEBUGFUNC();
  3934. /* In the case of the phy reset being blocked, it's not an error, we
  3935. * simply return success without performing the reset. */
  3936. ret_val = e1000_check_phy_reset_block(hw);
  3937. if (ret_val)
  3938. return E1000_SUCCESS;
  3939. switch (hw->phy_type) {
  3940. case e1000_phy_igp:
  3941. case e1000_phy_igp_2:
  3942. case e1000_phy_igp_3:
  3943. case e1000_phy_ife:
  3944. ret_val = e1000_phy_hw_reset(hw);
  3945. if (ret_val)
  3946. return ret_val;
  3947. break;
  3948. default:
  3949. ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
  3950. if (ret_val)
  3951. return ret_val;
  3952. phy_data |= MII_CR_RESET;
  3953. ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
  3954. if (ret_val)
  3955. return ret_val;
  3956. udelay(1);
  3957. break;
  3958. }
  3959. if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
  3960. e1000_phy_init_script(hw);
  3961. return E1000_SUCCESS;
  3962. }
  3963. static int e1000_set_phy_type (struct e1000_hw *hw)
  3964. {
  3965. DEBUGFUNC ();
  3966. if (hw->mac_type == e1000_undefined)
  3967. return -E1000_ERR_PHY_TYPE;
  3968. switch (hw->phy_id) {
  3969. case M88E1000_E_PHY_ID:
  3970. case M88E1000_I_PHY_ID:
  3971. case M88E1011_I_PHY_ID:
  3972. case M88E1111_I_PHY_ID:
  3973. hw->phy_type = e1000_phy_m88;
  3974. break;
  3975. case IGP01E1000_I_PHY_ID:
  3976. if (hw->mac_type == e1000_82541 ||
  3977. hw->mac_type == e1000_82541_rev_2 ||
  3978. hw->mac_type == e1000_82547 ||
  3979. hw->mac_type == e1000_82547_rev_2) {
  3980. hw->phy_type = e1000_phy_igp;
  3981. hw->phy_type = e1000_phy_igp;
  3982. break;
  3983. }
  3984. case IGP03E1000_E_PHY_ID:
  3985. hw->phy_type = e1000_phy_igp_3;
  3986. break;
  3987. case IFE_E_PHY_ID:
  3988. case IFE_PLUS_E_PHY_ID:
  3989. case IFE_C_E_PHY_ID:
  3990. hw->phy_type = e1000_phy_ife;
  3991. break;
  3992. case GG82563_E_PHY_ID:
  3993. if (hw->mac_type == e1000_80003es2lan) {
  3994. hw->phy_type = e1000_phy_gg82563;
  3995. break;
  3996. }
  3997. case BME1000_E_PHY_ID:
  3998. hw->phy_type = e1000_phy_bm;
  3999. break;
  4000. /* Fall Through */
  4001. default:
  4002. /* Should never have loaded on this device */
  4003. hw->phy_type = e1000_phy_undefined;
  4004. return -E1000_ERR_PHY_TYPE;
  4005. }
  4006. return E1000_SUCCESS;
  4007. }
  4008. /******************************************************************************
  4009. * Probes the expected PHY address for known PHY IDs
  4010. *
  4011. * hw - Struct containing variables accessed by shared code
  4012. ******************************************************************************/
  4013. static int32_t
  4014. e1000_detect_gig_phy(struct e1000_hw *hw)
  4015. {
  4016. int32_t phy_init_status, ret_val;
  4017. uint16_t phy_id_high, phy_id_low;
  4018. bool match = false;
  4019. DEBUGFUNC();
  4020. /* The 82571 firmware may still be configuring the PHY. In this
  4021. * case, we cannot access the PHY until the configuration is done. So
  4022. * we explicitly set the PHY values. */
  4023. if (hw->mac_type == e1000_82571 ||
  4024. hw->mac_type == e1000_82572) {
  4025. hw->phy_id = IGP01E1000_I_PHY_ID;
  4026. hw->phy_type = e1000_phy_igp_2;
  4027. return E1000_SUCCESS;
  4028. }
  4029. /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
  4030. * work- around that forces PHY page 0 to be set or the reads fail.
  4031. * The rest of the code in this routine uses e1000_read_phy_reg to
  4032. * read the PHY ID. So for ESB-2 we need to have this set so our
  4033. * reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
  4034. * the routines below will figure this out as well. */
  4035. if (hw->mac_type == e1000_80003es2lan)
  4036. hw->phy_type = e1000_phy_gg82563;
  4037. /* Read the PHY ID Registers to identify which PHY is onboard. */
  4038. ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
  4039. if (ret_val)
  4040. return ret_val;
  4041. hw->phy_id = (uint32_t) (phy_id_high << 16);
  4042. udelay(20);
  4043. ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
  4044. if (ret_val)
  4045. return ret_val;
  4046. hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
  4047. hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
  4048. switch (hw->mac_type) {
  4049. case e1000_82543:
  4050. if (hw->phy_id == M88E1000_E_PHY_ID)
  4051. match = true;
  4052. break;
  4053. case e1000_82544:
  4054. if (hw->phy_id == M88E1000_I_PHY_ID)
  4055. match = true;
  4056. break;
  4057. case e1000_82540:
  4058. case e1000_82545:
  4059. case e1000_82545_rev_3:
  4060. case e1000_82546:
  4061. case e1000_82546_rev_3:
  4062. if (hw->phy_id == M88E1011_I_PHY_ID)
  4063. match = true;
  4064. break;
  4065. case e1000_82541:
  4066. case e1000_82541_rev_2:
  4067. case e1000_82547:
  4068. case e1000_82547_rev_2:
  4069. if(hw->phy_id == IGP01E1000_I_PHY_ID)
  4070. match = true;
  4071. break;
  4072. case e1000_82573:
  4073. if (hw->phy_id == M88E1111_I_PHY_ID)
  4074. match = true;
  4075. break;
  4076. case e1000_82574:
  4077. if (hw->phy_id == BME1000_E_PHY_ID)
  4078. match = true;
  4079. break;
  4080. case e1000_80003es2lan:
  4081. if (hw->phy_id == GG82563_E_PHY_ID)
  4082. match = true;
  4083. break;
  4084. case e1000_ich8lan:
  4085. if (hw->phy_id == IGP03E1000_E_PHY_ID)
  4086. match = true;
  4087. if (hw->phy_id == IFE_E_PHY_ID)
  4088. match = true;
  4089. if (hw->phy_id == IFE_PLUS_E_PHY_ID)
  4090. match = true;
  4091. if (hw->phy_id == IFE_C_E_PHY_ID)
  4092. match = true;
  4093. break;
  4094. default:
  4095. DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
  4096. return -E1000_ERR_CONFIG;
  4097. }
  4098. phy_init_status = e1000_set_phy_type(hw);
  4099. if ((match) && (phy_init_status == E1000_SUCCESS)) {
  4100. DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
  4101. return 0;
  4102. }
  4103. DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
  4104. return -E1000_ERR_PHY;
  4105. }
  4106. /*****************************************************************************
  4107. * Set media type and TBI compatibility.
  4108. *
  4109. * hw - Struct containing variables accessed by shared code
  4110. * **************************************************************************/
  4111. void
  4112. e1000_set_media_type(struct e1000_hw *hw)
  4113. {
  4114. uint32_t status;
  4115. DEBUGFUNC();
  4116. if (hw->mac_type != e1000_82543) {
  4117. /* tbi_compatibility is only valid on 82543 */
  4118. hw->tbi_compatibility_en = false;
  4119. }
  4120. switch (hw->device_id) {
  4121. case E1000_DEV_ID_82545GM_SERDES:
  4122. case E1000_DEV_ID_82546GB_SERDES:
  4123. case E1000_DEV_ID_82571EB_SERDES:
  4124. case E1000_DEV_ID_82571EB_SERDES_DUAL:
  4125. case E1000_DEV_ID_82571EB_SERDES_QUAD:
  4126. case E1000_DEV_ID_82572EI_SERDES:
  4127. case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
  4128. hw->media_type = e1000_media_type_internal_serdes;
  4129. break;
  4130. default:
  4131. switch (hw->mac_type) {
  4132. case e1000_82542_rev2_0:
  4133. case e1000_82542_rev2_1:
  4134. hw->media_type = e1000_media_type_fiber;
  4135. break;
  4136. case e1000_ich8lan:
  4137. case e1000_82573:
  4138. case e1000_82574:
  4139. /* The STATUS_TBIMODE bit is reserved or reused
  4140. * for the this device.
  4141. */
  4142. hw->media_type = e1000_media_type_copper;
  4143. break;
  4144. default:
  4145. status = E1000_READ_REG(hw, STATUS);
  4146. if (status & E1000_STATUS_TBIMODE) {
  4147. hw->media_type = e1000_media_type_fiber;
  4148. /* tbi_compatibility not valid on fiber */
  4149. hw->tbi_compatibility_en = false;
  4150. } else {
  4151. hw->media_type = e1000_media_type_copper;
  4152. }
  4153. break;
  4154. }
  4155. }
  4156. }
  4157. /**
  4158. * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
  4159. *
  4160. * e1000_sw_init initializes the Adapter private data structure.
  4161. * Fields are initialized based on PCI device information and
  4162. * OS network device settings (MTU size).
  4163. **/
  4164. static int
  4165. e1000_sw_init(struct eth_device *nic)
  4166. {
  4167. struct e1000_hw *hw = (typeof(hw)) nic->priv;
  4168. int result;
  4169. /* PCI config space info */
  4170. pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
  4171. pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
  4172. pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
  4173. &hw->subsystem_vendor_id);
  4174. pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
  4175. pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
  4176. pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
  4177. /* identify the MAC */
  4178. result = e1000_set_mac_type(hw);
  4179. if (result) {
  4180. E1000_ERR(hw->nic, "Unknown MAC Type\n");
  4181. return result;
  4182. }
  4183. switch (hw->mac_type) {
  4184. default:
  4185. break;
  4186. case e1000_82541:
  4187. case e1000_82547:
  4188. case e1000_82541_rev_2:
  4189. case e1000_82547_rev_2:
  4190. hw->phy_init_script = 1;
  4191. break;
  4192. }
  4193. /* flow control settings */
  4194. hw->fc_high_water = E1000_FC_HIGH_THRESH;
  4195. hw->fc_low_water = E1000_FC_LOW_THRESH;
  4196. hw->fc_pause_time = E1000_FC_PAUSE_TIME;
  4197. hw->fc_send_xon = 1;
  4198. /* Media type - copper or fiber */
  4199. e1000_set_media_type(hw);
  4200. if (hw->mac_type >= e1000_82543) {
  4201. uint32_t status = E1000_READ_REG(hw, STATUS);
  4202. if (status & E1000_STATUS_TBIMODE) {
  4203. DEBUGOUT("fiber interface\n");
  4204. hw->media_type = e1000_media_type_fiber;
  4205. } else {
  4206. DEBUGOUT("copper interface\n");
  4207. hw->media_type = e1000_media_type_copper;
  4208. }
  4209. } else {
  4210. hw->media_type = e1000_media_type_fiber;
  4211. }
  4212. hw->tbi_compatibility_en = true;
  4213. hw->wait_autoneg_complete = true;
  4214. if (hw->mac_type < e1000_82543)
  4215. hw->report_tx_early = 0;
  4216. else
  4217. hw->report_tx_early = 1;
  4218. return E1000_SUCCESS;
  4219. }
  4220. void
  4221. fill_rx(struct e1000_hw *hw)
  4222. {
  4223. struct e1000_rx_desc *rd;
  4224. rx_last = rx_tail;
  4225. rd = rx_base + rx_tail;
  4226. rx_tail = (rx_tail + 1) % 8;
  4227. memset(rd, 0, 16);
  4228. rd->buffer_addr = cpu_to_le64((u32) & packet);
  4229. E1000_WRITE_REG(hw, RDT, rx_tail);
  4230. }
  4231. /**
  4232. * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
  4233. * @adapter: board private structure
  4234. *
  4235. * Configure the Tx unit of the MAC after a reset.
  4236. **/
  4237. static void
  4238. e1000_configure_tx(struct e1000_hw *hw)
  4239. {
  4240. unsigned long ptr;
  4241. unsigned long tctl;
  4242. unsigned long tipg, tarc;
  4243. uint32_t ipgr1, ipgr2;
  4244. ptr = (u32) tx_pool;
  4245. if (ptr & 0xf)
  4246. ptr = (ptr + 0x10) & (~0xf);
  4247. tx_base = (typeof(tx_base)) ptr;
  4248. E1000_WRITE_REG(hw, TDBAL, (u32) tx_base);
  4249. E1000_WRITE_REG(hw, TDBAH, 0);
  4250. E1000_WRITE_REG(hw, TDLEN, 128);
  4251. /* Setup the HW Tx Head and Tail descriptor pointers */
  4252. E1000_WRITE_REG(hw, TDH, 0);
  4253. E1000_WRITE_REG(hw, TDT, 0);
  4254. tx_tail = 0;
  4255. /* Set the default values for the Tx Inter Packet Gap timer */
  4256. if (hw->mac_type <= e1000_82547_rev_2 &&
  4257. (hw->media_type == e1000_media_type_fiber ||
  4258. hw->media_type == e1000_media_type_internal_serdes))
  4259. tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
  4260. else
  4261. tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
  4262. /* Set the default values for the Tx Inter Packet Gap timer */
  4263. switch (hw->mac_type) {
  4264. case e1000_82542_rev2_0:
  4265. case e1000_82542_rev2_1:
  4266. tipg = DEFAULT_82542_TIPG_IPGT;
  4267. ipgr1 = DEFAULT_82542_TIPG_IPGR1;
  4268. ipgr2 = DEFAULT_82542_TIPG_IPGR2;
  4269. break;
  4270. case e1000_80003es2lan:
  4271. ipgr1 = DEFAULT_82543_TIPG_IPGR1;
  4272. ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
  4273. break;
  4274. default:
  4275. ipgr1 = DEFAULT_82543_TIPG_IPGR1;
  4276. ipgr2 = DEFAULT_82543_TIPG_IPGR2;
  4277. break;
  4278. }
  4279. tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
  4280. tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
  4281. E1000_WRITE_REG(hw, TIPG, tipg);
  4282. /* Program the Transmit Control Register */
  4283. tctl = E1000_READ_REG(hw, TCTL);
  4284. tctl &= ~E1000_TCTL_CT;
  4285. tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
  4286. (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
  4287. if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
  4288. tarc = E1000_READ_REG(hw, TARC0);
  4289. /* set the speed mode bit, we'll clear it if we're not at
  4290. * gigabit link later */
  4291. /* git bit can be set to 1*/
  4292. } else if (hw->mac_type == e1000_80003es2lan) {
  4293. tarc = E1000_READ_REG(hw, TARC0);
  4294. tarc |= 1;
  4295. E1000_WRITE_REG(hw, TARC0, tarc);
  4296. tarc = E1000_READ_REG(hw, TARC1);
  4297. tarc |= 1;
  4298. E1000_WRITE_REG(hw, TARC1, tarc);
  4299. }
  4300. e1000_config_collision_dist(hw);
  4301. /* Setup Transmit Descriptor Settings for eop descriptor */
  4302. hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
  4303. /* Need to set up RS bit */
  4304. if (hw->mac_type < e1000_82543)
  4305. hw->txd_cmd |= E1000_TXD_CMD_RPS;
  4306. else
  4307. hw->txd_cmd |= E1000_TXD_CMD_RS;
  4308. E1000_WRITE_REG(hw, TCTL, tctl);
  4309. }
  4310. /**
  4311. * e1000_setup_rctl - configure the receive control register
  4312. * @adapter: Board private structure
  4313. **/
  4314. static void
  4315. e1000_setup_rctl(struct e1000_hw *hw)
  4316. {
  4317. uint32_t rctl;
  4318. rctl = E1000_READ_REG(hw, RCTL);
  4319. rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
  4320. rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
  4321. | E1000_RCTL_RDMTS_HALF; /* |
  4322. (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
  4323. if (hw->tbi_compatibility_on == 1)
  4324. rctl |= E1000_RCTL_SBP;
  4325. else
  4326. rctl &= ~E1000_RCTL_SBP;
  4327. rctl &= ~(E1000_RCTL_SZ_4096);
  4328. rctl |= E1000_RCTL_SZ_2048;
  4329. rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
  4330. E1000_WRITE_REG(hw, RCTL, rctl);
  4331. }
  4332. /**
  4333. * e1000_configure_rx - Configure 8254x Receive Unit after Reset
  4334. * @adapter: board private structure
  4335. *
  4336. * Configure the Rx unit of the MAC after a reset.
  4337. **/
  4338. static void
  4339. e1000_configure_rx(struct e1000_hw *hw)
  4340. {
  4341. unsigned long ptr;
  4342. unsigned long rctl, ctrl_ext;
  4343. rx_tail = 0;
  4344. /* make sure receives are disabled while setting up the descriptors */
  4345. rctl = E1000_READ_REG(hw, RCTL);
  4346. E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
  4347. if (hw->mac_type >= e1000_82540) {
  4348. /* Set the interrupt throttling rate. Value is calculated
  4349. * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
  4350. #define MAX_INTS_PER_SEC 8000
  4351. #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
  4352. E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
  4353. }
  4354. if (hw->mac_type >= e1000_82571) {
  4355. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  4356. /* Reset delay timers after every interrupt */
  4357. ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
  4358. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  4359. E1000_WRITE_FLUSH(hw);
  4360. }
  4361. /* Setup the Base and Length of the Rx Descriptor Ring */
  4362. ptr = (u32) rx_pool;
  4363. if (ptr & 0xf)
  4364. ptr = (ptr + 0x10) & (~0xf);
  4365. rx_base = (typeof(rx_base)) ptr;
  4366. E1000_WRITE_REG(hw, RDBAL, (u32) rx_base);
  4367. E1000_WRITE_REG(hw, RDBAH, 0);
  4368. E1000_WRITE_REG(hw, RDLEN, 128);
  4369. /* Setup the HW Rx Head and Tail Descriptor Pointers */
  4370. E1000_WRITE_REG(hw, RDH, 0);
  4371. E1000_WRITE_REG(hw, RDT, 0);
  4372. /* Enable Receives */
  4373. E1000_WRITE_REG(hw, RCTL, rctl);
  4374. fill_rx(hw);
  4375. }
  4376. /**************************************************************************
  4377. POLL - Wait for a frame
  4378. ***************************************************************************/
  4379. static int
  4380. e1000_poll(struct eth_device *nic)
  4381. {
  4382. struct e1000_hw *hw = nic->priv;
  4383. struct e1000_rx_desc *rd;
  4384. /* return true if there's an ethernet packet ready to read */
  4385. rd = rx_base + rx_last;
  4386. if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
  4387. return 0;
  4388. /*DEBUGOUT("recv: packet len=%d \n", rd->length); */
  4389. NetReceive((uchar *)packet, le32_to_cpu(rd->length));
  4390. fill_rx(hw);
  4391. return 1;
  4392. }
  4393. /**************************************************************************
  4394. TRANSMIT - Transmit a frame
  4395. ***************************************************************************/
  4396. static int e1000_transmit(struct eth_device *nic, void *packet, int length)
  4397. {
  4398. void *nv_packet = (void *)packet;
  4399. struct e1000_hw *hw = nic->priv;
  4400. struct e1000_tx_desc *txp;
  4401. int i = 0;
  4402. txp = tx_base + tx_tail;
  4403. tx_tail = (tx_tail + 1) % 8;
  4404. txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
  4405. txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
  4406. txp->upper.data = 0;
  4407. E1000_WRITE_REG(hw, TDT, tx_tail);
  4408. E1000_WRITE_FLUSH(hw);
  4409. while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) {
  4410. if (i++ > TOUT_LOOP) {
  4411. DEBUGOUT("e1000: tx timeout\n");
  4412. return 0;
  4413. }
  4414. udelay(10); /* give the nic a chance to write to the register */
  4415. }
  4416. return 1;
  4417. }
  4418. /*reset function*/
  4419. static inline int
  4420. e1000_reset(struct eth_device *nic)
  4421. {
  4422. struct e1000_hw *hw = nic->priv;
  4423. e1000_reset_hw(hw);
  4424. if (hw->mac_type >= e1000_82544) {
  4425. E1000_WRITE_REG(hw, WUC, 0);
  4426. }
  4427. return e1000_init_hw(nic);
  4428. }
  4429. /**************************************************************************
  4430. DISABLE - Turn off ethernet interface
  4431. ***************************************************************************/
  4432. static void
  4433. e1000_disable(struct eth_device *nic)
  4434. {
  4435. struct e1000_hw *hw = nic->priv;
  4436. /* Turn off the ethernet interface */
  4437. E1000_WRITE_REG(hw, RCTL, 0);
  4438. E1000_WRITE_REG(hw, TCTL, 0);
  4439. /* Clear the transmit ring */
  4440. E1000_WRITE_REG(hw, TDH, 0);
  4441. E1000_WRITE_REG(hw, TDT, 0);
  4442. /* Clear the receive ring */
  4443. E1000_WRITE_REG(hw, RDH, 0);
  4444. E1000_WRITE_REG(hw, RDT, 0);
  4445. /* put the card in its initial state */
  4446. #if 0
  4447. E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
  4448. #endif
  4449. mdelay(10);
  4450. }
  4451. /**************************************************************************
  4452. INIT - set up ethernet interface(s)
  4453. ***************************************************************************/
  4454. static int
  4455. e1000_init(struct eth_device *nic, bd_t * bis)
  4456. {
  4457. struct e1000_hw *hw = nic->priv;
  4458. int ret_val = 0;
  4459. ret_val = e1000_reset(nic);
  4460. if (ret_val < 0) {
  4461. if ((ret_val == -E1000_ERR_NOLINK) ||
  4462. (ret_val == -E1000_ERR_TIMEOUT)) {
  4463. E1000_ERR(hw->nic, "Valid Link not detected\n");
  4464. } else {
  4465. E1000_ERR(hw->nic, "Hardware Initialization Failed\n");
  4466. }
  4467. return 0;
  4468. }
  4469. e1000_configure_tx(hw);
  4470. e1000_setup_rctl(hw);
  4471. e1000_configure_rx(hw);
  4472. return 1;
  4473. }
  4474. /******************************************************************************
  4475. * Gets the current PCI bus type of hardware
  4476. *
  4477. * hw - Struct containing variables accessed by shared code
  4478. *****************************************************************************/
  4479. void e1000_get_bus_type(struct e1000_hw *hw)
  4480. {
  4481. uint32_t status;
  4482. switch (hw->mac_type) {
  4483. case e1000_82542_rev2_0:
  4484. case e1000_82542_rev2_1:
  4485. hw->bus_type = e1000_bus_type_pci;
  4486. break;
  4487. case e1000_82571:
  4488. case e1000_82572:
  4489. case e1000_82573:
  4490. case e1000_82574:
  4491. case e1000_80003es2lan:
  4492. hw->bus_type = e1000_bus_type_pci_express;
  4493. break;
  4494. case e1000_ich8lan:
  4495. hw->bus_type = e1000_bus_type_pci_express;
  4496. break;
  4497. default:
  4498. status = E1000_READ_REG(hw, STATUS);
  4499. hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
  4500. e1000_bus_type_pcix : e1000_bus_type_pci;
  4501. break;
  4502. }
  4503. }
  4504. /* A list of all registered e1000 devices */
  4505. static LIST_HEAD(e1000_hw_list);
  4506. /**************************************************************************
  4507. PROBE - Look for an adapter, this routine's visible to the outside
  4508. You should omit the last argument struct pci_device * for a non-PCI NIC
  4509. ***************************************************************************/
  4510. int
  4511. e1000_initialize(bd_t * bis)
  4512. {
  4513. unsigned int i;
  4514. pci_dev_t devno;
  4515. DEBUGFUNC();
  4516. /* Find and probe all the matching PCI devices */
  4517. for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
  4518. u32 val;
  4519. /*
  4520. * These will never get freed due to errors, this allows us to
  4521. * perform SPI EEPROM programming from U-boot, for example.
  4522. */
  4523. struct eth_device *nic = malloc(sizeof(*nic));
  4524. struct e1000_hw *hw = malloc(sizeof(*hw));
  4525. if (!nic || !hw) {
  4526. printf("e1000#%u: Out of Memory!\n", i);
  4527. free(nic);
  4528. free(hw);
  4529. continue;
  4530. }
  4531. /* Make sure all of the fields are initially zeroed */
  4532. memset(nic, 0, sizeof(*nic));
  4533. memset(hw, 0, sizeof(*hw));
  4534. /* Assign the passed-in values */
  4535. hw->cardnum = i;
  4536. hw->pdev = devno;
  4537. hw->nic = nic;
  4538. nic->priv = hw;
  4539. /* Generate a card name */
  4540. sprintf(nic->name, "e1000#%u", hw->cardnum);
  4541. /* Print a debug message with the IO base address */
  4542. pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
  4543. E1000_DBG(nic, "iobase 0x%08x\n", val & 0xfffffff0);
  4544. /* Try to enable I/O accesses and bus-mastering */
  4545. val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  4546. pci_write_config_dword(devno, PCI_COMMAND, val);
  4547. /* Make sure it worked */
  4548. pci_read_config_dword(devno, PCI_COMMAND, &val);
  4549. if (!(val & PCI_COMMAND_MEMORY)) {
  4550. E1000_ERR(nic, "Can't enable I/O memory\n");
  4551. continue;
  4552. }
  4553. if (!(val & PCI_COMMAND_MASTER)) {
  4554. E1000_ERR(nic, "Can't enable bus-mastering\n");
  4555. continue;
  4556. }
  4557. /* Are these variables needed? */
  4558. hw->fc = e1000_fc_default;
  4559. hw->original_fc = e1000_fc_default;
  4560. hw->autoneg_failed = 0;
  4561. hw->autoneg = 1;
  4562. hw->get_link_status = true;
  4563. hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
  4564. PCI_REGION_MEM);
  4565. hw->mac_type = e1000_undefined;
  4566. /* MAC and Phy settings */
  4567. if (e1000_sw_init(nic) < 0) {
  4568. E1000_ERR(nic, "Software init failed\n");
  4569. continue;
  4570. }
  4571. if (e1000_check_phy_reset_block(hw))
  4572. E1000_ERR(nic, "PHY Reset is blocked!\n");
  4573. /* Basic init was OK, reset the hardware and allow SPI access */
  4574. e1000_reset_hw(hw);
  4575. list_add_tail(&hw->list_node, &e1000_hw_list);
  4576. /* Validate the EEPROM and get chipset information */
  4577. #if !defined(CONFIG_MVBC_1G)
  4578. if (e1000_init_eeprom_params(hw)) {
  4579. E1000_ERR(nic, "EEPROM is invalid!\n");
  4580. continue;
  4581. }
  4582. if (e1000_validate_eeprom_checksum(hw))
  4583. continue;
  4584. #endif
  4585. e1000_read_mac_addr(nic);
  4586. e1000_get_bus_type(hw);
  4587. printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ",
  4588. nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
  4589. nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
  4590. /* Set up the function pointers and register the device */
  4591. nic->init = e1000_init;
  4592. nic->recv = e1000_poll;
  4593. nic->send = e1000_transmit;
  4594. nic->halt = e1000_disable;
  4595. eth_register(nic);
  4596. }
  4597. return i;
  4598. }
  4599. struct e1000_hw *e1000_find_card(unsigned int cardnum)
  4600. {
  4601. struct e1000_hw *hw;
  4602. list_for_each_entry(hw, &e1000_hw_list, list_node)
  4603. if (hw->cardnum == cardnum)
  4604. return hw;
  4605. return NULL;
  4606. }
  4607. #ifdef CONFIG_CMD_E1000
  4608. static int do_e1000(cmd_tbl_t *cmdtp, int flag,
  4609. int argc, char * const argv[])
  4610. {
  4611. struct e1000_hw *hw;
  4612. if (argc < 3) {
  4613. cmd_usage(cmdtp);
  4614. return 1;
  4615. }
  4616. /* Make sure we can find the requested e1000 card */
  4617. hw = e1000_find_card(simple_strtoul(argv[1], NULL, 10));
  4618. if (!hw) {
  4619. printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
  4620. return 1;
  4621. }
  4622. if (!strcmp(argv[2], "print-mac-address")) {
  4623. unsigned char *mac = hw->nic->enetaddr;
  4624. printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
  4625. mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
  4626. return 0;
  4627. }
  4628. #ifdef CONFIG_E1000_SPI
  4629. /* Handle the "SPI" subcommand */
  4630. if (!strcmp(argv[2], "spi"))
  4631. return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
  4632. #endif
  4633. cmd_usage(cmdtp);
  4634. return 1;
  4635. }
  4636. U_BOOT_CMD(
  4637. e1000, 7, 0, do_e1000,
  4638. "Intel e1000 controller management",
  4639. /* */"<card#> print-mac-address\n"
  4640. #ifdef CONFIG_E1000_SPI
  4641. "e1000 <card#> spi show [<offset> [<length>]]\n"
  4642. "e1000 <card#> spi dump <addr> <offset> <length>\n"
  4643. "e1000 <card#> spi program <addr> <offset> <length>\n"
  4644. "e1000 <card#> spi checksum [update]\n"
  4645. #endif
  4646. " - Manage the Intel E1000 PCI device"
  4647. );
  4648. #endif /* not CONFIG_CMD_E1000 */