virtex2.c 12 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  4. * Keith Outwater, keith_outwater@mvis.com
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. *
  24. */
  25. /*
  26. * Configuration support for Xilinx Virtex2 devices. Based
  27. * on spartan2.c (Rich Ireland, rireland@enterasys.com).
  28. */
  29. #include <common.h>
  30. #include <virtex2.h>
  31. #if 0
  32. #define FPGA_DEBUG
  33. #endif
  34. #ifdef FPGA_DEBUG
  35. #define PRINTF(fmt,args...) printf (fmt ,##args)
  36. #else
  37. #define PRINTF(fmt,args...)
  38. #endif
  39. /*
  40. * If the SelectMap interface can be overrun by the processor, define
  41. * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board configuration
  42. * file and add board-specific support for checking BUSY status. By default,
  43. * assume that the SelectMap interface cannot be overrun.
  44. */
  45. #ifndef CONFIG_SYS_FPGA_CHECK_BUSY
  46. #undef CONFIG_SYS_FPGA_CHECK_BUSY
  47. #endif
  48. #ifndef CONFIG_FPGA_DELAY
  49. #define CONFIG_FPGA_DELAY()
  50. #endif
  51. #ifndef CONFIG_SYS_FPGA_PROG_FEEDBACK
  52. #define CONFIG_SYS_FPGA_PROG_FEEDBACK
  53. #endif
  54. /*
  55. * Don't allow config cycle to be interrupted
  56. */
  57. #ifndef CONFIG_SYS_FPGA_CHECK_CTRLC
  58. #undef CONFIG_SYS_FPGA_CHECK_CTRLC
  59. #endif
  60. /*
  61. * Check for errors during configuration by default
  62. */
  63. #ifndef CONFIG_SYS_FPGA_CHECK_ERROR
  64. #define CONFIG_SYS_FPGA_CHECK_ERROR
  65. #endif
  66. /*
  67. * The default timeout in mS for INIT_B to deassert after PROG_B has
  68. * been deasserted. Per the latest Virtex II Handbook (page 347), the
  69. * max time from PORG_B deassertion to INIT_B deassertion is 4uS per
  70. * data frame for the XC2V8000. The XC2V8000 has 2860 data frames
  71. * which yields 11.44 mS. So let's make it bigger in order to handle
  72. * an XC2V1000, if anyone can ever get ahold of one.
  73. */
  74. #ifndef CONFIG_SYS_FPGA_WAIT_INIT
  75. #define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ/2 /* 500 ms */
  76. #endif
  77. /*
  78. * The default timeout for waiting for BUSY to deassert during configuration.
  79. * This is normally not necessary since for most reasonable configuration
  80. * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
  81. */
  82. #ifndef CONFIG_SYS_FPGA_WAIT_BUSY
  83. #define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ/200 /* 5 ms*/
  84. #endif
  85. /* Default timeout for waiting for FPGA to enter operational mode after
  86. * configuration data has been written.
  87. */
  88. #ifndef CONFIG_SYS_FPGA_WAIT_CONFIG
  89. #define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */
  90. #endif
  91. static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize);
  92. static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
  93. static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
  94. static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
  95. int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
  96. {
  97. int ret_val = FPGA_FAIL;
  98. switch (desc->iface) {
  99. case slave_serial:
  100. PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
  101. ret_val = Virtex2_ss_load (desc, buf, bsize);
  102. break;
  103. case slave_selectmap:
  104. PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
  105. ret_val = Virtex2_ssm_load (desc, buf, bsize);
  106. break;
  107. default:
  108. printf ("%s: Unsupported interface type, %d\n",
  109. __FUNCTION__, desc->iface);
  110. }
  111. return ret_val;
  112. }
  113. int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
  114. {
  115. int ret_val = FPGA_FAIL;
  116. switch (desc->iface) {
  117. case slave_serial:
  118. PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
  119. ret_val = Virtex2_ss_dump (desc, buf, bsize);
  120. break;
  121. case slave_parallel:
  122. PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
  123. ret_val = Virtex2_ssm_dump (desc, buf, bsize);
  124. break;
  125. default:
  126. printf ("%s: Unsupported interface type, %d\n",
  127. __FUNCTION__, desc->iface);
  128. }
  129. return ret_val;
  130. }
  131. int Virtex2_info (Xilinx_desc * desc)
  132. {
  133. return FPGA_SUCCESS;
  134. }
  135. /*
  136. * Virtex-II Slave SelectMap configuration loader. Configuration via
  137. * SelectMap is as follows:
  138. * 1. Set the FPGA's PROG_B line low.
  139. * 2. Set the FPGA's PROG_B line high. Wait for INIT_B to go high.
  140. * 3. Write data to the SelectMap port. If INIT_B goes low at any time
  141. * this process, a configuration error (most likely CRC failure) has
  142. * ocurred. At this point a status word may be read from the
  143. * SelectMap interface to determine the source of the problem (You
  144. * could, for instance, put this in your 'abort' function handler).
  145. * 4. After all data has been written, test the state of the FPGA
  146. * INIT_B and DONE lines. If both are high, configuration has
  147. * succeeded. Congratulations!
  148. */
  149. static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
  150. {
  151. int ret_val = FPGA_FAIL;
  152. Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
  153. PRINTF ("%s:%d: Start with interface functions @ 0x%p\n",
  154. __FUNCTION__, __LINE__, fn);
  155. if (fn) {
  156. size_t bytecount = 0;
  157. unsigned char *data = (unsigned char *) buf;
  158. int cookie = desc->cookie;
  159. unsigned long ts;
  160. /* Gotta split this one up (so the stack won't blow??) */
  161. PRINTF ("%s:%d: Function Table:\n"
  162. " base 0x%p\n"
  163. " struct 0x%p\n"
  164. " pre 0x%p\n"
  165. " prog 0x%p\n"
  166. " init 0x%p\n"
  167. " error 0x%p\n",
  168. __FUNCTION__, __LINE__,
  169. &fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
  170. PRINTF (" clock 0x%p\n"
  171. " cs 0x%p\n"
  172. " write 0x%p\n"
  173. " rdata 0x%p\n"
  174. " wdata 0x%p\n"
  175. " busy 0x%p\n"
  176. " abort 0x%p\n"
  177. " post 0x%p\n\n",
  178. fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
  179. fn->busy, fn->abort, fn->post);
  180. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  181. printf ("Initializing FPGA Device %d...\n", cookie);
  182. #endif
  183. /*
  184. * Run the pre configuration function if there is one.
  185. */
  186. if (*fn->pre) {
  187. (*fn->pre) (cookie);
  188. }
  189. /*
  190. * Assert the program line. The minimum pulse width for
  191. * Virtex II devices is 300 nS (Tprogram parameter in datasheet).
  192. * There is no maximum value for the pulse width. Check to make
  193. * sure that INIT_B goes low after assertion of PROG_B
  194. */
  195. (*fn->pgm) (true, true, cookie);
  196. udelay (10);
  197. ts = get_timer (0);
  198. do {
  199. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
  200. printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
  201. " to assert.\n", __FUNCTION__, __LINE__,
  202. CONFIG_SYS_FPGA_WAIT_INIT);
  203. (*fn->abort) (cookie);
  204. return FPGA_FAIL;
  205. }
  206. } while (!(*fn->init) (cookie));
  207. (*fn->pgm) (false, true, cookie);
  208. CONFIG_FPGA_DELAY ();
  209. (*fn->clk) (true, true, cookie);
  210. /*
  211. * Start a timer and wait for INIT_B to go high
  212. */
  213. ts = get_timer (0);
  214. do {
  215. CONFIG_FPGA_DELAY ();
  216. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
  217. printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
  218. " to deassert.\n", __FUNCTION__, __LINE__,
  219. CONFIG_SYS_FPGA_WAIT_INIT);
  220. (*fn->abort) (cookie);
  221. return FPGA_FAIL;
  222. }
  223. } while ((*fn->init) (cookie) && (*fn->busy) (cookie));
  224. (*fn->wr) (true, true, cookie);
  225. (*fn->cs) (true, true, cookie);
  226. udelay (10000);
  227. /*
  228. * Load the data byte by byte
  229. */
  230. while (bytecount < bsize) {
  231. #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
  232. if (ctrlc ()) {
  233. (*fn->abort) (cookie);
  234. return FPGA_FAIL;
  235. }
  236. #endif
  237. if ((*fn->done) (cookie) == FPGA_SUCCESS) {
  238. PRINTF ("%s:%d:done went active early, bytecount = %d\n",
  239. __FUNCTION__, __LINE__, bytecount);
  240. break;
  241. }
  242. #ifdef CONFIG_SYS_FPGA_CHECK_ERROR
  243. if ((*fn->init) (cookie)) {
  244. printf ("\n%s:%d: ** Error: INIT asserted during"
  245. " configuration\n", __FUNCTION__, __LINE__);
  246. printf ("%d = buffer offset, %d = buffer size\n",
  247. bytecount, bsize);
  248. (*fn->abort) (cookie);
  249. return FPGA_FAIL;
  250. }
  251. #endif
  252. (*fn->wdata) (data[bytecount++], true, cookie);
  253. CONFIG_FPGA_DELAY ();
  254. /*
  255. * Cycle the clock pin
  256. */
  257. (*fn->clk) (false, true, cookie);
  258. CONFIG_FPGA_DELAY ();
  259. (*fn->clk) (true, true, cookie);
  260. #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
  261. ts = get_timer (0);
  262. while ((*fn->busy) (cookie)) {
  263. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
  264. printf ("%s:%d: ** Timeout after %d ticks waiting for"
  265. " BUSY to deassert\n",
  266. __FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_BUSY);
  267. (*fn->abort) (cookie);
  268. return FPGA_FAIL;
  269. }
  270. }
  271. #endif
  272. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  273. if (bytecount % (bsize / 40) == 0)
  274. putc ('.');
  275. #endif
  276. }
  277. /*
  278. * Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
  279. */
  280. CONFIG_FPGA_DELAY ();
  281. (*fn->cs) (false, true, cookie);
  282. (*fn->wr) (false, true, cookie);
  283. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  284. putc ('\n');
  285. #endif
  286. /*
  287. * Check for successful configuration. FPGA INIT_B and DONE should
  288. * both be high upon successful configuration.
  289. */
  290. ts = get_timer (0);
  291. ret_val = FPGA_SUCCESS;
  292. while (((*fn->done) (cookie) == FPGA_FAIL) || (*fn->init) (cookie)) {
  293. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
  294. printf ("%s:%d: ** Timeout after %d ticks waiting for DONE to"
  295. "assert and INIT to deassert\n",
  296. __FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG);
  297. (*fn->abort) (cookie);
  298. ret_val = FPGA_FAIL;
  299. break;
  300. }
  301. }
  302. if (ret_val == FPGA_SUCCESS) {
  303. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  304. printf ("Initialization of FPGA device %d complete\n", cookie);
  305. #endif
  306. /*
  307. * Run the post configuration function if there is one.
  308. */
  309. if (*fn->post) {
  310. (*fn->post) (cookie);
  311. }
  312. } else {
  313. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  314. printf ("** Initialization of FPGA device %d FAILED\n",
  315. cookie);
  316. #endif
  317. }
  318. } else {
  319. printf ("%s:%d: NULL Interface function table!\n",
  320. __FUNCTION__, __LINE__);
  321. }
  322. return ret_val;
  323. }
  324. /*
  325. * Read the FPGA configuration data
  326. */
  327. static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
  328. {
  329. int ret_val = FPGA_FAIL;
  330. Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
  331. if (fn) {
  332. unsigned char *data = (unsigned char *) buf;
  333. size_t bytecount = 0;
  334. int cookie = desc->cookie;
  335. printf ("Starting Dump of FPGA Device %d...\n", cookie);
  336. (*fn->cs) (true, true, cookie);
  337. (*fn->clk) (true, true, cookie);
  338. while (bytecount < bsize) {
  339. #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
  340. if (ctrlc ()) {
  341. (*fn->abort) (cookie);
  342. return FPGA_FAIL;
  343. }
  344. #endif
  345. /*
  346. * Cycle the clock and read the data
  347. */
  348. (*fn->clk) (false, true, cookie);
  349. (*fn->clk) (true, true, cookie);
  350. (*fn->rdata) (&(data[bytecount++]), cookie);
  351. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  352. if (bytecount % (bsize / 40) == 0)
  353. putc ('.');
  354. #endif
  355. }
  356. /*
  357. * Deassert CS_B and cycle the clock to deselect the device.
  358. */
  359. (*fn->cs) (false, false, cookie);
  360. (*fn->clk) (false, true, cookie);
  361. (*fn->clk) (true, true, cookie);
  362. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  363. putc ('\n');
  364. #endif
  365. puts ("Done.\n");
  366. } else {
  367. printf ("%s:%d: NULL Interface function table!\n",
  368. __FUNCTION__, __LINE__);
  369. }
  370. return ret_val;
  371. }
  372. static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
  373. {
  374. printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__);
  375. return FPGA_FAIL;
  376. }
  377. static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
  378. {
  379. printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__);
  380. return FPGA_FAIL;
  381. }
  382. /* vim: set ts=4 tw=78: */