spartan2.c 13 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. */
  24. #include <common.h> /* core U-Boot definitions */
  25. #include <spartan2.h> /* Spartan-II device family */
  26. /* Define FPGA_DEBUG to get debug printf's */
  27. #ifdef FPGA_DEBUG
  28. #define PRINTF(fmt,args...) printf (fmt ,##args)
  29. #else
  30. #define PRINTF(fmt,args...)
  31. #endif
  32. #undef CONFIG_SYS_FPGA_CHECK_BUSY
  33. #undef CONFIG_SYS_FPGA_PROG_FEEDBACK
  34. /* Note: The assumption is that we cannot possibly run fast enough to
  35. * overrun the device (the Slave Parallel mode can free run at 50MHz).
  36. * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
  37. * the board config file to slow things down.
  38. */
  39. #ifndef CONFIG_FPGA_DELAY
  40. #define CONFIG_FPGA_DELAY()
  41. #endif
  42. #ifndef CONFIG_SYS_FPGA_WAIT
  43. #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
  44. #endif
  45. static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize);
  46. static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
  47. /* static int Spartan2_sp_info(Xilinx_desc *desc ); */
  48. static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
  49. static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
  50. /* static int Spartan2_ss_info(Xilinx_desc *desc ); */
  51. /* ------------------------------------------------------------------------- */
  52. /* Spartan-II Generic Implementation */
  53. int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
  54. {
  55. int ret_val = FPGA_FAIL;
  56. switch (desc->iface) {
  57. case slave_serial:
  58. PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
  59. ret_val = Spartan2_ss_load (desc, buf, bsize);
  60. break;
  61. case slave_parallel:
  62. PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
  63. ret_val = Spartan2_sp_load (desc, buf, bsize);
  64. break;
  65. default:
  66. printf ("%s: Unsupported interface type, %d\n",
  67. __FUNCTION__, desc->iface);
  68. }
  69. return ret_val;
  70. }
  71. int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
  72. {
  73. int ret_val = FPGA_FAIL;
  74. switch (desc->iface) {
  75. case slave_serial:
  76. PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
  77. ret_val = Spartan2_ss_dump (desc, buf, bsize);
  78. break;
  79. case slave_parallel:
  80. PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
  81. ret_val = Spartan2_sp_dump (desc, buf, bsize);
  82. break;
  83. default:
  84. printf ("%s: Unsupported interface type, %d\n",
  85. __FUNCTION__, desc->iface);
  86. }
  87. return ret_val;
  88. }
  89. int Spartan2_info( Xilinx_desc *desc )
  90. {
  91. return FPGA_SUCCESS;
  92. }
  93. /* ------------------------------------------------------------------------- */
  94. /* Spartan-II Slave Parallel Generic Implementation */
  95. static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
  96. {
  97. int ret_val = FPGA_FAIL; /* assume the worst */
  98. Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns;
  99. PRINTF ("%s: start with interface functions @ 0x%p\n",
  100. __FUNCTION__, fn);
  101. if (fn) {
  102. size_t bytecount = 0;
  103. unsigned char *data = (unsigned char *) buf;
  104. int cookie = desc->cookie; /* make a local copy */
  105. unsigned long ts; /* timestamp */
  106. PRINTF ("%s: Function Table:\n"
  107. "ptr:\t0x%p\n"
  108. "struct: 0x%p\n"
  109. "pre: 0x%p\n"
  110. "pgm:\t0x%p\n"
  111. "init:\t0x%p\n"
  112. "err:\t0x%p\n"
  113. "clk:\t0x%p\n"
  114. "cs:\t0x%p\n"
  115. "wr:\t0x%p\n"
  116. "read data:\t0x%p\n"
  117. "write data:\t0x%p\n"
  118. "busy:\t0x%p\n"
  119. "abort:\t0x%p\n",
  120. "post:\t0x%p\n\n",
  121. __FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
  122. fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
  123. fn->abort, fn->post);
  124. /*
  125. * This code is designed to emulate the "Express Style"
  126. * Continuous Data Loading in Slave Parallel Mode for
  127. * the Spartan-II Family.
  128. */
  129. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  130. printf ("Loading FPGA Device %d...\n", cookie);
  131. #endif
  132. /*
  133. * Run the pre configuration function if there is one.
  134. */
  135. if (*fn->pre) {
  136. (*fn->pre) (cookie);
  137. }
  138. /* Establish the initial state */
  139. (*fn->pgm) (true, true, cookie); /* Assert the program, commit */
  140. /* Get ready for the burn */
  141. CONFIG_FPGA_DELAY ();
  142. (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */
  143. ts = get_timer (0); /* get current time */
  144. /* Now wait for INIT and BUSY to go high */
  145. do {
  146. CONFIG_FPGA_DELAY ();
  147. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
  148. puts ("** Timeout waiting for INIT to clear.\n");
  149. (*fn->abort) (cookie); /* abort the burn */
  150. return FPGA_FAIL;
  151. }
  152. } while ((*fn->init) (cookie) && (*fn->busy) (cookie));
  153. (*fn->wr) (true, true, cookie); /* Assert write, commit */
  154. (*fn->cs) (true, true, cookie); /* Assert chip select, commit */
  155. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  156. /* Load the data */
  157. while (bytecount < bsize) {
  158. /* XXX - do we check for an Ctrl-C press in here ??? */
  159. /* XXX - Check the error bit? */
  160. (*fn->wdata) (data[bytecount++], true, cookie); /* write the data */
  161. CONFIG_FPGA_DELAY ();
  162. (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
  163. CONFIG_FPGA_DELAY ();
  164. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  165. #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
  166. ts = get_timer (0); /* get current time */
  167. while ((*fn->busy) (cookie)) {
  168. /* XXX - we should have a check in here somewhere to
  169. * make sure we aren't busy forever... */
  170. CONFIG_FPGA_DELAY ();
  171. (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
  172. CONFIG_FPGA_DELAY ();
  173. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  174. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
  175. puts ("** Timeout waiting for BUSY to clear.\n");
  176. (*fn->abort) (cookie); /* abort the burn */
  177. return FPGA_FAIL;
  178. }
  179. }
  180. #endif
  181. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  182. if (bytecount % (bsize / 40) == 0)
  183. putc ('.'); /* let them know we are alive */
  184. #endif
  185. }
  186. CONFIG_FPGA_DELAY ();
  187. (*fn->cs) (false, true, cookie); /* Deassert the chip select */
  188. (*fn->wr) (false, true, cookie); /* Deassert the write pin */
  189. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  190. putc ('\n'); /* terminate the dotted line */
  191. #endif
  192. /* now check for done signal */
  193. ts = get_timer (0); /* get current time */
  194. ret_val = FPGA_SUCCESS;
  195. while ((*fn->done) (cookie) == FPGA_FAIL) {
  196. CONFIG_FPGA_DELAY ();
  197. (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
  198. CONFIG_FPGA_DELAY ();
  199. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  200. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
  201. puts ("** Timeout waiting for DONE to clear.\n");
  202. (*fn->abort) (cookie); /* abort the burn */
  203. ret_val = FPGA_FAIL;
  204. break;
  205. }
  206. }
  207. /*
  208. * Run the post configuration function if there is one.
  209. */
  210. if (*fn->post)
  211. (*fn->post) (cookie);
  212. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  213. if (ret_val == FPGA_SUCCESS)
  214. puts ("Done.\n");
  215. else
  216. puts ("Fail.\n");
  217. #endif
  218. } else {
  219. printf ("%s: NULL Interface function table!\n", __FUNCTION__);
  220. }
  221. return ret_val;
  222. }
  223. static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
  224. {
  225. int ret_val = FPGA_FAIL; /* assume the worst */
  226. Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns;
  227. if (fn) {
  228. unsigned char *data = (unsigned char *) buf;
  229. size_t bytecount = 0;
  230. int cookie = desc->cookie; /* make a local copy */
  231. printf ("Starting Dump of FPGA Device %d...\n", cookie);
  232. (*fn->cs) (true, true, cookie); /* Assert chip select, commit */
  233. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  234. /* dump the data */
  235. while (bytecount < bsize) {
  236. /* XXX - do we check for an Ctrl-C press in here ??? */
  237. (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
  238. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  239. (*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */
  240. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  241. if (bytecount % (bsize / 40) == 0)
  242. putc ('.'); /* let them know we are alive */
  243. #endif
  244. }
  245. (*fn->cs) (false, false, cookie); /* Deassert the chip select */
  246. (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
  247. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  248. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  249. putc ('\n'); /* terminate the dotted line */
  250. #endif
  251. puts ("Done.\n");
  252. /* XXX - checksum the data? */
  253. } else {
  254. printf ("%s: NULL Interface function table!\n", __FUNCTION__);
  255. }
  256. return ret_val;
  257. }
  258. /* ------------------------------------------------------------------------- */
  259. static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
  260. {
  261. int ret_val = FPGA_FAIL; /* assume the worst */
  262. Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns;
  263. int i;
  264. unsigned char val;
  265. PRINTF ("%s: start with interface functions @ 0x%p\n",
  266. __FUNCTION__, fn);
  267. if (fn) {
  268. size_t bytecount = 0;
  269. unsigned char *data = (unsigned char *) buf;
  270. int cookie = desc->cookie; /* make a local copy */
  271. unsigned long ts; /* timestamp */
  272. PRINTF ("%s: Function Table:\n"
  273. "ptr:\t0x%p\n"
  274. "struct: 0x%p\n"
  275. "pgm:\t0x%p\n"
  276. "init:\t0x%p\n"
  277. "clk:\t0x%p\n"
  278. "wr:\t0x%p\n"
  279. "done:\t0x%p\n\n",
  280. __FUNCTION__, &fn, fn, fn->pgm, fn->init,
  281. fn->clk, fn->wr, fn->done);
  282. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  283. printf ("Loading FPGA Device %d...\n", cookie);
  284. #endif
  285. /*
  286. * Run the pre configuration function if there is one.
  287. */
  288. if (*fn->pre) {
  289. (*fn->pre) (cookie);
  290. }
  291. /* Establish the initial state */
  292. (*fn->pgm) (true, true, cookie); /* Assert the program, commit */
  293. /* Wait for INIT state (init low) */
  294. ts = get_timer (0); /* get current time */
  295. do {
  296. CONFIG_FPGA_DELAY ();
  297. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
  298. puts ("** Timeout waiting for INIT to start.\n");
  299. return FPGA_FAIL;
  300. }
  301. } while (!(*fn->init) (cookie));
  302. /* Get ready for the burn */
  303. CONFIG_FPGA_DELAY ();
  304. (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */
  305. ts = get_timer (0); /* get current time */
  306. /* Now wait for INIT to go high */
  307. do {
  308. CONFIG_FPGA_DELAY ();
  309. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
  310. puts ("** Timeout waiting for INIT to clear.\n");
  311. return FPGA_FAIL;
  312. }
  313. } while ((*fn->init) (cookie));
  314. /* Load the data */
  315. while (bytecount < bsize) {
  316. /* Xilinx detects an error if INIT goes low (active)
  317. while DONE is low (inactive) */
  318. if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
  319. puts ("** CRC error during FPGA load.\n");
  320. return (FPGA_FAIL);
  321. }
  322. val = data [bytecount ++];
  323. i = 8;
  324. do {
  325. /* Deassert the clock */
  326. (*fn->clk) (false, true, cookie);
  327. CONFIG_FPGA_DELAY ();
  328. /* Write data */
  329. (*fn->wr) ((val & 0x80), true, cookie);
  330. CONFIG_FPGA_DELAY ();
  331. /* Assert the clock */
  332. (*fn->clk) (true, true, cookie);
  333. CONFIG_FPGA_DELAY ();
  334. val <<= 1;
  335. i --;
  336. } while (i > 0);
  337. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  338. if (bytecount % (bsize / 40) == 0)
  339. putc ('.'); /* let them know we are alive */
  340. #endif
  341. }
  342. CONFIG_FPGA_DELAY ();
  343. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  344. putc ('\n'); /* terminate the dotted line */
  345. #endif
  346. /* now check for done signal */
  347. ts = get_timer (0); /* get current time */
  348. ret_val = FPGA_SUCCESS;
  349. (*fn->wr) (true, true, cookie);
  350. while (! (*fn->done) (cookie)) {
  351. CONFIG_FPGA_DELAY ();
  352. (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
  353. CONFIG_FPGA_DELAY ();
  354. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  355. putc ('*');
  356. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
  357. puts ("** Timeout waiting for DONE to clear.\n");
  358. ret_val = FPGA_FAIL;
  359. break;
  360. }
  361. }
  362. putc ('\n'); /* terminate the dotted line */
  363. /*
  364. * Run the post configuration function if there is one.
  365. */
  366. if (*fn->post)
  367. (*fn->post) (cookie);
  368. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  369. if (ret_val == FPGA_SUCCESS)
  370. puts ("Done.\n");
  371. else
  372. puts ("Fail.\n");
  373. #endif
  374. } else {
  375. printf ("%s: NULL Interface function table!\n", __FUNCTION__);
  376. }
  377. return ret_val;
  378. }
  379. static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
  380. {
  381. /* Readback is only available through the Slave Parallel and */
  382. /* boundary-scan interfaces. */
  383. printf ("%s: Slave Serial Dumping is unavailable\n",
  384. __FUNCTION__);
  385. return FPGA_FAIL;
  386. }