ahci.c 25 KB

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  1. /*
  2. * Copyright (C) Freescale Semiconductor, Inc. 2006.
  3. * Author: Jason Jin<Jason.jin@freescale.com>
  4. * Zhang Wei<wei.zhang@freescale.com>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. *
  24. * with the reference on libata and ahci drvier in kernel
  25. *
  26. */
  27. #include <common.h>
  28. #include <command.h>
  29. #include <pci.h>
  30. #include <asm/processor.h>
  31. #include <asm/errno.h>
  32. #include <asm/io.h>
  33. #include <malloc.h>
  34. #include <scsi.h>
  35. #include <ata.h>
  36. #include <linux/ctype.h>
  37. #include <ahci.h>
  38. static int ata_io_flush(u8 port);
  39. struct ahci_probe_ent *probe_ent = NULL;
  40. hd_driveid_t *ataid[AHCI_MAX_PORTS];
  41. #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
  42. /*
  43. * Some controllers limit number of blocks they can read/write at once.
  44. * Contemporary SSD devices work much faster if the read/write size is aligned
  45. * to a power of 2. Let's set default to 128 and allowing to be overwritten if
  46. * needed.
  47. */
  48. #ifndef MAX_SATA_BLOCKS_READ_WRITE
  49. #define MAX_SATA_BLOCKS_READ_WRITE 0x80
  50. #endif
  51. /* Maximum timeouts for each event */
  52. #define WAIT_MS_SPINUP 10000
  53. #define WAIT_MS_DATAIO 5000
  54. #define WAIT_MS_FLUSH 5000
  55. #define WAIT_MS_LINKUP 4
  56. static inline u32 ahci_port_base(u32 base, u32 port)
  57. {
  58. return base + 0x100 + (port * 0x80);
  59. }
  60. static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
  61. unsigned int port_idx)
  62. {
  63. base = ahci_port_base(base, port_idx);
  64. port->cmd_addr = base;
  65. port->scr_addr = base + PORT_SCR;
  66. }
  67. #define msleep(a) udelay(a * 1000)
  68. static void ahci_dcache_flush_range(unsigned begin, unsigned len)
  69. {
  70. const unsigned long start = begin;
  71. const unsigned long end = start + len;
  72. debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
  73. flush_dcache_range(start, end);
  74. }
  75. /*
  76. * SATA controller DMAs to physical RAM. Ensure data from the
  77. * controller is invalidated from dcache; next access comes from
  78. * physical RAM.
  79. */
  80. static void ahci_dcache_invalidate_range(unsigned begin, unsigned len)
  81. {
  82. const unsigned long start = begin;
  83. const unsigned long end = start + len;
  84. debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
  85. invalidate_dcache_range(start, end);
  86. }
  87. /*
  88. * Ensure data for SATA controller is flushed out of dcache and
  89. * written to physical memory.
  90. */
  91. static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
  92. {
  93. ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
  94. AHCI_PORT_PRIV_DMA_SZ);
  95. }
  96. static int waiting_for_cmd_completed(volatile u8 *offset,
  97. int timeout_msec,
  98. u32 sign)
  99. {
  100. int i;
  101. u32 status;
  102. for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
  103. msleep(1);
  104. return (i < timeout_msec) ? 0 : -1;
  105. }
  106. static int ahci_host_init(struct ahci_probe_ent *probe_ent)
  107. {
  108. #ifndef CONFIG_SCSI_AHCI_PLAT
  109. pci_dev_t pdev = probe_ent->dev;
  110. u16 tmp16;
  111. unsigned short vendor;
  112. #endif
  113. volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
  114. u32 tmp, cap_save, cmd;
  115. int i, j;
  116. volatile u8 *port_mmio;
  117. debug("ahci_host_init: start\n");
  118. cap_save = readl(mmio + HOST_CAP);
  119. cap_save &= ((1 << 28) | (1 << 17));
  120. cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
  121. /* global controller reset */
  122. tmp = readl(mmio + HOST_CTL);
  123. if ((tmp & HOST_RESET) == 0)
  124. writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
  125. /* reset must complete within 1 second, or
  126. * the hardware should be considered fried.
  127. */
  128. i = 1000;
  129. do {
  130. udelay(1000);
  131. tmp = readl(mmio + HOST_CTL);
  132. if (!i--) {
  133. debug("controller reset failed (0x%x)\n", tmp);
  134. return -1;
  135. }
  136. } while (tmp & HOST_RESET);
  137. writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
  138. writel(cap_save, mmio + HOST_CAP);
  139. writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
  140. #ifndef CONFIG_SCSI_AHCI_PLAT
  141. pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
  142. if (vendor == PCI_VENDOR_ID_INTEL) {
  143. u16 tmp16;
  144. pci_read_config_word(pdev, 0x92, &tmp16);
  145. tmp16 |= 0xf;
  146. pci_write_config_word(pdev, 0x92, tmp16);
  147. }
  148. #endif
  149. probe_ent->cap = readl(mmio + HOST_CAP);
  150. probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
  151. probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
  152. debug("cap 0x%x port_map 0x%x n_ports %d\n",
  153. probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
  154. if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
  155. probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
  156. for (i = 0; i < probe_ent->n_ports; i++) {
  157. probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
  158. port_mmio = (u8 *) probe_ent->port[i].port_mmio;
  159. ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
  160. /* make sure port is not active */
  161. tmp = readl(port_mmio + PORT_CMD);
  162. if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
  163. PORT_CMD_FIS_RX | PORT_CMD_START)) {
  164. debug("Port %d is active. Deactivating.\n", i);
  165. tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
  166. PORT_CMD_FIS_RX | PORT_CMD_START);
  167. writel_with_flush(tmp, port_mmio + PORT_CMD);
  168. /* spec says 500 msecs for each bit, so
  169. * this is slightly incorrect.
  170. */
  171. msleep(500);
  172. }
  173. /* Add the spinup command to whatever mode bits may
  174. * already be on in the command register.
  175. */
  176. cmd = readl(port_mmio + PORT_CMD);
  177. cmd |= PORT_CMD_FIS_RX;
  178. cmd |= PORT_CMD_SPIN_UP;
  179. writel_with_flush(cmd, port_mmio + PORT_CMD);
  180. /* Bring up SATA link.
  181. * SATA link bringup time is usually less than 1 ms; only very
  182. * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
  183. */
  184. j = 0;
  185. while (j < WAIT_MS_LINKUP) {
  186. tmp = readl(port_mmio + PORT_SCR_STAT);
  187. if ((tmp & 0xf) == 0x3)
  188. break;
  189. udelay(1000);
  190. j++;
  191. }
  192. if (j == WAIT_MS_LINKUP) {
  193. printf("SATA link %d timeout.\n", i);
  194. continue;
  195. } else {
  196. debug("SATA link ok.\n");
  197. }
  198. /* Clear error status */
  199. tmp = readl(port_mmio + PORT_SCR_ERR);
  200. if (tmp)
  201. writel(tmp, port_mmio + PORT_SCR_ERR);
  202. debug("Spinning up device on SATA port %d... ", i);
  203. j = 0;
  204. while (j < WAIT_MS_SPINUP) {
  205. tmp = readl(port_mmio + PORT_TFDATA);
  206. if (!(tmp & (ATA_STAT_BUSY | ATA_STAT_DRQ)))
  207. break;
  208. udelay(1000);
  209. j++;
  210. }
  211. printf("Target spinup took %d ms.\n", j);
  212. if (j == WAIT_MS_SPINUP)
  213. debug("timeout.\n");
  214. else
  215. debug("ok.\n");
  216. tmp = readl(port_mmio + PORT_SCR_ERR);
  217. debug("PORT_SCR_ERR 0x%x\n", tmp);
  218. writel(tmp, port_mmio + PORT_SCR_ERR);
  219. /* ack any pending irq events for this port */
  220. tmp = readl(port_mmio + PORT_IRQ_STAT);
  221. debug("PORT_IRQ_STAT 0x%x\n", tmp);
  222. if (tmp)
  223. writel(tmp, port_mmio + PORT_IRQ_STAT);
  224. writel(1 << i, mmio + HOST_IRQ_STAT);
  225. /* set irq mask (enables interrupts) */
  226. writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
  227. /* register linkup ports */
  228. tmp = readl(port_mmio + PORT_SCR_STAT);
  229. debug("SATA port %d status: 0x%x\n", i, tmp);
  230. if ((tmp & 0xf) == 0x03)
  231. probe_ent->link_port_map |= (0x01 << i);
  232. }
  233. tmp = readl(mmio + HOST_CTL);
  234. debug("HOST_CTL 0x%x\n", tmp);
  235. writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
  236. tmp = readl(mmio + HOST_CTL);
  237. debug("HOST_CTL 0x%x\n", tmp);
  238. #ifndef CONFIG_SCSI_AHCI_PLAT
  239. pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
  240. tmp |= PCI_COMMAND_MASTER;
  241. pci_write_config_word(pdev, PCI_COMMAND, tmp16);
  242. #endif
  243. return 0;
  244. }
  245. static void ahci_print_info(struct ahci_probe_ent *probe_ent)
  246. {
  247. #ifndef CONFIG_SCSI_AHCI_PLAT
  248. pci_dev_t pdev = probe_ent->dev;
  249. u16 cc;
  250. #endif
  251. volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
  252. u32 vers, cap, cap2, impl, speed;
  253. const char *speed_s;
  254. const char *scc_s;
  255. vers = readl(mmio + HOST_VERSION);
  256. cap = probe_ent->cap;
  257. cap2 = readl(mmio + HOST_CAP2);
  258. impl = probe_ent->port_map;
  259. speed = (cap >> 20) & 0xf;
  260. if (speed == 1)
  261. speed_s = "1.5";
  262. else if (speed == 2)
  263. speed_s = "3";
  264. else if (speed == 3)
  265. speed_s = "6";
  266. else
  267. speed_s = "?";
  268. #ifdef CONFIG_SCSI_AHCI_PLAT
  269. scc_s = "SATA";
  270. #else
  271. pci_read_config_word(pdev, 0x0a, &cc);
  272. if (cc == 0x0101)
  273. scc_s = "IDE";
  274. else if (cc == 0x0106)
  275. scc_s = "SATA";
  276. else if (cc == 0x0104)
  277. scc_s = "RAID";
  278. else
  279. scc_s = "unknown";
  280. #endif
  281. printf("AHCI %02x%02x.%02x%02x "
  282. "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
  283. (vers >> 24) & 0xff,
  284. (vers >> 16) & 0xff,
  285. (vers >> 8) & 0xff,
  286. vers & 0xff,
  287. ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
  288. printf("flags: "
  289. "%s%s%s%s%s%s%s"
  290. "%s%s%s%s%s%s%s"
  291. "%s%s%s%s%s%s\n",
  292. cap & (1 << 31) ? "64bit " : "",
  293. cap & (1 << 30) ? "ncq " : "",
  294. cap & (1 << 28) ? "ilck " : "",
  295. cap & (1 << 27) ? "stag " : "",
  296. cap & (1 << 26) ? "pm " : "",
  297. cap & (1 << 25) ? "led " : "",
  298. cap & (1 << 24) ? "clo " : "",
  299. cap & (1 << 19) ? "nz " : "",
  300. cap & (1 << 18) ? "only " : "",
  301. cap & (1 << 17) ? "pmp " : "",
  302. cap & (1 << 16) ? "fbss " : "",
  303. cap & (1 << 15) ? "pio " : "",
  304. cap & (1 << 14) ? "slum " : "",
  305. cap & (1 << 13) ? "part " : "",
  306. cap & (1 << 7) ? "ccc " : "",
  307. cap & (1 << 6) ? "ems " : "",
  308. cap & (1 << 5) ? "sxs " : "",
  309. cap2 & (1 << 2) ? "apst " : "",
  310. cap2 & (1 << 1) ? "nvmp " : "",
  311. cap2 & (1 << 0) ? "boh " : "");
  312. }
  313. #ifndef CONFIG_SCSI_AHCI_PLAT
  314. static int ahci_init_one(pci_dev_t pdev)
  315. {
  316. u16 vendor;
  317. int rc;
  318. memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);
  319. probe_ent = malloc(sizeof(struct ahci_probe_ent));
  320. memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
  321. probe_ent->dev = pdev;
  322. probe_ent->host_flags = ATA_FLAG_SATA
  323. | ATA_FLAG_NO_LEGACY
  324. | ATA_FLAG_MMIO
  325. | ATA_FLAG_PIO_DMA
  326. | ATA_FLAG_NO_ATAPI;
  327. probe_ent->pio_mask = 0x1f;
  328. probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
  329. pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base);
  330. debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base);
  331. /* Take from kernel:
  332. * JMicron-specific fixup:
  333. * make sure we're in AHCI mode
  334. */
  335. pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
  336. if (vendor == 0x197b)
  337. pci_write_config_byte(pdev, 0x41, 0xa1);
  338. /* initialize adapter */
  339. rc = ahci_host_init(probe_ent);
  340. if (rc)
  341. goto err_out;
  342. ahci_print_info(probe_ent);
  343. return 0;
  344. err_out:
  345. return rc;
  346. }
  347. #endif
  348. #define MAX_DATA_BYTE_COUNT (4*1024*1024)
  349. static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
  350. {
  351. struct ahci_ioports *pp = &(probe_ent->port[port]);
  352. struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
  353. u32 sg_count;
  354. int i;
  355. sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
  356. if (sg_count > AHCI_MAX_SG) {
  357. printf("Error:Too much sg!\n");
  358. return -1;
  359. }
  360. for (i = 0; i < sg_count; i++) {
  361. ahci_sg->addr =
  362. cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
  363. ahci_sg->addr_hi = 0;
  364. ahci_sg->flags_size = cpu_to_le32(0x3fffff &
  365. (buf_len < MAX_DATA_BYTE_COUNT
  366. ? (buf_len - 1)
  367. : (MAX_DATA_BYTE_COUNT - 1)));
  368. ahci_sg++;
  369. buf_len -= MAX_DATA_BYTE_COUNT;
  370. }
  371. return sg_count;
  372. }
  373. static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
  374. {
  375. pp->cmd_slot->opts = cpu_to_le32(opts);
  376. pp->cmd_slot->status = 0;
  377. pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
  378. pp->cmd_slot->tbl_addr_hi = 0;
  379. }
  380. #ifdef CONFIG_AHCI_SETFEATURES_XFER
  381. static void ahci_set_feature(u8 port)
  382. {
  383. struct ahci_ioports *pp = &(probe_ent->port[port]);
  384. volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
  385. u32 cmd_fis_len = 5; /* five dwords */
  386. u8 fis[20];
  387. /* set feature */
  388. memset(fis, 0, sizeof(fis));
  389. fis[0] = 0x27;
  390. fis[1] = 1 << 7;
  391. fis[2] = ATA_CMD_SETF;
  392. fis[3] = SETFEATURES_XFER;
  393. fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
  394. memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis));
  395. ahci_fill_cmd_slot(pp, cmd_fis_len);
  396. ahci_dcache_flush_sata_cmd(pp);
  397. writel(1, port_mmio + PORT_CMD_ISSUE);
  398. readl(port_mmio + PORT_CMD_ISSUE);
  399. if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
  400. WAIT_MS_DATAIO, 0x1)) {
  401. printf("set feature error on port %d!\n", port);
  402. }
  403. }
  404. #endif
  405. static int ahci_port_start(u8 port)
  406. {
  407. struct ahci_ioports *pp = &(probe_ent->port[port]);
  408. volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
  409. u32 port_status;
  410. u32 mem;
  411. debug("Enter start port: %d\n", port);
  412. port_status = readl(port_mmio + PORT_SCR_STAT);
  413. debug("Port %d status: %x\n", port, port_status);
  414. if ((port_status & 0xf) != 0x03) {
  415. printf("No Link on this port!\n");
  416. return -1;
  417. }
  418. mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
  419. if (!mem) {
  420. free(pp);
  421. printf("No mem for table!\n");
  422. return -ENOMEM;
  423. }
  424. mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
  425. memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
  426. /*
  427. * First item in chunk of DMA memory: 32-slot command table,
  428. * 32 bytes each in size
  429. */
  430. pp->cmd_slot =
  431. (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
  432. debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot);
  433. mem += (AHCI_CMD_SLOT_SZ + 224);
  434. /*
  435. * Second item: Received-FIS area
  436. */
  437. pp->rx_fis = virt_to_phys((void *)mem);
  438. mem += AHCI_RX_FIS_SZ;
  439. /*
  440. * Third item: data area for storing a single command
  441. * and its scatter-gather table
  442. */
  443. pp->cmd_tbl = virt_to_phys((void *)mem);
  444. debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
  445. mem += AHCI_CMD_TBL_HDR;
  446. pp->cmd_tbl_sg =
  447. (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
  448. writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
  449. writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
  450. writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
  451. PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
  452. PORT_CMD_START, port_mmio + PORT_CMD);
  453. debug("Exit start port %d\n", port);
  454. return 0;
  455. }
  456. static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf,
  457. int buf_len, u8 is_write)
  458. {
  459. struct ahci_ioports *pp = &(probe_ent->port[port]);
  460. volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
  461. u32 opts;
  462. u32 port_status;
  463. int sg_count;
  464. debug("Enter %s: for port %d\n", __func__, port);
  465. if (port > probe_ent->n_ports) {
  466. printf("Invalid port number %d\n", port);
  467. return -1;
  468. }
  469. port_status = readl(port_mmio + PORT_SCR_STAT);
  470. if ((port_status & 0xf) != 0x03) {
  471. debug("No Link on port %d!\n", port);
  472. return -1;
  473. }
  474. memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
  475. sg_count = ahci_fill_sg(port, buf, buf_len);
  476. opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
  477. ahci_fill_cmd_slot(pp, opts);
  478. ahci_dcache_flush_sata_cmd(pp);
  479. ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len);
  480. writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
  481. if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
  482. WAIT_MS_DATAIO, 0x1)) {
  483. printf("timeout exit!\n");
  484. return -1;
  485. }
  486. ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len);
  487. debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
  488. return 0;
  489. }
  490. static char *ata_id_strcpy(u16 *target, u16 *src, int len)
  491. {
  492. int i;
  493. for (i = 0; i < len / 2; i++)
  494. target[i] = swab16(src[i]);
  495. return (char *)target;
  496. }
  497. static void dump_ataid(hd_driveid_t *ataid)
  498. {
  499. debug("(49)ataid->capability = 0x%x\n", ataid->capability);
  500. debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);
  501. debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);
  502. debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);
  503. debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);
  504. debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);
  505. debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);
  506. debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);
  507. debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);
  508. debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);
  509. debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);
  510. debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);
  511. debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);
  512. debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);
  513. debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);
  514. }
  515. /*
  516. * SCSI INQUIRY command operation.
  517. */
  518. static int ata_scsiop_inquiry(ccb *pccb)
  519. {
  520. u8 hdr[] = {
  521. 0,
  522. 0,
  523. 0x5, /* claim SPC-3 version compatibility */
  524. 2,
  525. 95 - 4,
  526. };
  527. u8 fis[20];
  528. u8 *tmpid;
  529. u8 port;
  530. /* Clean ccb data buffer */
  531. memset(pccb->pdata, 0, pccb->datalen);
  532. memcpy(pccb->pdata, hdr, sizeof(hdr));
  533. if (pccb->datalen <= 35)
  534. return 0;
  535. memset(fis, 0, sizeof(fis));
  536. /* Construct the FIS */
  537. fis[0] = 0x27; /* Host to device FIS. */
  538. fis[1] = 1 << 7; /* Command FIS. */
  539. fis[2] = ATA_CMD_IDENT; /* Command byte. */
  540. /* Read id from sata */
  541. port = pccb->target;
  542. if (!(tmpid = malloc(sizeof(hd_driveid_t))))
  543. return -ENOMEM;
  544. if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), tmpid,
  545. sizeof(hd_driveid_t), 0)) {
  546. debug("scsi_ahci: SCSI inquiry command failure.\n");
  547. return -EIO;
  548. }
  549. if (ataid[port])
  550. free(ataid[port]);
  551. ataid[port] = (hd_driveid_t *) tmpid;
  552. memcpy(&pccb->pdata[8], "ATA ", 8);
  553. ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);
  554. ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);
  555. dump_ataid(ataid[port]);
  556. return 0;
  557. }
  558. /*
  559. * SCSI READ10/WRITE10 command operation.
  560. */
  561. static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
  562. {
  563. u32 lba = 0;
  564. u16 blocks = 0;
  565. u8 fis[20];
  566. u8 *user_buffer = pccb->pdata;
  567. u32 user_buffer_size = pccb->datalen;
  568. /* Retrieve the base LBA number from the ccb structure. */
  569. memcpy(&lba, pccb->cmd + 2, sizeof(lba));
  570. lba = be32_to_cpu(lba);
  571. /*
  572. * And the number of blocks.
  573. *
  574. * For 10-byte and 16-byte SCSI R/W commands, transfer
  575. * length 0 means transfer 0 block of data.
  576. * However, for ATA R/W commands, sector count 0 means
  577. * 256 or 65536 sectors, not 0 sectors as in SCSI.
  578. *
  579. * WARNING: one or two older ATA drives treat 0 as 0...
  580. */
  581. blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
  582. debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",
  583. is_write ? "write" : "read", (unsigned)lba, blocks);
  584. /* Preset the FIS */
  585. memset(fis, 0, sizeof(fis));
  586. fis[0] = 0x27; /* Host to device FIS. */
  587. fis[1] = 1 << 7; /* Command FIS. */
  588. /* Command byte (read/write). */
  589. fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
  590. while (blocks) {
  591. u16 now_blocks; /* number of blocks per iteration */
  592. u32 transfer_size; /* number of bytes per iteration */
  593. now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks);
  594. transfer_size = ATA_BLOCKSIZE * now_blocks;
  595. if (transfer_size > user_buffer_size) {
  596. printf("scsi_ahci: Error: buffer too small.\n");
  597. return -EIO;
  598. }
  599. /* LBA48 SATA command but only use 32bit address range within
  600. * that. The next smaller command range (28bit) is too small.
  601. */
  602. fis[4] = (lba >> 0) & 0xff;
  603. fis[5] = (lba >> 8) & 0xff;
  604. fis[6] = (lba >> 16) & 0xff;
  605. fis[7] = 1 << 6; /* device reg: set LBA mode */
  606. fis[8] = ((lba >> 24) & 0xff);
  607. fis[3] = 0xe0; /* features */
  608. /* Block (sector) count */
  609. fis[12] = (now_blocks >> 0) & 0xff;
  610. fis[13] = (now_blocks >> 8) & 0xff;
  611. /* Read/Write from ahci */
  612. if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis),
  613. user_buffer, user_buffer_size,
  614. is_write)) {
  615. debug("scsi_ahci: SCSI %s10 command failure.\n",
  616. is_write ? "WRITE" : "READ");
  617. return -EIO;
  618. }
  619. /* If this transaction is a write, do a following flush.
  620. * Writes in u-boot are so rare, and the logic to know when is
  621. * the last write and do a flush only there is sufficiently
  622. * difficult. Just do a flush after every write. This incurs,
  623. * usually, one extra flush when the rare writes do happen.
  624. */
  625. if (is_write) {
  626. if (-EIO == ata_io_flush(pccb->target))
  627. return -EIO;
  628. }
  629. user_buffer += transfer_size;
  630. user_buffer_size -= transfer_size;
  631. blocks -= now_blocks;
  632. lba += now_blocks;
  633. }
  634. return 0;
  635. }
  636. /*
  637. * SCSI READ CAPACITY10 command operation.
  638. */
  639. static int ata_scsiop_read_capacity10(ccb *pccb)
  640. {
  641. u32 cap;
  642. u32 block_size;
  643. if (!ataid[pccb->target]) {
  644. printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
  645. "\tNo ATA info!\n"
  646. "\tPlease run SCSI commmand INQUIRY firstly!\n");
  647. return -EPERM;
  648. }
  649. cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
  650. if (cap == 0xfffffff) {
  651. unsigned short *cap48 = ataid[pccb->target]->lba48_capacity;
  652. if (cap48[2] || cap48[3]) {
  653. cap = 0xffffffff;
  654. } else {
  655. cap = (le16_to_cpu(cap48[1]) << 16) |
  656. (le16_to_cpu(cap48[0]));
  657. }
  658. }
  659. cap = cpu_to_be32(cap);
  660. memcpy(pccb->pdata, &cap, sizeof(cap));
  661. block_size = cpu_to_be32((u32)512);
  662. memcpy(&pccb->pdata[4], &block_size, 4);
  663. return 0;
  664. }
  665. /*
  666. * SCSI READ CAPACITY16 command operation.
  667. */
  668. static int ata_scsiop_read_capacity16(ccb *pccb)
  669. {
  670. u64 cap;
  671. u64 block_size;
  672. if (!ataid[pccb->target]) {
  673. printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
  674. "\tNo ATA info!\n"
  675. "\tPlease run SCSI commmand INQUIRY firstly!\n");
  676. return -EPERM;
  677. }
  678. cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
  679. if (cap == 0xfffffff) {
  680. memcpy(&cap, ataid[pccb->target]->lba48_capacity, sizeof(cap));
  681. cap = le64_to_cpu(cap);
  682. }
  683. cap = cpu_to_be64(cap);
  684. memcpy(pccb->pdata, &cap, sizeof(cap));
  685. block_size = cpu_to_be64((u64)512);
  686. memcpy(&pccb->pdata[8], &block_size, 8);
  687. return 0;
  688. }
  689. /*
  690. * SCSI TEST UNIT READY command operation.
  691. */
  692. static int ata_scsiop_test_unit_ready(ccb *pccb)
  693. {
  694. return (ataid[pccb->target]) ? 0 : -EPERM;
  695. }
  696. int scsi_exec(ccb *pccb)
  697. {
  698. int ret;
  699. switch (pccb->cmd[0]) {
  700. case SCSI_READ10:
  701. ret = ata_scsiop_read_write(pccb, 0);
  702. break;
  703. case SCSI_WRITE10:
  704. ret = ata_scsiop_read_write(pccb, 1);
  705. break;
  706. case SCSI_RD_CAPAC10:
  707. ret = ata_scsiop_read_capacity10(pccb);
  708. break;
  709. case SCSI_RD_CAPAC16:
  710. ret = ata_scsiop_read_capacity16(pccb);
  711. break;
  712. case SCSI_TST_U_RDY:
  713. ret = ata_scsiop_test_unit_ready(pccb);
  714. break;
  715. case SCSI_INQUIRY:
  716. ret = ata_scsiop_inquiry(pccb);
  717. break;
  718. default:
  719. printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
  720. return false;
  721. }
  722. if (ret) {
  723. debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
  724. return false;
  725. }
  726. return true;
  727. }
  728. void scsi_low_level_init(int busdevfunc)
  729. {
  730. int i;
  731. u32 linkmap;
  732. #ifndef CONFIG_SCSI_AHCI_PLAT
  733. ahci_init_one(busdevfunc);
  734. #endif
  735. linkmap = probe_ent->link_port_map;
  736. for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
  737. if (((linkmap >> i) & 0x01)) {
  738. if (ahci_port_start((u8) i)) {
  739. printf("Can not start port %d\n", i);
  740. continue;
  741. }
  742. #ifdef CONFIG_AHCI_SETFEATURES_XFER
  743. ahci_set_feature((u8) i);
  744. #endif
  745. }
  746. }
  747. }
  748. #ifdef CONFIG_SCSI_AHCI_PLAT
  749. int ahci_init(u32 base)
  750. {
  751. int i, rc = 0;
  752. u32 linkmap;
  753. memset(ataid, 0, sizeof(ataid));
  754. probe_ent = malloc(sizeof(struct ahci_probe_ent));
  755. memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
  756. probe_ent->host_flags = ATA_FLAG_SATA
  757. | ATA_FLAG_NO_LEGACY
  758. | ATA_FLAG_MMIO
  759. | ATA_FLAG_PIO_DMA
  760. | ATA_FLAG_NO_ATAPI;
  761. probe_ent->pio_mask = 0x1f;
  762. probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
  763. probe_ent->mmio_base = base;
  764. /* initialize adapter */
  765. rc = ahci_host_init(probe_ent);
  766. if (rc)
  767. goto err_out;
  768. ahci_print_info(probe_ent);
  769. linkmap = probe_ent->link_port_map;
  770. for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
  771. if (((linkmap >> i) & 0x01)) {
  772. if (ahci_port_start((u8) i)) {
  773. printf("Can not start port %d\n", i);
  774. continue;
  775. }
  776. #ifdef CONFIG_AHCI_SETFEATURES_XFER
  777. ahci_set_feature((u8) i);
  778. #endif
  779. }
  780. }
  781. err_out:
  782. return rc;
  783. }
  784. #endif
  785. /*
  786. * In the general case of generic rotating media it makes sense to have a
  787. * flush capability. It probably even makes sense in the case of SSDs because
  788. * one cannot always know for sure what kind of internal cache/flush mechanism
  789. * is embodied therein. At first it was planned to invoke this after the last
  790. * write to disk and before rebooting. In practice, knowing, a priori, which
  791. * is the last write is difficult. Because writing to the disk in u-boot is
  792. * very rare, this flush command will be invoked after every block write.
  793. */
  794. static int ata_io_flush(u8 port)
  795. {
  796. u8 fis[20];
  797. struct ahci_ioports *pp = &(probe_ent->port[port]);
  798. volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
  799. u32 cmd_fis_len = 5; /* five dwords */
  800. /* Preset the FIS */
  801. memset(fis, 0, 20);
  802. fis[0] = 0x27; /* Host to device FIS. */
  803. fis[1] = 1 << 7; /* Command FIS. */
  804. fis[2] = ATA_CMD_FLUSH_EXT;
  805. memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
  806. ahci_fill_cmd_slot(pp, cmd_fis_len);
  807. writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
  808. if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
  809. WAIT_MS_FLUSH, 0x1)) {
  810. debug("scsi_ahci: flush command timeout on port %d.\n", port);
  811. return -EIO;
  812. }
  813. return 0;
  814. }
  815. void scsi_bus_reset(void)
  816. {
  817. /*Not implement*/
  818. }
  819. void scsi_print_error(ccb * pccb)
  820. {
  821. /*The ahci error info can be read in the ahci driver*/
  822. }