mt_ventoux.c 7.7 KB

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  1. /*
  2. * Copyright (C) 2011
  3. * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
  4. *
  5. * Copyright (C) 2009 TechNexion Ltd.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc.
  20. */
  21. #include <common.h>
  22. #include <netdev.h>
  23. #include <malloc.h>
  24. #include <fpga.h>
  25. #include <video_fb.h>
  26. #include <asm/io.h>
  27. #include <asm/arch/mem.h>
  28. #include <asm/arch/mux.h>
  29. #include <asm/arch/sys_proto.h>
  30. #include <asm/omap_gpio.h>
  31. #include <asm/arch/mmc_host_def.h>
  32. #include <asm/arch/dss.h>
  33. #include <asm/arch/clocks.h>
  34. #include <i2c.h>
  35. #include <spartan3.h>
  36. #include <asm/gpio.h>
  37. #ifdef CONFIG_USB_EHCI
  38. #include <usb.h>
  39. #include <asm/ehci-omap.h>
  40. #endif
  41. #include "mt_ventoux.h"
  42. DECLARE_GLOBAL_DATA_PTR;
  43. #define BUZZER 140
  44. #define SPEAKER 141
  45. #define USB1_PWR 127
  46. #define USB2_PWR 149
  47. #ifndef CONFIG_FPGA
  48. #error "The Teejet mt_ventoux must have CONFIG_FPGA enabled"
  49. #endif
  50. #define FPGA_RESET 62
  51. #define FPGA_PROG 116
  52. #define FPGA_CCLK 117
  53. #define FPGA_DIN 118
  54. #define FPGA_INIT 119
  55. #define FPGA_DONE 154
  56. #define LCD_PWR 138
  57. #define LCD_PON_PIN 139
  58. #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
  59. static struct {
  60. u32 xres;
  61. u32 yres;
  62. } panel_resolution[] = {
  63. { 480, 272 },
  64. { 800, 480 }
  65. };
  66. static struct panel_config lcd_cfg[] = {
  67. {
  68. .timing_h = PANEL_TIMING_H(40, 5, 2),
  69. .timing_v = PANEL_TIMING_V(8, 8, 2),
  70. .pol_freq = 0x00003000, /* Pol Freq */
  71. .divisor = 0x00010033, /* 9 Mhz Pixel Clock */
  72. .panel_type = 0x01, /* TFT */
  73. .data_lines = 0x03, /* 24 Bit RGB */
  74. .load_mode = 0x02, /* Frame Mode */
  75. .panel_color = 0,
  76. .gfx_format = GFXFORMAT_RGB24_UNPACKED,
  77. },
  78. {
  79. .timing_h = PANEL_TIMING_H(20, 192, 4),
  80. .timing_v = PANEL_TIMING_V(2, 20, 10),
  81. .pol_freq = 0x00004000, /* Pol Freq */
  82. .divisor = 0x0001000E, /* 36Mhz Pixel Clock */
  83. .panel_type = 0x01, /* TFT */
  84. .data_lines = 0x03, /* 24 Bit RGB */
  85. .load_mode = 0x02, /* Frame Mode */
  86. .panel_color = 0,
  87. .gfx_format = GFXFORMAT_RGB24_UNPACKED,
  88. }
  89. };
  90. #endif
  91. /* Timing definitions for FPGA */
  92. static const u32 gpmc_fpga[] = {
  93. FPGA_GPMC_CONFIG1,
  94. FPGA_GPMC_CONFIG2,
  95. FPGA_GPMC_CONFIG3,
  96. FPGA_GPMC_CONFIG4,
  97. FPGA_GPMC_CONFIG5,
  98. FPGA_GPMC_CONFIG6,
  99. };
  100. #ifdef CONFIG_USB_EHCI
  101. static struct omap_usbhs_board_data usbhs_bdata = {
  102. .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
  103. .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
  104. .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
  105. };
  106. int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  107. {
  108. return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
  109. }
  110. int ehci_hcd_stop(int index)
  111. {
  112. return omap_ehci_hcd_stop();
  113. }
  114. #endif
  115. static inline void fpga_reset(int nassert)
  116. {
  117. gpio_set_value(FPGA_RESET, !nassert);
  118. }
  119. int fpga_pgm_fn(int nassert, int nflush, int cookie)
  120. {
  121. debug("%s:%d: FPGA PROGRAM ", __func__, __LINE__);
  122. gpio_set_value(FPGA_PROG, !nassert);
  123. return nassert;
  124. }
  125. int fpga_init_fn(int cookie)
  126. {
  127. return !gpio_get_value(FPGA_INIT);
  128. }
  129. int fpga_done_fn(int cookie)
  130. {
  131. return gpio_get_value(FPGA_DONE);
  132. }
  133. int fpga_pre_config_fn(int cookie)
  134. {
  135. debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
  136. /* Setting GPIOs for programming Mode */
  137. gpio_request(FPGA_RESET, "FPGA_RESET");
  138. gpio_direction_output(FPGA_RESET, 1);
  139. gpio_request(FPGA_PROG, "FPGA_PROG");
  140. gpio_direction_output(FPGA_PROG, 1);
  141. gpio_request(FPGA_CCLK, "FPGA_CCLK");
  142. gpio_direction_output(FPGA_CCLK, 1);
  143. gpio_request(FPGA_DIN, "FPGA_DIN");
  144. gpio_direction_output(FPGA_DIN, 0);
  145. gpio_request(FPGA_INIT, "FPGA_INIT");
  146. gpio_direction_input(FPGA_INIT);
  147. gpio_request(FPGA_DONE, "FPGA_DONE");
  148. gpio_direction_input(FPGA_DONE);
  149. /* Be sure that signal are deasserted */
  150. gpio_set_value(FPGA_RESET, 1);
  151. gpio_set_value(FPGA_PROG, 1);
  152. return 0;
  153. }
  154. int fpga_post_config_fn(int cookie)
  155. {
  156. debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__);
  157. fpga_reset(true);
  158. udelay(100);
  159. fpga_reset(false);
  160. return 0;
  161. }
  162. /* Write program to the FPGA */
  163. int fpga_wr_fn(int nassert_write, int flush, int cookie)
  164. {
  165. gpio_set_value(FPGA_DIN, nassert_write);
  166. return nassert_write;
  167. }
  168. int fpga_clk_fn(int assert_clk, int flush, int cookie)
  169. {
  170. gpio_set_value(FPGA_CCLK, assert_clk);
  171. return assert_clk;
  172. }
  173. Xilinx_Spartan3_Slave_Serial_fns mt_ventoux_fpga_fns = {
  174. fpga_pre_config_fn,
  175. fpga_pgm_fn,
  176. fpga_clk_fn,
  177. fpga_init_fn,
  178. fpga_done_fn,
  179. fpga_wr_fn,
  180. fpga_post_config_fn,
  181. };
  182. Xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
  183. (void *)&mt_ventoux_fpga_fns, 0);
  184. /* Initialize the FPGA */
  185. static void mt_ventoux_init_fpga(void)
  186. {
  187. fpga_pre_config_fn(0);
  188. /* Setting CS1 for FPGA access */
  189. enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1],
  190. FPGA_BASE_ADDR, GPMC_SIZE_128M);
  191. fpga_init();
  192. fpga_add(fpga_xilinx, &fpga);
  193. }
  194. /*
  195. * Routine: board_init
  196. * Description: Early hardware init.
  197. */
  198. int board_init(void)
  199. {
  200. gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  201. /* boot param addr */
  202. gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  203. mt_ventoux_init_fpga();
  204. /* GPIO_140: speaker #mute */
  205. MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4))
  206. /* GPIO_141: Buzz Hi */
  207. MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4))
  208. /* Turning off the buzzer */
  209. gpio_request(BUZZER, "BUZZER_MUTE");
  210. gpio_request(SPEAKER, "SPEAKER");
  211. gpio_direction_output(BUZZER, 0);
  212. gpio_direction_output(SPEAKER, 0);
  213. /* Activate USB power */
  214. gpio_request(USB1_PWR, "USB1_PWR");
  215. gpio_request(USB2_PWR, "USB2_PWR");
  216. gpio_direction_output(USB1_PWR, 1);
  217. gpio_direction_output(USB2_PWR, 1);
  218. return 0;
  219. }
  220. #ifndef CONFIG_SPL_BUILD
  221. int misc_init_r(void)
  222. {
  223. char *eth_addr;
  224. struct tam3517_module_info info;
  225. int ret;
  226. TAM3517_READ_EEPROM(&info, ret);
  227. dieid_num_r();
  228. if (ret)
  229. return 0;
  230. eth_addr = getenv("ethaddr");
  231. if (!eth_addr)
  232. TAM3517_READ_MAC_FROM_EEPROM(&info);
  233. TAM3517_PRINT_SOM_INFO(&info);
  234. return 0;
  235. }
  236. #endif
  237. /*
  238. * Routine: set_muxconf_regs
  239. * Description: Setting up the configuration Mux registers specific to the
  240. * hardware. Many pins need to be moved from protect to primary
  241. * mode.
  242. */
  243. void set_muxconf_regs(void)
  244. {
  245. MUX_MT_VENTOUX();
  246. }
  247. /*
  248. * Initializes on-chip ethernet controllers.
  249. * to override, implement board_eth_init()
  250. */
  251. int board_eth_init(bd_t *bis)
  252. {
  253. davinci_emac_initialize();
  254. return 0;
  255. }
  256. #if defined(CONFIG_OMAP_HSMMC) && \
  257. !defined(CONFIG_SPL_BUILD)
  258. int board_mmc_init(bd_t *bis)
  259. {
  260. return omap_mmc_init(0, 0, 0, -1, -1);
  261. }
  262. #endif
  263. #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
  264. int board_video_init(void)
  265. {
  266. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  267. struct panel_config *panel = &lcd_cfg[0];
  268. char *s;
  269. u32 index = 0;
  270. void *fb;
  271. fb = (void *)0x88000000;
  272. s = getenv("panel");
  273. if (s) {
  274. index = simple_strtoul(s, NULL, 10);
  275. if (index < ARRAY_SIZE(lcd_cfg))
  276. panel = &lcd_cfg[index];
  277. else
  278. return 0;
  279. }
  280. panel->frame_buffer = fb;
  281. printf("Panel: %dx%d\n", panel_resolution[index].xres,
  282. panel_resolution[index].yres);
  283. panel->lcd_size = (panel_resolution[index].yres - 1) << 16 |
  284. (panel_resolution[index].xres - 1);
  285. gpio_request(LCD_PWR, "LCD Power");
  286. gpio_request(LCD_PON_PIN, "LCD Pon");
  287. gpio_direction_output(LCD_PWR, 0);
  288. gpio_direction_output(LCD_PON_PIN, 1);
  289. setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
  290. setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
  291. omap3_dss_panel_config(panel);
  292. omap3_dss_enable();
  293. return 0;
  294. }
  295. #endif