fpga.c 6.5 KB

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  1. /*
  2. * Copyright (C) 2012 Stefan Roese <sr@denx.de>
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <common.h>
  23. #include <spartan3.h>
  24. #include <command.h>
  25. #include <asm/gpio.h>
  26. #include <asm/io.h>
  27. #include <asm/arch/hardware.h>
  28. #include <asm/arch/spr_misc.h>
  29. #include <asm/arch/spr_ssp.h>
  30. /*
  31. * FPGA program pin configuration on X600:
  32. *
  33. * Only PROG and DONE are connected to GPIOs. INIT is not connected to the
  34. * SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use
  35. * 16bit serial writes via this SSP port to write the data bits into the
  36. * FPGA.
  37. */
  38. #define CONFIG_SYS_FPGA_PROG 2
  39. #define CONFIG_SYS_FPGA_DONE 3
  40. /*
  41. * Set the active-low FPGA reset signal.
  42. */
  43. static void fpga_reset(int assert)
  44. {
  45. /*
  46. * On x600 we have no means to toggle the FPGA reset signal
  47. */
  48. debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert);
  49. }
  50. /*
  51. * Set the FPGA's active-low SelectMap program line to the specified level
  52. */
  53. static int fpga_pgm_fn(int assert, int flush, int cookie)
  54. {
  55. debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert);
  56. gpio_set_value(CONFIG_SYS_FPGA_PROG, assert);
  57. return assert;
  58. }
  59. /*
  60. * Test the state of the active-low FPGA INIT line. Return 1 on INIT
  61. * asserted (low).
  62. */
  63. static int fpga_init_fn(int cookie)
  64. {
  65. static int state;
  66. debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state);
  67. /*
  68. * On x600, the FPGA INIT signal is not connected to the SoC.
  69. * We can't read the INIT status. Let's return the "correct"
  70. * INIT signal state generated via a local state-machine.
  71. */
  72. if (++state == 1) {
  73. return 1;
  74. } else {
  75. state = 0;
  76. return 0;
  77. }
  78. }
  79. /*
  80. * Test the state of the active-high FPGA DONE pin
  81. */
  82. static int fpga_done_fn(int cookie)
  83. {
  84. struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
  85. /*
  86. * Wait for Tx-FIFO to become empty before looking for DONE
  87. */
  88. while (!(readl(&ssp->sspsr) & SSPSR_TFE))
  89. ;
  90. if (gpio_get_value(CONFIG_SYS_FPGA_DONE))
  91. return 1;
  92. else
  93. return 0;
  94. }
  95. /*
  96. * FPGA pre-configuration function. Just make sure that
  97. * FPGA reset is asserted to keep the FPGA from starting up after
  98. * configuration.
  99. */
  100. static int fpga_pre_config_fn(int cookie)
  101. {
  102. debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
  103. fpga_reset(true);
  104. return 0;
  105. }
  106. /*
  107. * FPGA post configuration function. Blip the FPGA reset line and then see if
  108. * the FPGA appears to be running.
  109. */
  110. static int fpga_post_config_fn(int cookie)
  111. {
  112. int rc = 0;
  113. debug("%s:%d: FPGA post configuration\n", __func__, __LINE__);
  114. fpga_reset(true);
  115. udelay(100);
  116. fpga_reset(false);
  117. udelay(100);
  118. return rc;
  119. }
  120. static int fpga_clk_fn(int assert_clk, int flush, int cookie)
  121. {
  122. /*
  123. * No dedicated clock signal on x600 (data & clock generated)
  124. * in SSP interface. So we don't have to do anything here.
  125. */
  126. return assert_clk;
  127. }
  128. static int fpga_wr_fn(int assert_write, int flush, int cookie)
  129. {
  130. struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
  131. static int count;
  132. static u16 data;
  133. /*
  134. * First collect 16 bits of data
  135. */
  136. data = data << 1;
  137. if (assert_write)
  138. data |= 1;
  139. /*
  140. * If 16 bits are not available, return for more bits
  141. */
  142. count++;
  143. if (count != 16)
  144. return assert_write;
  145. count = 0;
  146. /*
  147. * Wait for Tx-FIFO to become ready
  148. */
  149. while (!(readl(&ssp->sspsr) & SSPSR_TNF))
  150. ;
  151. /* Send 16 bits to FPGA via SSP bus */
  152. writel(data, &ssp->sspdr);
  153. return assert_write;
  154. }
  155. static Xilinx_Spartan3_Slave_Serial_fns x600_fpga_fns = {
  156. fpga_pre_config_fn,
  157. fpga_pgm_fn,
  158. fpga_clk_fn,
  159. fpga_init_fn,
  160. fpga_done_fn,
  161. fpga_wr_fn,
  162. fpga_post_config_fn,
  163. };
  164. static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
  165. XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0)
  166. };
  167. /*
  168. * Initialize the SelectMap interface. We assume that the mode and the
  169. * initial state of all of the port pins have already been set!
  170. */
  171. static void fpga_serialslave_init(void)
  172. {
  173. debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__);
  174. fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */
  175. }
  176. static int expi_setup(int freq)
  177. {
  178. struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  179. int pll2_m, pll2_n, pll2_p, expi_x, expi_y;
  180. pll2_m = (freq * 2) / 1000;
  181. pll2_n = 15;
  182. pll2_p = 1;
  183. expi_x = 1;
  184. expi_y = 2;
  185. /*
  186. * Disable reset, Low compression, Disable retiming, Enable Expi,
  187. * Enable soft reset, DMA, PLL2, Internal
  188. */
  189. writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST |
  190. EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 |
  191. EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24),
  192. &misc->expi_clk_cfg);
  193. /*
  194. * 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters,
  195. * Enable PLL2, Disable reset
  196. */
  197. writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq);
  198. writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE |
  199. PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl);
  200. /*
  201. * Disable soft reset
  202. */
  203. clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST);
  204. return 0;
  205. }
  206. /*
  207. * Initialize the fpga
  208. */
  209. int x600_init_fpga(void)
  210. {
  211. struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
  212. struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  213. /* Enable SSP2 clock */
  214. writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB,
  215. &misc->periph1_clken);
  216. /* Set EXPI clock to 45 MHz */
  217. expi_setup(45000);
  218. /* Configure GPIO directions */
  219. gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0);
  220. gpio_direction_input(CONFIG_SYS_FPGA_DONE);
  221. writel(SSPCR0_DSS_16BITS, &ssp->sspcr0);
  222. writel(SSPCR1_SSE, &ssp->sspcr1);
  223. /*
  224. * Set lowest prescale divisor value (CPSDVSR) of 2 for max download
  225. * speed.
  226. *
  227. * Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1))
  228. * With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz.
  229. */
  230. writel(2, &ssp->sspcpsr);
  231. fpga_init();
  232. fpga_serialslave_init();
  233. debug("%s:%d: Adding fpga 0\n", __func__, __LINE__);
  234. fpga_add(fpga_xilinx, &fpga[0]);
  235. return 0;
  236. }