pip405.c 24 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. *
  24. * TODO: clean-up
  25. */
  26. #include <common.h>
  27. #include "pip405.h"
  28. #include <asm/processor.h>
  29. #include <i2c.h>
  30. #include <stdio_dev.h>
  31. #include "../common/isa.h"
  32. #include "../common/common_util.h"
  33. DECLARE_GLOBAL_DATA_PTR;
  34. #undef SDRAM_DEBUG
  35. /* stdlib.h causes some compatibility problems; should fixe these! -- wd */
  36. #ifndef __ldiv_t_defined
  37. typedef struct {
  38. long int quot; /* Quotient */
  39. long int rem; /* Remainder */
  40. } ldiv_t;
  41. extern ldiv_t ldiv (long int __numer, long int __denom);
  42. # define __ldiv_t_defined 1
  43. #endif
  44. typedef enum {
  45. SDRAM_NO_ERR,
  46. SDRAM_SPD_COMM_ERR,
  47. SDRAM_SPD_CHKSUM_ERR,
  48. SDRAM_UNSUPPORTED_ERR,
  49. SDRAM_UNKNOWN_ERR
  50. } SDRAM_ERR;
  51. typedef struct {
  52. const unsigned char mode;
  53. const unsigned char row;
  54. const unsigned char col;
  55. const unsigned char bank;
  56. } SDRAM_SETUP;
  57. static const SDRAM_SETUP sdram_setup_table[] = {
  58. {1, 11, 9, 2},
  59. {1, 11, 10, 2},
  60. {2, 12, 9, 4},
  61. {2, 12, 10, 4},
  62. {3, 13, 9, 4},
  63. {3, 13, 10, 4},
  64. {3, 13, 11, 4},
  65. {4, 12, 8, 2},
  66. {4, 12, 8, 4},
  67. {5, 11, 8, 2},
  68. {5, 11, 8, 4},
  69. {6, 13, 8, 2},
  70. {6, 13, 8, 4},
  71. {7, 13, 9, 2},
  72. {7, 13, 10, 2},
  73. {0, 0, 0, 0}
  74. };
  75. static const unsigned char cal_indextable[] = {
  76. 9, 23, 25
  77. };
  78. /*
  79. * translate ns.ns/10 coding of SPD timing values
  80. * into 10 ps unit values
  81. */
  82. unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version)
  83. {
  84. unsigned short ns, ns10;
  85. /* isolate upper nibble */
  86. ns = (spd_byte >> 4) & 0x0F;
  87. /* isolate lower nibble */
  88. ns10 = (spd_byte & 0x0F);
  89. return (ns * 100 + ns10 * 10);
  90. }
  91. /*
  92. * translate ns.ns/4 coding of SPD timing values
  93. * into 10 ps unit values
  94. */
  95. unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version)
  96. {
  97. unsigned short ns, ns4;
  98. /* isolate upper 6 bits */
  99. ns = (spd_byte >> 2) & 0x3F;
  100. /* isloate lower 2 bits */
  101. ns4 = (spd_byte & 0x03);
  102. return (ns * 100 + ns4 * 25);
  103. }
  104. /*
  105. * translate ns coding of SPD timing values
  106. * into 10 ps unit values
  107. */
  108. unsigned short NSto10PS (unsigned char spd_byte)
  109. {
  110. return (spd_byte * 100);
  111. }
  112. void SDRAM_err (const char *s)
  113. {
  114. #ifndef SDRAM_DEBUG
  115. (void) get_clocks ();
  116. gd->baudrate = 9600;
  117. serial_init ();
  118. #endif
  119. serial_puts ("\n");
  120. serial_puts (s);
  121. serial_puts ("\n enable SDRAM_DEBUG for more info\n");
  122. for (;;);
  123. }
  124. #ifdef SDRAM_DEBUG
  125. void write_hex (unsigned char i)
  126. {
  127. char cc;
  128. cc = i >> 4;
  129. cc &= 0xf;
  130. if (cc > 9)
  131. serial_putc (cc + 55);
  132. else
  133. serial_putc (cc + 48);
  134. cc = i & 0xf;
  135. if (cc > 9)
  136. serial_putc (cc + 55);
  137. else
  138. serial_putc (cc + 48);
  139. }
  140. void write_4hex (unsigned long val)
  141. {
  142. write_hex ((unsigned char) (val >> 24));
  143. write_hex ((unsigned char) (val >> 16));
  144. write_hex ((unsigned char) (val >> 8));
  145. write_hex ((unsigned char) val);
  146. }
  147. #endif
  148. int board_early_init_f (void)
  149. {
  150. unsigned char datain[128];
  151. unsigned long sdram_size = 0;
  152. SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table;
  153. unsigned long memclk;
  154. unsigned long tmemclk = 0;
  155. unsigned long tmp, bank, baseaddr, bank_size;
  156. unsigned short i;
  157. unsigned char rows, cols, banks, sdram_banks, density;
  158. unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks,
  159. trc_clocks;
  160. unsigned char cal_index, cal_val, spd_version, spd_chksum;
  161. unsigned char buf[8];
  162. #ifdef SDRAM_DEBUG
  163. unsigned char tctp_clocks;
  164. #endif
  165. /* set up the config port */
  166. mtdcr (EBC0_CFGADDR, PB7AP);
  167. mtdcr (EBC0_CFGDATA, CONFIG_PORT_AP);
  168. mtdcr (EBC0_CFGADDR, PB7CR);
  169. mtdcr (EBC0_CFGDATA, CONFIG_PORT_CR);
  170. memclk = get_bus_freq (tmemclk);
  171. tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
  172. #ifdef SDRAM_DEBUG
  173. (void) get_clocks ();
  174. gd->baudrate = 9600;
  175. serial_init ();
  176. serial_puts ("\nstart SDRAM Setup\n");
  177. #endif
  178. /* Read Serial Presence Detect Information */
  179. i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  180. for (i = 0; i < 128; i++)
  181. datain[i] = 127;
  182. i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128);
  183. #ifdef SDRAM_DEBUG
  184. serial_puts ("\ni2c_read returns ");
  185. write_hex (i);
  186. serial_puts ("\n");
  187. #endif
  188. #ifdef SDRAM_DEBUG
  189. for (i = 0; i < 128; i++) {
  190. write_hex (datain[i]);
  191. serial_puts (" ");
  192. if (((i + 1) % 16) == 0)
  193. serial_puts ("\n");
  194. }
  195. serial_puts ("\n");
  196. #endif
  197. spd_chksum = 0;
  198. for (i = 0; i < 63; i++) {
  199. spd_chksum += datain[i];
  200. } /* endfor */
  201. if (datain[63] != spd_chksum) {
  202. #ifdef SDRAM_DEBUG
  203. serial_puts ("SPD chksum: 0x");
  204. write_hex (datain[63]);
  205. serial_puts (" != calc. chksum: 0x");
  206. write_hex (spd_chksum);
  207. serial_puts ("\n");
  208. #endif
  209. SDRAM_err ("SPD checksum Error");
  210. }
  211. /* SPD seems to be ok, use it */
  212. /* get SPD version */
  213. spd_version = datain[62];
  214. /* do some sanity checks on the kind of RAM */
  215. if ((datain[0] < 0x80) || /* less than 128 valid bytes in SPD */
  216. (datain[2] != 0x04) || /* if not SDRAM */
  217. (!((datain[6] == 0x40) || (datain[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */
  218. (datain[7] != 0x00) || (datain[8] != 0x01) || /* or not LVTTL signal levels */
  219. (datain[126] == 0x66)) /* or a 66MHz modules */
  220. SDRAM_err ("unsupported SDRAM");
  221. #ifdef SDRAM_DEBUG
  222. serial_puts ("SDRAM sanity ok\n");
  223. #endif
  224. /* get number of rows/cols/banks out of byte 3+4+5 */
  225. rows = datain[3];
  226. cols = datain[4];
  227. banks = datain[5];
  228. /* get number of SDRAM banks out of byte 17 and
  229. supported CAS latencies out of byte 18 */
  230. sdram_banks = datain[17];
  231. supported_cal = datain[18] & ~0x81;
  232. while (t->mode != 0) {
  233. if ((t->row == rows) && (t->col == cols)
  234. && (t->bank == sdram_banks))
  235. break;
  236. t++;
  237. } /* endwhile */
  238. #ifdef SDRAM_DEBUG
  239. serial_puts ("rows: ");
  240. write_hex (rows);
  241. serial_puts (" cols: ");
  242. write_hex (cols);
  243. serial_puts (" banks: ");
  244. write_hex (banks);
  245. serial_puts (" mode: ");
  246. write_hex (t->mode);
  247. serial_puts ("\n");
  248. #endif
  249. if (t->mode == 0)
  250. SDRAM_err ("unsupported SDRAM");
  251. /* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */
  252. #ifdef SDRAM_DEBUG
  253. serial_puts ("tRP: ");
  254. write_hex (datain[27]);
  255. serial_puts ("\ntRCD: ");
  256. write_hex (datain[29]);
  257. serial_puts ("\ntRAS: ");
  258. write_hex (datain[30]);
  259. serial_puts ("\n");
  260. #endif
  261. trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk;
  262. trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk;
  263. tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk;
  264. density = datain[31];
  265. /* trc_clocks is sum of trp_clocks + tras_clocks */
  266. trc_clocks = trp_clocks + tras_clocks;
  267. #ifdef SDRAM_DEBUG
  268. /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
  269. tctp_clocks =
  270. ((NSto10PS (datain[30]) - NSto10PS (datain[29])) +
  271. (tmemclk - 1)) / tmemclk;
  272. serial_puts ("c_RP: ");
  273. write_hex (trp_clocks);
  274. serial_puts ("\nc_RCD: ");
  275. write_hex (trcd_clocks);
  276. serial_puts ("\nc_RAS: ");
  277. write_hex (tras_clocks);
  278. serial_puts ("\nc_RC: (RP+RAS): ");
  279. write_hex (trc_clocks);
  280. serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): ");
  281. write_hex (tctp_clocks);
  282. serial_puts ("\nt_CTP: RAS - RCD: ");
  283. write_hex ((unsigned
  284. char) ((NSto10PS (datain[30]) -
  285. NSto10PS (datain[29])) >> 8));
  286. write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29])));
  287. serial_puts ("\ntmemclk: ");
  288. write_hex ((unsigned char) (tmemclk >> 8));
  289. write_hex ((unsigned char) (tmemclk));
  290. serial_puts ("\n");
  291. #endif
  292. cal_val = 255;
  293. for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) {
  294. /* is this CAS latency supported ? */
  295. if ((supported_cal >> i) & 0x01) {
  296. buf[0] = datain[cal_indextable[cal_index]];
  297. if (cal_index < 2) {
  298. if (NS10to10PS (buf[0], spd_version) <= tmemclk)
  299. cal_val = i;
  300. } else {
  301. /* SPD bytes 25+26 have another format */
  302. if (NS4to10PS (buf[0], spd_version) <= tmemclk)
  303. cal_val = i;
  304. } /* endif */
  305. cal_index++;
  306. } /* endif */
  307. } /* endfor */
  308. #ifdef SDRAM_DEBUG
  309. serial_puts ("CAL: ");
  310. write_hex (cal_val + 1);
  311. serial_puts ("\n");
  312. #endif
  313. if (cal_val == 255)
  314. SDRAM_err ("unsupported SDRAM");
  315. /* get SDRAM timing register */
  316. mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
  317. tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
  318. /* insert CASL value */
  319. /* tmp |= ((unsigned long)cal_val) << 23; */
  320. tmp |= ((unsigned long) cal_val) << 23;
  321. /* insert PTA value */
  322. tmp |= ((unsigned long) (trp_clocks - 1)) << 18;
  323. /* insert CTP value */
  324. /* tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */
  325. tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16;
  326. /* insert LDF (always 01) */
  327. tmp |= ((unsigned long) 0x01) << 14;
  328. /* insert RFTA value */
  329. tmp |= ((unsigned long) (trc_clocks - 4)) << 2;
  330. /* insert RCD value */
  331. tmp |= ((unsigned long) (trcd_clocks - 1)) << 0;
  332. #ifdef SDRAM_DEBUG
  333. serial_puts ("sdtr: ");
  334. write_4hex (tmp);
  335. serial_puts ("\n");
  336. #endif
  337. /* write SDRAM timing register */
  338. mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
  339. mtdcr (SDRAM0_CFGDATA, tmp);
  340. baseaddr = CONFIG_SYS_SDRAM_BASE;
  341. bank_size = (((unsigned long) density) << 22) / 2;
  342. /* insert AM value */
  343. tmp = ((unsigned long) t->mode - 1) << 13;
  344. /* insert SZ value; */
  345. switch (bank_size) {
  346. case 0x00400000:
  347. tmp |= ((unsigned long) 0x00) << 17;
  348. break;
  349. case 0x00800000:
  350. tmp |= ((unsigned long) 0x01) << 17;
  351. break;
  352. case 0x01000000:
  353. tmp |= ((unsigned long) 0x02) << 17;
  354. break;
  355. case 0x02000000:
  356. tmp |= ((unsigned long) 0x03) << 17;
  357. break;
  358. case 0x04000000:
  359. tmp |= ((unsigned long) 0x04) << 17;
  360. break;
  361. case 0x08000000:
  362. tmp |= ((unsigned long) 0x05) << 17;
  363. break;
  364. case 0x10000000:
  365. tmp |= ((unsigned long) 0x06) << 17;
  366. break;
  367. default:
  368. SDRAM_err ("unsupported SDRAM");
  369. } /* endswitch */
  370. /* get SDRAM bank 0 register */
  371. mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
  372. bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
  373. bank |= (baseaddr | tmp | 0x01);
  374. #ifdef SDRAM_DEBUG
  375. serial_puts ("bank0: baseaddr: ");
  376. write_4hex (baseaddr);
  377. serial_puts (" banksize: ");
  378. write_4hex (bank_size);
  379. serial_puts (" mb0cf: ");
  380. write_4hex (bank);
  381. serial_puts ("\n");
  382. #endif
  383. baseaddr += bank_size;
  384. sdram_size += bank_size;
  385. /* write SDRAM bank 0 register */
  386. mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
  387. mtdcr (SDRAM0_CFGDATA, bank);
  388. /* get SDRAM bank 1 register */
  389. mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
  390. bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
  391. sdram_size = 0;
  392. #ifdef SDRAM_DEBUG
  393. serial_puts ("bank1: baseaddr: ");
  394. write_4hex (baseaddr);
  395. serial_puts (" banksize: ");
  396. write_4hex (bank_size);
  397. #endif
  398. if (banks == 2) {
  399. bank |= (baseaddr | tmp | 0x01);
  400. baseaddr += bank_size;
  401. sdram_size += bank_size;
  402. } /* endif */
  403. #ifdef SDRAM_DEBUG
  404. serial_puts (" mb1cf: ");
  405. write_4hex (bank);
  406. serial_puts ("\n");
  407. #endif
  408. /* write SDRAM bank 1 register */
  409. mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
  410. mtdcr (SDRAM0_CFGDATA, bank);
  411. /* get SDRAM bank 2 register */
  412. mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
  413. bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
  414. bank |= (baseaddr | tmp | 0x01);
  415. #ifdef SDRAM_DEBUG
  416. serial_puts ("bank2: baseaddr: ");
  417. write_4hex (baseaddr);
  418. serial_puts (" banksize: ");
  419. write_4hex (bank_size);
  420. serial_puts (" mb2cf: ");
  421. write_4hex (bank);
  422. serial_puts ("\n");
  423. #endif
  424. baseaddr += bank_size;
  425. sdram_size += bank_size;
  426. /* write SDRAM bank 2 register */
  427. mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
  428. mtdcr (SDRAM0_CFGDATA, bank);
  429. /* get SDRAM bank 3 register */
  430. mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
  431. bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
  432. #ifdef SDRAM_DEBUG
  433. serial_puts ("bank3: baseaddr: ");
  434. write_4hex (baseaddr);
  435. serial_puts (" banksize: ");
  436. write_4hex (bank_size);
  437. #endif
  438. if (banks == 2) {
  439. bank |= (baseaddr | tmp | 0x01);
  440. baseaddr += bank_size;
  441. sdram_size += bank_size;
  442. }
  443. /* endif */
  444. #ifdef SDRAM_DEBUG
  445. serial_puts (" mb3cf: ");
  446. write_4hex (bank);
  447. serial_puts ("\n");
  448. #endif
  449. /* write SDRAM bank 3 register */
  450. mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
  451. mtdcr (SDRAM0_CFGDATA, bank);
  452. /* get SDRAM refresh interval register */
  453. mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
  454. tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
  455. if (tmemclk < NSto10PS (16))
  456. tmp |= 0x05F00000;
  457. else
  458. tmp |= 0x03F80000;
  459. /* write SDRAM refresh interval register */
  460. mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
  461. mtdcr (SDRAM0_CFGDATA, tmp);
  462. /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
  463. mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
  464. tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000;
  465. mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
  466. mtdcr (SDRAM0_CFGDATA, tmp);
  467. /*-------------------------------------------------------------------------+
  468. | Interrupt controller setup for the PIP405 board.
  469. | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
  470. | IRQ 16 405GP internally generated; active low; level sensitive
  471. | IRQ 17-24 RESERVED
  472. | IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive
  473. | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
  474. | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
  475. | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
  476. | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
  477. | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
  478. | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
  479. | Note for PIP405 board:
  480. | An interrupt taken for the SouthBridge (IRQ 25) indicates that
  481. | the Interrupt Controller in the South Bridge has caused the
  482. | interrupt. The IC must be read to determine which device
  483. | caused the interrupt.
  484. |
  485. +-------------------------------------------------------------------------*/
  486. mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
  487. mtdcr (UIC0ER, 0x00000000); /* disable all ints */
  488. mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */
  489. mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
  490. mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
  491. mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
  492. mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
  493. return 0;
  494. }
  495. int board_early_init_r(void)
  496. {
  497. int mode;
  498. /*
  499. * since we are relocated, we can finally enable i-cache
  500. * and set up the flash CS correctly
  501. */
  502. icache_enable();
  503. setup_cs_reloc();
  504. /* get and display boot mode */
  505. mode = get_boot_mode();
  506. if (mode & BOOT_PCI)
  507. printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ?
  508. "MPS" : "Flash");
  509. else
  510. printf("%s Boot\n", (mode & BOOT_MPS) ?
  511. "MPS" : "Flash");
  512. return 0;
  513. }
  514. /* ------------------------------------------------------------------------- */
  515. /*
  516. * Check Board Identity:
  517. */
  518. int checkboard (void)
  519. {
  520. char s[50];
  521. unsigned char bc;
  522. int i;
  523. backup_t *b = (backup_t *) s;
  524. puts ("Board: ");
  525. i = getenv_f("serial#", (char *)s, 32);
  526. if ((i == 0) || strncmp ((char *)s, "PIP405", 6)) {
  527. get_backup_values (b);
  528. if (strncmp (b->signature, "MPL\0", 4) != 0) {
  529. puts ("### No HW ID - assuming PIP405");
  530. } else {
  531. b->serial_name[6] = 0;
  532. printf ("%s SN: %s", b->serial_name,
  533. &b->serial_name[7]);
  534. }
  535. } else {
  536. s[6] = 0;
  537. printf ("%s SN: %s", s, &s[7]);
  538. }
  539. bc = in8 (CONFIG_PORT_ADDR);
  540. printf (" Boot Config: 0x%x\n", bc);
  541. return (0);
  542. }
  543. /* ------------------------------------------------------------------------- */
  544. /* ------------------------------------------------------------------------- */
  545. /*
  546. initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
  547. the necessary info for SDRAM controller configuration
  548. */
  549. /* ------------------------------------------------------------------------- */
  550. /* ------------------------------------------------------------------------- */
  551. static int test_dram (unsigned long ramsize);
  552. phys_size_t initdram (int board_type)
  553. {
  554. unsigned long bank_reg[4], tmp, bank_size;
  555. int i, ds;
  556. unsigned long TotalSize;
  557. ds = 0;
  558. /* since the DRAM controller is allready set up,
  559. * calculate the size with the bank registers
  560. */
  561. mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
  562. bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
  563. mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
  564. bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
  565. mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
  566. bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
  567. mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
  568. bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
  569. TotalSize = 0;
  570. for (i = 0; i < 4; i++) {
  571. if ((bank_reg[i] & 0x1) == 0x1) {
  572. tmp = (bank_reg[i] >> 17) & 0x7;
  573. bank_size = 4 << tmp;
  574. TotalSize += bank_size;
  575. } else
  576. ds = 1;
  577. }
  578. if (ds == 1)
  579. printf ("single-sided DIMM ");
  580. else
  581. printf ("double-sided DIMM ");
  582. test_dram (TotalSize * 1024 * 1024);
  583. /* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */
  584. (void) get_clocks();
  585. if (gd->cpu_clk > 220000000)
  586. TotalSize /= 2;
  587. return (TotalSize * 1024 * 1024);
  588. }
  589. /* ------------------------------------------------------------------------- */
  590. static int test_dram (unsigned long ramsize)
  591. {
  592. /* not yet implemented */
  593. return (1);
  594. }
  595. int misc_init_r (void)
  596. {
  597. /* adjust flash start and size as well as the offset */
  598. gd->bd->bi_flashstart=0-flash_info[0].size;
  599. gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
  600. gd->bd->bi_flashoffset=0;
  601. /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
  602. if (mfdcr(CPC0_PSR) & PSR_ROM_LOC)
  603. mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
  604. return (0);
  605. }
  606. /***************************************************************************
  607. * some helping routines
  608. */
  609. int overwrite_console (void)
  610. {
  611. /* return true if console should be overwritten */
  612. return in8(CONFIG_PORT_ADDR) & 0x1;
  613. }
  614. extern int isa_init (void);
  615. void print_pip405_rev (void)
  616. {
  617. unsigned char part, vers, cfg;
  618. part = in8 (PLD_PART_REG);
  619. vers = in8 (PLD_VERS_REG);
  620. cfg = in8 (PLD_BOARD_CFG_REG);
  621. printf ("Rev: PIP405-%d Rev %c PLD%d %d PLD%d %d\n",
  622. 16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf,
  623. vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf);
  624. }
  625. extern void check_env(void);
  626. int last_stage_init (void)
  627. {
  628. print_pip405_rev ();
  629. isa_init ();
  630. stdio_print_current_devices ();
  631. check_env();
  632. return 0;
  633. }
  634. /************************************************************************
  635. * Print PIP405 Info
  636. ************************************************************************/
  637. void print_pip405_info (void)
  638. {
  639. unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr,
  640. compwr, nicvga, scsirst;
  641. part = in8 (PLD_PART_REG);
  642. vers = in8 (PLD_VERS_REG);
  643. cfg = in8 (PLD_BOARD_CFG_REG);
  644. ledu = in8 (PLD_LED_USER_REG);
  645. sysman = in8 (PLD_SYS_MAN_REG);
  646. flashcom = in8 (PLD_FLASH_COM_REG);
  647. can = in8 (PLD_CAN_REG);
  648. serpwr = in8 (PLD_SER_PWR_REG);
  649. compwr = in8 (PLD_COM_PWR_REG);
  650. nicvga = in8 (PLD_NIC_VGA_REG);
  651. scsirst = in8 (PLD_SCSI_RST_REG);
  652. printf ("PLD Part %d version %d\n",
  653. part & 0xf, vers & 0xf);
  654. printf ("PLD Part %d version %d\n",
  655. (part >> 4) & 0xf, (vers >> 4) & 0xf);
  656. printf ("Board Revision %c\n", (cfg & 0xf) + 'A');
  657. printf ("Population Options %d %d %d %d\n",
  658. (cfg >> 4) & 0x1, (cfg >> 5) & 0x1,
  659. (cfg >> 6) & 0x1, (cfg >> 7) & 0x1);
  660. printf ("User LED0 %s User LED1 %s\n",
  661. ((ledu & 0x1) == 0x1) ? "on" : "off",
  662. ((ledu & 0x2) == 0x2) ? "on" : "off");
  663. printf ("Additionally Options %d %d\n",
  664. (ledu >> 2) & 0x1, (ledu >> 3) & 0x1);
  665. printf ("User Config Switch %d %d %d %d\n",
  666. (ledu >> 4) & 0x1, (ledu >> 5) & 0x1,
  667. (ledu >> 6) & 0x1, (ledu >> 7) & 0x1);
  668. switch (sysman & 0x3) {
  669. case 0:
  670. printf ("PCI Clocks are running\n");
  671. break;
  672. case 1:
  673. printf ("PCI Clocks are stopped in POS State\n");
  674. break;
  675. case 2:
  676. printf ("PCI Clocks are stopped when PCI_STP# is asserted\n");
  677. break;
  678. case 3:
  679. printf ("PCI Clocks are stopped\n");
  680. break;
  681. }
  682. switch ((sysman >> 2) & 0x3) {
  683. case 0:
  684. printf ("Main Clocks are running\n");
  685. break;
  686. case 1:
  687. printf ("Main Clocks are stopped in POS State\n");
  688. break;
  689. case 2:
  690. case 3:
  691. printf ("PCI Clocks are stopped\n");
  692. break;
  693. }
  694. printf ("INIT asserts %sINT2# (SMI)\n",
  695. ((sysman & 0x10) == 0x10) ? "" : "not ");
  696. printf ("INIT asserts %sINT1# (NMI)\n",
  697. ((sysman & 0x20) == 0x20) ? "" : "not ");
  698. printf ("INIT occured %d\n", (sysman >> 6) & 0x1);
  699. printf ("SER1 is routed to %s\n",
  700. ((flashcom & 0x1) == 0x1) ? "RS485" : "RS232");
  701. printf ("COM2 is routed to %s\n",
  702. ((flashcom & 0x2) == 0x2) ? "RS485" : "RS232");
  703. printf ("RS485 is configured as %s duplex\n",
  704. ((flashcom & 0x4) == 0x4) ? "full" : "half");
  705. printf ("RS485 is connected to %s\n",
  706. ((flashcom & 0x8) == 0x8) ? "COM1" : "COM2");
  707. printf ("SER1 uses handshakes %s\n",
  708. ((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS");
  709. printf ("Bootflash is %swriteprotected\n",
  710. ((flashcom & 0x20) == 0x20) ? "not " : "");
  711. printf ("Bootflash VPP is %s\n",
  712. ((flashcom & 0x40) == 0x40) ? "on" : "off");
  713. printf ("Bootsector is %swriteprotected\n",
  714. ((flashcom & 0x80) == 0x80) ? "not " : "");
  715. switch ((can) & 0x3) {
  716. case 0:
  717. printf ("CAN Controller is on address 0x1000..0x10FF\n");
  718. break;
  719. case 1:
  720. printf ("CAN Controller is on address 0x8000..0x80FF\n");
  721. break;
  722. case 2:
  723. printf ("CAN Controller is on address 0xE000..0xE0FF\n");
  724. break;
  725. case 3:
  726. printf ("CAN Controller is disabled\n");
  727. break;
  728. }
  729. switch ((can >> 2) & 0x3) {
  730. case 0:
  731. printf ("CAN Controller Reset is ISA Reset\n");
  732. break;
  733. case 1:
  734. printf ("CAN Controller Reset is ISA Reset and POS State\n");
  735. break;
  736. case 2:
  737. case 3:
  738. printf ("CAN Controller is in reset\n");
  739. break;
  740. }
  741. if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13))
  742. printf ("CAN Interrupt is disabled\n");
  743. else
  744. printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf);
  745. switch (serpwr & 0x3) {
  746. case 0:
  747. printf ("SER0 Drivers are enabled\n");
  748. break;
  749. case 1:
  750. printf ("SER0 Drivers are disabled in the POS state\n");
  751. break;
  752. case 2:
  753. case 3:
  754. printf ("SER0 Drivers are disabled\n");
  755. break;
  756. }
  757. switch ((serpwr >> 2) & 0x3) {
  758. case 0:
  759. printf ("SER1 Drivers are enabled\n");
  760. break;
  761. case 1:
  762. printf ("SER1 Drivers are disabled in the POS state\n");
  763. break;
  764. case 2:
  765. case 3:
  766. printf ("SER1 Drivers are disabled\n");
  767. break;
  768. }
  769. switch (compwr & 0x3) {
  770. case 0:
  771. printf ("COM1 Drivers are enabled\n");
  772. break;
  773. case 1:
  774. printf ("COM1 Drivers are disabled in the POS state\n");
  775. break;
  776. case 2:
  777. case 3:
  778. printf ("COM1 Drivers are disabled\n");
  779. break;
  780. }
  781. switch ((compwr >> 2) & 0x3) {
  782. case 0:
  783. printf ("COM2 Drivers are enabled\n");
  784. break;
  785. case 1:
  786. printf ("COM2 Drivers are disabled in the POS state\n");
  787. break;
  788. case 2:
  789. case 3:
  790. printf ("COM2 Drivers are disabled\n");
  791. break;
  792. }
  793. switch ((nicvga) & 0x3) {
  794. case 0:
  795. printf ("PHY is running\n");
  796. break;
  797. case 1:
  798. printf ("PHY is in Power save mode in POS state\n");
  799. break;
  800. case 2:
  801. case 3:
  802. printf ("PHY is in Power save mode\n");
  803. break;
  804. }
  805. switch ((nicvga >> 2) & 0x3) {
  806. case 0:
  807. printf ("VGA is running\n");
  808. break;
  809. case 1:
  810. printf ("VGA is in Power save mode in POS state\n");
  811. break;
  812. case 2:
  813. case 3:
  814. printf ("VGA is in Power save mode\n");
  815. break;
  816. }
  817. printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not ");
  818. printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not ");
  819. printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1,
  820. (nicvga >> 7) & 0x1);
  821. switch ((scsirst) & 0x3) {
  822. case 0:
  823. printf ("SCSI Controller is running\n");
  824. break;
  825. case 1:
  826. printf ("SCSI Controller is in Power save mode in POS state\n");
  827. break;
  828. case 2:
  829. case 3:
  830. printf ("SCSI Controller is in Power save mode\n");
  831. break;
  832. }
  833. printf ("SCSI termination is %s\n",
  834. ((scsirst & 0x4) == 0x4) ? "disabled" : "enabled");
  835. printf ("SCSI Controller is %sreseted\n",
  836. ((scsirst & 0x10) == 0x10) ? "" : "not ");
  837. printf ("IDE disks are %sreseted\n",
  838. ((scsirst & 0x20) == 0x20) ? "" : "not ");
  839. printf ("ISA Bus is %sreseted\n",
  840. ((scsirst & 0x40) == 0x40) ? "" : "not ");
  841. printf ("Super IO is %sreseted\n",
  842. ((scsirst & 0x80) == 0x80) ? "" : "not ");
  843. }
  844. void user_led0 (unsigned char on)
  845. {
  846. if (on == true)
  847. out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1));
  848. else
  849. out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe));
  850. }
  851. void user_led1 (unsigned char on)
  852. {
  853. if (on == true)
  854. out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2));
  855. else
  856. out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd));
  857. }
  858. void ide_set_reset (int idereset)
  859. {
  860. /* if reset = 1 IDE reset will be asserted */
  861. unsigned char resreg;
  862. resreg = in8 (PLD_SCSI_RST_REG);
  863. if (idereset == 1)
  864. resreg |= 0x20;
  865. else {
  866. udelay(10000);
  867. resreg &= 0xdf;
  868. }
  869. out8 (PLD_SCSI_RST_REG, resreg);
  870. }