mip405.c 23 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. *
  24. * TODO: clean-up
  25. */
  26. /*
  27. * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM?
  28. *
  29. * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being
  30. * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum
  31. * parameters from the datasheet are:
  32. * Tclk = 7.5ns (CL = 2)
  33. * Trp = 15ns
  34. * Trc = 60ns
  35. * Trcd = 15ns
  36. * Trfc = 66ns
  37. *
  38. * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock
  39. * period is 10ns and the parameters needed for the Timing Register are:
  40. * CASL = CL = 2 clock cycles
  41. * PTA = Trp = 15ns / 10ns = 2 clock cycles
  42. * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles
  43. * LDF = 2 clock cycles (but can be extended to meet board-level timing)
  44. * RFTA = Trfc = 66ns / 10ns= 7 clock cycles
  45. * RCD = Trcd = 15ns / 10ns= 2 clock cycles
  46. *
  47. * The actual bit settings in the register would be:
  48. *
  49. * CASL = 0b01
  50. * PTA = 0b01
  51. * CTP = 0b10
  52. * LDF = 0b01
  53. * RFTA = 0b011
  54. * RCD = 0b01
  55. *
  56. * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc
  57. * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay
  58. * defined as Trc rather than Trfc.
  59. * When using DIMM modules, most but not all of the required timing parameters can be read
  60. * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc
  61. * are not available from the EEPROM
  62. */
  63. #include <common.h>
  64. #include "mip405.h"
  65. #include <asm/processor.h>
  66. #include <asm/ppc4xx.h>
  67. #include <asm/ppc4xx-i2c.h>
  68. #include <miiphy.h>
  69. #include "../common/common_util.h"
  70. #include <stdio_dev.h>
  71. #include <i2c.h>
  72. #include <rtc.h>
  73. DECLARE_GLOBAL_DATA_PTR;
  74. #undef SDRAM_DEBUG
  75. #define ENABLE_ECC /* for ecc boards */
  76. /* stdlib.h causes some compatibility problems; should fixe these! -- wd */
  77. #ifndef __ldiv_t_defined
  78. typedef struct {
  79. long int quot; /* Quotient */
  80. long int rem; /* Remainder */
  81. } ldiv_t;
  82. extern ldiv_t ldiv (long int __numer, long int __denom);
  83. # define __ldiv_t_defined 1
  84. #endif
  85. #define PLD_PART_REG PER_PLD_ADDR + 0
  86. #define PLD_VERS_REG PER_PLD_ADDR + 1
  87. #define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2
  88. #define PLD_IRQ_REG PER_PLD_ADDR + 3
  89. #define PLD_COM_MODE_REG PER_PLD_ADDR + 4
  90. #define PLD_EXT_CONF_REG PER_PLD_ADDR + 5
  91. #define MEGA_BYTE (1024*1024)
  92. typedef struct {
  93. unsigned char boardtype; /* Board revision and Population Options */
  94. unsigned char cal; /* cas Latency (will be programmend as cal-1) */
  95. unsigned char trp; /* datain27 in clocks */
  96. unsigned char trcd; /* datain29 in clocks */
  97. unsigned char tras; /* datain30 in clocks */
  98. unsigned char tctp; /* tras - trcd in clocks */
  99. unsigned char am; /* Address Mod (will be programmed as am-1) */
  100. unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
  101. unsigned char ecc; /* if true, ecc is enabled */
  102. } sdram_t;
  103. #if defined(CONFIG_MIP405T)
  104. const sdram_t sdram_table[] = {
  105. { 0x0F, /* MIP405T Rev A, 64MByte -1 Board */
  106. 3, /* Case Latenty = 3 */
  107. 3, /* trp 20ns / 7.5 ns datain[27] */
  108. 3, /* trcd 20ns /7.5 ns (datain[29]) */
  109. 6, /* tras 44ns /7.5 ns (datain[30]) */
  110. 4, /* tcpt 44 - 20ns = 24ns */
  111. 2, /* Address Mode = 2 (12x9x4) */
  112. 3, /* size value (32MByte) */
  113. 0}, /* ECC disabled */
  114. { 0xff, /* terminator */
  115. 0xff,
  116. 0xff,
  117. 0xff,
  118. 0xff,
  119. 0xff,
  120. 0xff,
  121. 0xff }
  122. };
  123. #else
  124. const sdram_t sdram_table[] = {
  125. { 0x0f, /* Rev A, 128MByte -1 Board */
  126. 3, /* Case Latenty = 3 */
  127. 3, /* trp 20ns / 7.5 ns datain[27] */
  128. 3, /* trcd 20ns /7.5 ns (datain[29]) */
  129. 6, /* tras 44ns /7.5 ns (datain[30]) */
  130. 4, /* tcpt 44 - 20ns = 24ns */
  131. 3, /* Address Mode = 3 */
  132. 5, /* size value */
  133. 1}, /* ECC enabled */
  134. { 0x07, /* Rev A, 64MByte -2 Board */
  135. 3, /* Case Latenty = 3 */
  136. 3, /* trp 20ns / 7.5 ns datain[27] */
  137. 3, /* trcd 20ns /7.5 ns (datain[29]) */
  138. 6, /* tras 44ns /7.5 ns (datain[30]) */
  139. 4, /* tcpt 44 - 20ns = 24ns */
  140. 2, /* Address Mode = 2 */
  141. 4, /* size value */
  142. 1}, /* ECC enabled */
  143. { 0x03, /* Rev A, 128MByte -4 Board */
  144. 3, /* Case Latenty = 3 */
  145. 3, /* trp 20ns / 7.5 ns datain[27] */
  146. 3, /* trcd 20ns /7.5 ns (datain[29]) */
  147. 6, /* tras 44ns /7.5 ns (datain[30]) */
  148. 4, /* tcpt 44 - 20ns = 24ns */
  149. 3, /* Address Mode = 3 */
  150. 5, /* size value */
  151. 1}, /* ECC enabled */
  152. { 0x1f, /* Rev B, 128MByte -3 Board */
  153. 3, /* Case Latenty = 3 */
  154. 3, /* trp 20ns / 7.5 ns datain[27] */
  155. 3, /* trcd 20ns /7.5 ns (datain[29]) */
  156. 6, /* tras 44ns /7.5 ns (datain[30]) */
  157. 4, /* tcpt 44 - 20ns = 24ns */
  158. 3, /* Address Mode = 3 */
  159. 5, /* size value */
  160. 1}, /* ECC enabled */
  161. { 0x2f, /* Rev C, 128MByte -3 Board */
  162. 3, /* Case Latenty = 3 */
  163. 3, /* trp 20ns / 7.5 ns datain[27] */
  164. 3, /* trcd 20ns /7.5 ns (datain[29]) */
  165. 6, /* tras 44ns /7.5 ns (datain[30]) */
  166. 4, /* tcpt 44 - 20ns = 24ns */
  167. 3, /* Address Mode = 3 */
  168. 5, /* size value */
  169. 1}, /* ECC enabled */
  170. { 0xff, /* terminator */
  171. 0xff,
  172. 0xff,
  173. 0xff,
  174. 0xff,
  175. 0xff,
  176. 0xff,
  177. 0xff }
  178. };
  179. #endif /*CONFIG_MIP405T */
  180. void SDRAM_err (const char *s)
  181. {
  182. #ifndef SDRAM_DEBUG
  183. (void) get_clocks ();
  184. gd->baudrate = 9600;
  185. serial_init ();
  186. #endif
  187. serial_puts ("\n");
  188. serial_puts (s);
  189. serial_puts ("\n enable SDRAM_DEBUG for more info\n");
  190. for (;;);
  191. }
  192. unsigned char get_board_revcfg (void)
  193. {
  194. out8 (PER_BOARD_ADDR, 0);
  195. return (in8 (PER_BOARD_ADDR));
  196. }
  197. #ifdef SDRAM_DEBUG
  198. void write_hex (unsigned char i)
  199. {
  200. char cc;
  201. cc = i >> 4;
  202. cc &= 0xf;
  203. if (cc > 9)
  204. serial_putc (cc + 55);
  205. else
  206. serial_putc (cc + 48);
  207. cc = i & 0xf;
  208. if (cc > 9)
  209. serial_putc (cc + 55);
  210. else
  211. serial_putc (cc + 48);
  212. }
  213. void write_4hex (unsigned long val)
  214. {
  215. write_hex ((unsigned char) (val >> 24));
  216. write_hex ((unsigned char) (val >> 16));
  217. write_hex ((unsigned char) (val >> 8));
  218. write_hex ((unsigned char) val);
  219. }
  220. #endif
  221. int init_sdram (void)
  222. {
  223. unsigned long tmp, baseaddr;
  224. unsigned short i;
  225. unsigned char trp_clocks,
  226. trcd_clocks,
  227. tras_clocks,
  228. trc_clocks;
  229. unsigned char cal_val;
  230. unsigned char bc;
  231. unsigned long sdram_tim, sdram_bank;
  232. /*i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);*/
  233. (void) get_clocks ();
  234. gd->baudrate = 9600;
  235. serial_init ();
  236. /* set up the pld */
  237. mtdcr (EBC0_CFGADDR, PB7AP);
  238. mtdcr (EBC0_CFGDATA, PLD_AP);
  239. mtdcr (EBC0_CFGADDR, PB7CR);
  240. mtdcr (EBC0_CFGDATA, PLD_CR);
  241. /* THIS IS OBSOLETE */
  242. /* set up the board rev reg*/
  243. mtdcr (EBC0_CFGADDR, PB5AP);
  244. mtdcr (EBC0_CFGDATA, BOARD_AP);
  245. mtdcr (EBC0_CFGADDR, PB5CR);
  246. mtdcr (EBC0_CFGDATA, BOARD_CR);
  247. #ifdef SDRAM_DEBUG
  248. /* get all informations from PLD */
  249. serial_puts ("\nPLD Part 0x");
  250. bc = in8 (PLD_PART_REG);
  251. write_hex (bc);
  252. serial_puts ("\nPLD Vers 0x");
  253. bc = in8 (PLD_VERS_REG);
  254. write_hex (bc);
  255. serial_puts ("\nBoard Rev 0x");
  256. bc = in8 (PLD_BOARD_CFG_REG);
  257. write_hex (bc);
  258. serial_puts ("\n");
  259. #endif
  260. /* check board */
  261. bc = in8 (PLD_PART_REG);
  262. #if defined(CONFIG_MIP405T)
  263. if((bc & 0x80)==0)
  264. SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n");
  265. #else
  266. if((bc & 0x80)==0x80)
  267. SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n");
  268. #endif
  269. /* set-up the chipselect machine */
  270. mtdcr (EBC0_CFGADDR, PB0CR); /* get cs0 config reg */
  271. tmp = mfdcr (EBC0_CFGDATA);
  272. if ((tmp & 0x00002000) == 0) {
  273. /* MPS Boot, set up the flash */
  274. mtdcr (EBC0_CFGADDR, PB1AP);
  275. mtdcr (EBC0_CFGDATA, FLASH_AP);
  276. mtdcr (EBC0_CFGADDR, PB1CR);
  277. mtdcr (EBC0_CFGDATA, FLASH_CR);
  278. } else {
  279. /* Flash boot, set up the MPS */
  280. mtdcr (EBC0_CFGADDR, PB1AP);
  281. mtdcr (EBC0_CFGDATA, MPS_AP);
  282. mtdcr (EBC0_CFGADDR, PB1CR);
  283. mtdcr (EBC0_CFGDATA, MPS_CR);
  284. }
  285. /* set up UART0 (CS2) and UART1 (CS3) */
  286. mtdcr (EBC0_CFGADDR, PB2AP);
  287. mtdcr (EBC0_CFGDATA, UART0_AP);
  288. mtdcr (EBC0_CFGADDR, PB2CR);
  289. mtdcr (EBC0_CFGDATA, UART0_CR);
  290. mtdcr (EBC0_CFGADDR, PB3AP);
  291. mtdcr (EBC0_CFGDATA, UART1_AP);
  292. mtdcr (EBC0_CFGADDR, PB3CR);
  293. mtdcr (EBC0_CFGDATA, UART1_CR);
  294. bc = in8 (PLD_BOARD_CFG_REG);
  295. #ifdef SDRAM_DEBUG
  296. serial_puts ("\nstart SDRAM Setup\n");
  297. serial_puts ("\nBoard Rev: ");
  298. write_hex (bc);
  299. serial_puts ("\n");
  300. #endif
  301. i = 0;
  302. baseaddr = CONFIG_SYS_SDRAM_BASE;
  303. while (sdram_table[i].sz != 0xff) {
  304. if (sdram_table[i].boardtype == bc)
  305. break;
  306. i++;
  307. }
  308. if (sdram_table[i].boardtype != bc)
  309. SDRAM_err ("No SDRAM table found for this board!!!\n");
  310. #ifdef SDRAM_DEBUG
  311. serial_puts (" found table ");
  312. write_hex (i);
  313. serial_puts (" \n");
  314. #endif
  315. /* since the ECC initialisation needs some time,
  316. * we show that we're alive
  317. */
  318. if (sdram_table[i].ecc)
  319. serial_puts ("\nInitializing SDRAM, Please stand by");
  320. cal_val = sdram_table[i].cal - 1; /* Cas Latency */
  321. trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */
  322. trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */
  323. tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */
  324. /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
  325. /* trc_clocks is sum of trp_clocks + tras_clocks */
  326. trc_clocks = trp_clocks + tras_clocks;
  327. /* get SDRAM timing register */
  328. mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
  329. sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
  330. /* insert CASL value */
  331. sdram_tim |= ((unsigned long) (cal_val)) << 23;
  332. /* insert PTA value */
  333. sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18;
  334. /* insert CTP value */
  335. sdram_tim |=
  336. ((unsigned long) (trc_clocks - trp_clocks -
  337. trcd_clocks)) << 16;
  338. /* insert LDF (always 01) */
  339. sdram_tim |= ((unsigned long) 0x01) << 14;
  340. /* insert RFTA value */
  341. sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2;
  342. /* insert RCD value */
  343. sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0;
  344. tmp = ((unsigned long) (sdram_table[i].am - 1) << 13); /* AM = 3 */
  345. /* insert SZ value; */
  346. tmp |= ((unsigned long) sdram_table[i].sz << 17);
  347. /* get SDRAM bank 0 register */
  348. mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
  349. sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
  350. sdram_bank |= (baseaddr | tmp | 0x01);
  351. #ifdef SDRAM_DEBUG
  352. serial_puts ("sdtr: ");
  353. write_4hex (sdram_tim);
  354. serial_puts ("\n");
  355. #endif
  356. /* write SDRAM timing register */
  357. mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
  358. mtdcr (SDRAM0_CFGDATA, sdram_tim);
  359. #ifdef SDRAM_DEBUG
  360. serial_puts ("mb0cf: ");
  361. write_4hex (sdram_bank);
  362. serial_puts ("\n");
  363. #endif
  364. /* write SDRAM bank 0 register */
  365. mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
  366. mtdcr (SDRAM0_CFGDATA, sdram_bank);
  367. if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */
  368. /* get SDRAM refresh interval register */
  369. mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
  370. tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
  371. tmp |= 0x07F00000;
  372. } else {
  373. /* get SDRAM refresh interval register */
  374. mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
  375. tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
  376. tmp |= 0x05F00000;
  377. }
  378. /* write SDRAM refresh interval register */
  379. mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
  380. mtdcr (SDRAM0_CFGDATA, tmp);
  381. /* enable ECC if used */
  382. #if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
  383. if (sdram_table[i].ecc) {
  384. /* disable checking for all banks */
  385. unsigned long *p;
  386. #ifdef SDRAM_DEBUG
  387. serial_puts ("disable ECC.. ");
  388. #endif
  389. mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
  390. tmp = mfdcr (SDRAM0_CFGDATA);
  391. tmp &= 0xff0fffff; /* disable all banks */
  392. mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
  393. /* set up SDRAM Controller with ECC enabled */
  394. #ifdef SDRAM_DEBUG
  395. serial_puts ("setup SDRAM Controller.. ");
  396. #endif
  397. mtdcr (SDRAM0_CFGDATA, tmp);
  398. mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
  399. tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
  400. mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
  401. mtdcr (SDRAM0_CFGDATA, tmp);
  402. udelay (600);
  403. #ifdef SDRAM_DEBUG
  404. serial_puts ("fill the memory..\n");
  405. #endif
  406. serial_puts (".");
  407. /* now, fill all the memory */
  408. tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz);
  409. p = (unsigned long) 0;
  410. while ((unsigned long) p < tmp) {
  411. *p++ = 0L;
  412. if (!((unsigned long) p % 0x00800000)) /* every 8MByte */
  413. serial_puts (".");
  414. }
  415. /* enable bank 0 */
  416. serial_puts (".");
  417. #ifdef SDRAM_DEBUG
  418. serial_puts ("enable ECC\n");
  419. #endif
  420. udelay (400);
  421. mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
  422. tmp = mfdcr (SDRAM0_CFGDATA);
  423. tmp |= 0x00800000; /* enable bank 0 */
  424. mtdcr (SDRAM0_CFGDATA, tmp);
  425. udelay (400);
  426. } else
  427. #endif
  428. {
  429. /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
  430. mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
  431. tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000;
  432. mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
  433. mtdcr (SDRAM0_CFGDATA, tmp);
  434. udelay (400);
  435. }
  436. serial_puts ("\n");
  437. return (0);
  438. }
  439. int board_early_init_f (void)
  440. {
  441. init_sdram ();
  442. /*-------------------------------------------------------------------------+
  443. | Interrupt controller setup for the PIP405 board.
  444. | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
  445. | IRQ 16 405GP internally generated; active low; level sensitive
  446. | IRQ 17-24 RESERVED
  447. | IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive
  448. | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
  449. | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
  450. | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
  451. | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
  452. | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
  453. | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
  454. | Note for MIP405 board:
  455. | An interrupt taken for the SouthBridge (IRQ 25) indicates that
  456. | the Interrupt Controller in the South Bridge has caused the
  457. | interrupt. The IC must be read to determine which device
  458. | caused the interrupt.
  459. |
  460. +-------------------------------------------------------------------------*/
  461. mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
  462. mtdcr (UIC0ER, 0x00000000); /* disable all ints */
  463. mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */
  464. mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
  465. mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
  466. mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
  467. mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
  468. return 0;
  469. }
  470. int board_early_init_r(void)
  471. {
  472. int mode;
  473. /*
  474. * since we are relocated, we can finally enable i-cache
  475. * and set up the flash CS correctly
  476. */
  477. icache_enable();
  478. setup_cs_reloc();
  479. /* get and display boot mode */
  480. mode = get_boot_mode();
  481. if (mode & BOOT_PCI)
  482. printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ?
  483. "MPS" : "Flash");
  484. else
  485. printf("%s Boot\n", (mode & BOOT_MPS) ?
  486. "MPS" : "Flash");
  487. return 0;
  488. }
  489. /*
  490. * Get some PLD Registers
  491. */
  492. unsigned short get_pld_parvers (void)
  493. {
  494. unsigned short result;
  495. unsigned char rc;
  496. rc = in8 (PLD_PART_REG);
  497. result = (unsigned short) rc << 8;
  498. rc = in8 (PLD_VERS_REG);
  499. result |= rc;
  500. return result;
  501. }
  502. void user_led0 (unsigned char on)
  503. {
  504. if (on)
  505. out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4));
  506. else
  507. out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb));
  508. }
  509. void ide_set_reset (int idereset)
  510. {
  511. /* if reset = 1 IDE reset will be asserted */
  512. if (idereset)
  513. out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1));
  514. else {
  515. udelay (10000);
  516. out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe));
  517. }
  518. }
  519. /* ------------------------------------------------------------------------- */
  520. void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var)
  521. {
  522. #if !defined(CONFIG_MIP405T)
  523. unsigned char bc,rc,tmp;
  524. int i;
  525. bc = in8 (PLD_BOARD_CFG_REG);
  526. tmp = ~bc;
  527. tmp &= 0xf;
  528. rc = 0;
  529. for (i = 0; i < 4; i++) {
  530. rc <<= 1;
  531. rc += (tmp & 0x1);
  532. tmp >>= 1;
  533. }
  534. rc++;
  535. if(( (((bc>>4) & 0xf)==0x2) /* Rev C PCB or */
  536. || (((bc>>4) & 0xf)==0x1)) /* Rev B PCB with */
  537. && (rc==0x1)) /* Population Option 1 is a -3 */
  538. rc=3;
  539. *pcbrev=(bc >> 4) & 0xf;
  540. *var=rc;
  541. #else
  542. unsigned char bc;
  543. bc = in8 (PLD_BOARD_CFG_REG);
  544. *pcbrev=(bc >> 4) & 0xf;
  545. *var=16-(bc & 0xf);
  546. #endif
  547. }
  548. /*
  549. * Check Board Identity:
  550. */
  551. /* serial String: "MIP405_1000" OR "MIP405T_1000" */
  552. #if !defined(CONFIG_MIP405T)
  553. #define BOARD_NAME "MIP405"
  554. #else
  555. #define BOARD_NAME "MIP405T"
  556. #endif
  557. int checkboard (void)
  558. {
  559. char s[50];
  560. unsigned char bc, var;
  561. int i;
  562. backup_t *b = (backup_t *) s;
  563. puts ("Board: ");
  564. get_pcbrev_var(&bc,&var);
  565. i = getenv_f("serial#", (char *)s, 32);
  566. if ((i == 0) || strncmp ((char *)s, BOARD_NAME,sizeof(BOARD_NAME))) {
  567. get_backup_values (b);
  568. if (strncmp (b->signature, "MPL\0", 4) != 0) {
  569. puts ("### No HW ID - assuming " BOARD_NAME);
  570. printf ("-%d Rev %c", var, 'A' + bc);
  571. } else {
  572. b->serial_name[sizeof(BOARD_NAME)-1] = 0;
  573. printf ("%s-%d Rev %c SN: %s", b->serial_name, var,
  574. 'A' + bc, &b->serial_name[sizeof(BOARD_NAME)]);
  575. }
  576. } else {
  577. s[sizeof(BOARD_NAME)-1] = 0;
  578. printf ("%s-%d Rev %c SN: %s", s, var,'A' + bc,
  579. &s[sizeof(BOARD_NAME)]);
  580. }
  581. bc = in8 (PLD_EXT_CONF_REG);
  582. printf (" Boot Config: 0x%x\n", bc);
  583. return (0);
  584. }
  585. /* ------------------------------------------------------------------------- */
  586. /* ------------------------------------------------------------------------- */
  587. /*
  588. initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
  589. the necessary info for SDRAM controller configuration
  590. */
  591. /* ------------------------------------------------------------------------- */
  592. /* ------------------------------------------------------------------------- */
  593. static int test_dram (unsigned long ramsize);
  594. phys_size_t initdram (int board_type)
  595. {
  596. unsigned long bank_reg[4], tmp, bank_size;
  597. int i;
  598. unsigned long TotalSize;
  599. /* since the DRAM controller is allready set up, calculate the size with the
  600. bank registers */
  601. mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
  602. bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
  603. mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
  604. bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
  605. mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
  606. bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
  607. mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
  608. bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
  609. TotalSize = 0;
  610. for (i = 0; i < 4; i++) {
  611. if ((bank_reg[i] & 0x1) == 0x1) {
  612. tmp = (bank_reg[i] >> 17) & 0x7;
  613. bank_size = 4 << tmp;
  614. TotalSize += bank_size;
  615. }
  616. }
  617. mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
  618. tmp = mfdcr (SDRAM0_CFGDATA);
  619. if (!tmp)
  620. printf ("No ");
  621. printf ("ECC ");
  622. test_dram (TotalSize * MEGA_BYTE);
  623. return (TotalSize * MEGA_BYTE);
  624. }
  625. /* ------------------------------------------------------------------------- */
  626. static int test_dram (unsigned long ramsize)
  627. {
  628. #ifdef SDRAM_DEBUG
  629. mem_test (0L, ramsize, 1);
  630. #endif
  631. /* not yet implemented */
  632. return (1);
  633. }
  634. /* used to check if the time in RTC is valid */
  635. static unsigned long start;
  636. static struct rtc_time tm;
  637. int misc_init_r (void)
  638. {
  639. /* adjust flash start and size as well as the offset */
  640. gd->bd->bi_flashstart=0-flash_info[0].size;
  641. gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
  642. gd->bd->bi_flashoffset=0;
  643. /* check, if RTC is running */
  644. rtc_get (&tm);
  645. start=get_timer(0);
  646. /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
  647. if (mfdcr(CPC0_PSR) & PSR_ROM_LOC)
  648. mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
  649. return (0);
  650. }
  651. void print_mip405_rev (void)
  652. {
  653. unsigned char part, vers, pcbrev, var;
  654. get_pcbrev_var(&pcbrev,&var);
  655. part = in8 (PLD_PART_REG);
  656. vers = in8 (PLD_VERS_REG);
  657. printf ("Rev: " BOARD_NAME "-%d Rev %c PLD %d Vers %d\n",
  658. var, pcbrev + 'A', part & 0x7F, vers);
  659. }
  660. extern int mk_date (char *, struct rtc_time *);
  661. int last_stage_init (void)
  662. {
  663. unsigned long stop;
  664. struct rtc_time newtm;
  665. char *s;
  666. /* write correct LED configuration */
  667. if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) {
  668. printf ("Error writing to the PHY\n");
  669. }
  670. /* since LED/CFG2 is not connected on the -2,
  671. * write to correct capability information */
  672. if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) {
  673. printf ("Error writing to the PHY\n");
  674. }
  675. print_mip405_rev ();
  676. stdio_print_current_devices ();
  677. check_env ();
  678. /* check if RTC time is valid */
  679. stop=get_timer(start);
  680. while(stop<1200) { /* we wait 1.2 sec to check if the RTC is running */
  681. udelay(1000);
  682. stop=get_timer(start);
  683. }
  684. rtc_get (&newtm);
  685. if(tm.tm_sec==newtm.tm_sec) {
  686. s=getenv("defaultdate");
  687. if(!s)
  688. mk_date ("010112001970", &newtm);
  689. else
  690. if(mk_date (s, &newtm)!=0) {
  691. printf("RTC: Bad date format in defaultdate\n");
  692. return 0;
  693. }
  694. rtc_reset ();
  695. rtc_set(&newtm);
  696. }
  697. return 0;
  698. }
  699. /***************************************************************************
  700. * some helping routines
  701. */
  702. int overwrite_console (void)
  703. {
  704. /* return true if console should be overwritten */
  705. return ((in8(PLD_EXT_CONF_REG) & 0x1) == 0);
  706. }
  707. /************************************************************************
  708. * Print MIP405 Info
  709. ************************************************************************/
  710. void print_mip405_info (void)
  711. {
  712. unsigned char part, vers, cfg, irq_reg, com_mode, ext;
  713. part = in8 (PLD_PART_REG);
  714. vers = in8 (PLD_VERS_REG);
  715. cfg = in8 (PLD_BOARD_CFG_REG);
  716. irq_reg = in8 (PLD_IRQ_REG);
  717. com_mode = in8 (PLD_COM_MODE_REG);
  718. ext = in8 (PLD_EXT_CONF_REG);
  719. printf ("PLD Part %d version %d\n", part & 0x7F, vers);
  720. printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A');
  721. printf ("Population Options %d %d %d %d\n", (cfg) & 0x1,
  722. (cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1);
  723. printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off");
  724. printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3);
  725. #if !defined(CONFIG_MIP405T)
  726. printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
  727. (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
  728. (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
  729. (ext >> 6) & 0x1, (ext >> 7) & 0x1);
  730. printf ("SER1 uses handshakes %s\n",
  731. (ext & 0x80) ? "DTR/DSR" : "RTS/CTS");
  732. #else
  733. printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
  734. (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
  735. (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
  736. (ext >> 6) & 0x1,(ext >> 7) & 0x1);
  737. #endif
  738. printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
  739. printf ("IRQs:\n");
  740. printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active");
  741. #if !defined(CONFIG_MIP405T)
  742. printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active");
  743. printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active");
  744. #endif
  745. printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active");
  746. printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active");
  747. printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active");
  748. }