fpga.c 9.5 KB

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  1. /*
  2. * (C) Copyright 2007
  3. * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <asm/io.h>
  25. #include <spartan2.h>
  26. #include <spartan3.h>
  27. #include <command.h>
  28. #include "fpga.h"
  29. #include "pmc440.h"
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #if defined(CONFIG_FPGA)
  32. #define USE_SP_CODE
  33. #ifdef USE_SP_CODE
  34. Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = {
  35. fpga_pre_config_fn,
  36. fpga_pgm_fn,
  37. fpga_init_fn,
  38. NULL, /* err */
  39. fpga_done_fn,
  40. fpga_clk_fn,
  41. fpga_cs_fn,
  42. fpga_wr_fn,
  43. NULL, /* rdata */
  44. fpga_wdata_fn,
  45. fpga_busy_fn,
  46. fpga_abort_fn,
  47. fpga_post_config_fn,
  48. };
  49. #else
  50. Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = {
  51. fpga_pre_config_fn,
  52. fpga_pgm_fn,
  53. fpga_clk_fn,
  54. fpga_init_fn,
  55. fpga_done_fn,
  56. fpga_wr_fn,
  57. fpga_post_config_fn,
  58. };
  59. #endif
  60. Xilinx_Spartan2_Slave_Serial_fns ngcc_fpga_fns = {
  61. ngcc_fpga_pre_config_fn,
  62. ngcc_fpga_pgm_fn,
  63. ngcc_fpga_clk_fn,
  64. ngcc_fpga_init_fn,
  65. ngcc_fpga_done_fn,
  66. ngcc_fpga_wr_fn,
  67. ngcc_fpga_post_config_fn
  68. };
  69. Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
  70. XILINX_XC3S1200E_DESC(
  71. #ifdef USE_SP_CODE
  72. slave_parallel,
  73. #else
  74. slave_serial,
  75. #endif
  76. (void *)&pmc440_fpga_fns,
  77. 0),
  78. XILINX_XC2S200_DESC(
  79. slave_serial,
  80. (void *)&ngcc_fpga_fns,
  81. 0)
  82. };
  83. /*
  84. * Set the active-low FPGA reset signal.
  85. */
  86. void fpga_reset(int assert)
  87. {
  88. debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
  89. if (assert) {
  90. out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
  91. debug("asserted\n");
  92. } else {
  93. out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
  94. debug("deasserted\n");
  95. }
  96. }
  97. /*
  98. * Initialize the SelectMap interface. We assume that the mode and the
  99. * initial state of all of the port pins have already been set!
  100. */
  101. void fpga_serialslave_init(void)
  102. {
  103. debug("%s:%d: Initialize serial slave interface\n", __FUNCTION__,
  104. __LINE__);
  105. fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */
  106. }
  107. /*
  108. * Set the FPGA's active-low SelectMap program line to the specified level
  109. */
  110. int fpga_pgm_fn(int assert, int flush, int cookie)
  111. {
  112. debug("%s:%d: FPGA PROGRAM ",
  113. __FUNCTION__, __LINE__);
  114. if (assert) {
  115. out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_PRG);
  116. debug("asserted\n");
  117. } else {
  118. out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_PRG);
  119. debug("deasserted\n");
  120. }
  121. return assert;
  122. }
  123. /*
  124. * Test the state of the active-low FPGA INIT line. Return 1 on INIT
  125. * asserted (low).
  126. */
  127. int fpga_init_fn(int cookie)
  128. {
  129. if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_INIT)
  130. return 0;
  131. else
  132. return 1;
  133. }
  134. #ifdef USE_SP_CODE
  135. int fpga_abort_fn(int cookie)
  136. {
  137. return 0;
  138. }
  139. int fpga_cs_fn(int assert_cs, int flush, int cookie)
  140. {
  141. return assert_cs;
  142. }
  143. int fpga_busy_fn(int cookie)
  144. {
  145. return 1;
  146. }
  147. #endif
  148. /*
  149. * Test the state of the active-high FPGA DONE pin
  150. */
  151. int fpga_done_fn(int cookie)
  152. {
  153. if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_DONE)
  154. return 1;
  155. else
  156. return 0;
  157. }
  158. /*
  159. * FPGA pre-configuration function. Just make sure that
  160. * FPGA reset is asserted to keep the FPGA from starting up after
  161. * configuration.
  162. */
  163. int fpga_pre_config_fn(int cookie)
  164. {
  165. debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
  166. fpga_reset(true);
  167. /* release init# */
  168. out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | GPIO0_FPGA_FORCEINIT);
  169. /* disable PLD IOs */
  170. out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_IOEN_N);
  171. return 0;
  172. }
  173. /*
  174. * FPGA post configuration function. Blip the FPGA reset line and then see if
  175. * the FPGA appears to be running.
  176. */
  177. int fpga_post_config_fn(int cookie)
  178. {
  179. pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
  180. int rc=0;
  181. char *s;
  182. debug("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
  183. /* enable PLD0..7 pins */
  184. out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_IOEN_N);
  185. fpga_reset(true);
  186. udelay (100);
  187. fpga_reset(false);
  188. udelay (100);
  189. FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK);
  190. /* NGCC/CANDES only: enable ledlink */
  191. if ((s = getenv("bd_type")) &&
  192. ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes"))))
  193. FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
  194. return rc;
  195. }
  196. int fpga_clk_fn(int assert_clk, int flush, int cookie)
  197. {
  198. if (assert_clk)
  199. out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_CLK);
  200. else
  201. out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_CLK);
  202. return assert_clk;
  203. }
  204. int fpga_wr_fn(int assert_write, int flush, int cookie)
  205. {
  206. if (assert_write)
  207. out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
  208. else
  209. out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
  210. return assert_write;
  211. }
  212. #ifdef USE_SP_CODE
  213. int fpga_wdata_fn(uchar data, int flush, int cookie)
  214. {
  215. uchar val = data;
  216. ulong or = in_be32((void*)GPIO1_OR);
  217. int i = 7;
  218. do {
  219. /* Write data */
  220. if (val & 0x80)
  221. or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
  222. else
  223. or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
  224. out_be32((void*)GPIO1_OR, or);
  225. /* Assert the clock */
  226. or |= GPIO1_FPGA_CLK;
  227. out_be32((void*)GPIO1_OR, or);
  228. val <<= 1;
  229. i --;
  230. } while (i > 0);
  231. /* Write last data bit (the 8th clock comes from the sp_load() code */
  232. if (val & 0x80)
  233. or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
  234. else
  235. or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
  236. out_be32((void*)GPIO1_OR, or);
  237. return 0;
  238. }
  239. #endif
  240. #define NGCC_FPGA_PRG CLOCK_EN
  241. #define NGCC_FPGA_DATA RESET_OUT
  242. #define NGCC_FPGA_DONE CLOCK_IN
  243. #define NGCC_FPGA_INIT IRIGB_R_IN
  244. #define NGCC_FPGA_CLK CLOCK_OUT
  245. void ngcc_fpga_serialslave_init(void)
  246. {
  247. debug("%s:%d: Initialize serial slave interface\n",
  248. __FUNCTION__, __LINE__);
  249. /* make sure program pin is inactive */
  250. ngcc_fpga_pgm_fn(false, false, 0);
  251. }
  252. /*
  253. * Set the active-low FPGA reset signal.
  254. */
  255. void ngcc_fpga_reset(int assert)
  256. {
  257. debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
  258. if (assert) {
  259. FPGA_CLRBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
  260. debug("asserted\n");
  261. } else {
  262. FPGA_SETBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
  263. debug("deasserted\n");
  264. }
  265. }
  266. /*
  267. * Set the FPGA's active-low SelectMap program line to the specified level
  268. */
  269. int ngcc_fpga_pgm_fn(int assert, int flush, int cookie)
  270. {
  271. pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
  272. debug("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
  273. if (assert) {
  274. FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_PRG);
  275. debug("asserted\n");
  276. } else {
  277. FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_PRG);
  278. debug("deasserted\n");
  279. }
  280. return assert;
  281. }
  282. /*
  283. * Test the state of the active-low FPGA INIT line. Return 1 on INIT
  284. * asserted (low).
  285. */
  286. int ngcc_fpga_init_fn(int cookie)
  287. {
  288. pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
  289. debug("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
  290. if (FPGA_IN32(&fpga->status) & NGCC_FPGA_INIT) {
  291. debug("high\n");
  292. return 0;
  293. } else {
  294. debug("low\n");
  295. return 1;
  296. }
  297. }
  298. /*
  299. * Test the state of the active-high FPGA DONE pin
  300. */
  301. int ngcc_fpga_done_fn(int cookie)
  302. {
  303. pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
  304. debug("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
  305. if (FPGA_IN32(&fpga->status) & NGCC_FPGA_DONE) {
  306. debug("DONE high\n");
  307. return 1;
  308. } else {
  309. debug("low\n");
  310. return 0;
  311. }
  312. }
  313. /*
  314. * FPGA pre-configuration function.
  315. */
  316. int ngcc_fpga_pre_config_fn(int cookie)
  317. {
  318. pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
  319. debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
  320. ngcc_fpga_reset(true);
  321. FPGA_CLRBITS(&fpga->ctrla, 0xfffffe00);
  322. ngcc_fpga_reset(true);
  323. return 0;
  324. }
  325. /*
  326. * FPGA post configuration function. Blip the FPGA reset line and then see if
  327. * the FPGA appears to be running.
  328. */
  329. int ngcc_fpga_post_config_fn(int cookie)
  330. {
  331. pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
  332. debug("%s:%d: NGCC FPGA post configuration\n", __FUNCTION__, __LINE__);
  333. udelay (100);
  334. ngcc_fpga_reset(false);
  335. FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
  336. return 0;
  337. }
  338. int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie)
  339. {
  340. pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
  341. if (assert_clk)
  342. FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_CLK);
  343. else
  344. FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_CLK);
  345. return assert_clk;
  346. }
  347. int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie)
  348. {
  349. pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
  350. if (assert_write)
  351. FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_DATA);
  352. else
  353. FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_DATA);
  354. return assert_write;
  355. }
  356. /*
  357. * Initialize the fpga. Return 1 on success, 0 on failure.
  358. */
  359. int pmc440_init_fpga(void)
  360. {
  361. char *s;
  362. debug("%s:%d: Initialize FPGA interface\n",
  363. __FUNCTION__, __LINE__);
  364. fpga_init();
  365. fpga_serialslave_init ();
  366. debug("%s:%d: Adding fpga 0\n", __FUNCTION__, __LINE__);
  367. fpga_add (fpga_xilinx, &fpga[0]);
  368. /* NGCC only */
  369. if ((s = getenv("bd_type")) && !strcmp(s, "ngcc")) {
  370. ngcc_fpga_serialslave_init ();
  371. debug("%s:%d: Adding fpga 1\n", __FUNCTION__, __LINE__);
  372. fpga_add (fpga_xilinx, &fpga[1]);
  373. }
  374. return 0;
  375. }
  376. #endif /* CONFIG_FPGA */