bamboo.h 16 KB

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  1. /*
  2. * (C) Copyright 2005
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*----------------------------------------------------------------------------+
  24. | FPGA registers and bit definitions
  25. +----------------------------------------------------------------------------*/
  26. /*
  27. * PowerPC 440EP Board FPGA is reached with physical address 0x80001FF0.
  28. * TLB initialization makes it correspond to logical address 0x80001FF0.
  29. * => Done init_chip.s in bootlib
  30. */
  31. #define FPGA_BASE_ADDR 0x80002000
  32. /*----------------------------------------------------------------------------+
  33. | Board Jumpers Setting Register
  34. | Board Settings provided by jumpers
  35. +----------------------------------------------------------------------------*/
  36. #define FPGA_SETTING_REG (FPGA_BASE_ADDR+0x3)
  37. /* Boot from small flash */
  38. #define FPGA_SET_REG_BOOT_SMALL_FLASH 0x80
  39. /* Operational Flash versus SRAM position in Memory Map */
  40. #define FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK 0x40
  41. #define FPGA_SET_REG_OP_CODE_FLASH_ABOVE 0x40
  42. #define FPGA_SET_REG_SRAM_ABOVE 0x00
  43. /* Boot From NAND Flash */
  44. #define FPGA_SET_REG_BOOT_NAND_FLASH_MASK 0x40
  45. #define FPGA_SET_REG_BOOT_NAND_FLASH_SELECT 0x00
  46. /* On Board PCI Arbiter Select */
  47. #define FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK 0x10
  48. #define FPGA_SET_REG_PCI_EXT_ARBITER_SEL 0x00
  49. /*----------------------------------------------------------------------------+
  50. | Functions Selection Register 1
  51. +----------------------------------------------------------------------------*/
  52. #define FPGA_SELECTION_1_REG (FPGA_BASE_ADDR+0x4)
  53. #define FPGA_SEL_1_REG_PHY_MASK 0xE0
  54. #define FPGA_SEL_1_REG_MII 0x80
  55. #define FPGA_SEL_1_REG_RMII 0x40
  56. #define FPGA_SEL_1_REG_SMII 0x20
  57. #define FPGA_SEL_1_REG_USB2_DEV_SEL 0x10 /* USB2 Device Selection */
  58. #define FPGA_SEL_1_REG_USB2_HOST_SEL 0x08 /* USB2 Host Selection */
  59. #define FPGA_SEL_1_REG_NF_SELEC_MASK 0x07 /* NF Selection Mask */
  60. #define FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04 /* NF0 Selected by NF_CS1 */
  61. #define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02 /* NF1 Selected by NF_CS2 */
  62. #define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01 /* NF1 Selected by NF_CS3 */
  63. /*----------------------------------------------------------------------------+
  64. | Functions Selection Register 2
  65. +----------------------------------------------------------------------------*/
  66. #define FPGA_SELECTION_2_REG (FPGA_BASE_ADDR+0x5)
  67. #define FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80 /* IIC1 / SCP Selection */
  68. #define FPGA_SEL2_REG_SEL_FRAM 0x80 /* FRAM on IIC1 bus selected - SCP Select */
  69. #define FPGA_SEL2_REG_SEL_SCP 0x80 /* Identical to SCP Selection */
  70. #define FPGA_SEL2_REG_SEL_IIC1 0x00 /* IIC1 Selection - Default Value */
  71. #define FPGA_SEL2_REG_SEL_DMA_A_B 0x40 /* DMA A & B channels selected */
  72. #define FPGA_SEL2_REG_SEL_DMA_C_D 0x20 /* DMA C & D channels selected */
  73. #define FPGA_SEL2_REG_DMA_EOT_TC_3_SEL 0x10 /* 0 = EOT - input to 440EP */
  74. /* 1 = TC - output from 440EP */
  75. #define FPGA_SEL2_REG_DMA_EOT_TC_2_SEL 0x08 /* 0 = EOT (input to 440EP) */
  76. /* 1 = TC (output from 440EP) */
  77. #define FPGA_SEL2_REG_SEL_GPIO_1 0x04 /* EBC_GPIO & USB2_GPIO selected */
  78. #define FPGA_SEL2_REG_SEL_GPIO_2 0x02 /* Ether._GPIO & UART_GPIO selected */
  79. #define FPGA_SEL2_REG_SEL_GPIO_3 0x01 /* DMA_GPIO & Trace_GPIO selected */
  80. /*----------------------------------------------------------------------------+
  81. | Functions Selection Register 3
  82. +----------------------------------------------------------------------------*/
  83. #define FPGA_SELECTION_3_REG (FPGA_BASE_ADDR+0x6)
  84. #define FPGA_SEL3_REG_EXP_SLOT_EN 0x80 /* Expansion Slot enabled */
  85. #define FPGA_SEL3_REG_SEL_UART_CONFIG_MASK 0x70
  86. #define FPGA_SEL3_REG_SEL_UART_CONFIG1 0x40 /* one 8_pin UART */
  87. #define FPGA_SEL3_REG_SEL_UART_CONFIG2 0x20 /* two 4_pin UARTs */
  88. #define FPGA_SEL3_REG_SEL_UART_CONFIG3 0x10 /* one 4_pin & two 2_pin UARTs */
  89. #define FPGA_SEL3_REG_SEL_UART_CONFIG4 0x08 /* four 2_pin UARTs */
  90. #define FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART 0x00 /* DTR/DSR mode for 4_pin_UART */
  91. #define FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART 0x04 /* RTS/CTS mode for 4_pin_UART */
  92. /*----------------------------------------------------------------------------+
  93. | Soft Reset Register
  94. +----------------------------------------------------------------------------*/
  95. #define FPGA_RESET_REG (FPGA_BASE_ADDR+0x7)
  96. #define FPGA_RESET_REG_RESET_USB20_DEV 0x80 /* Hard Reset of the GT3200 */
  97. #define FPGA_RESET_REG_RESET_DISPLAY 0x40 /* Hard Reset on Display Device */
  98. #define FPGA_RESET_REG_STATUS_LED_0 0x08 /* 1 = Led On */
  99. #define FPGA_RESET_REG_STATUS_LED_1 0x04 /* 1 = Led On */
  100. #define FPGA_RESET_REG_STATUS_LED_2 0x02 /* 1 = Led On */
  101. #define FPGA_RESET_REG_STATUS_LED_3 0x01 /* 1 = Led On */
  102. /*----------------------------------------------------------------------------+
  103. | SDR Configuration registers
  104. +----------------------------------------------------------------------------*/
  105. #define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00006000 /* EBC Boot Size Mask */
  106. #define SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000 /* EBC 32 bits */
  107. #define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000 /* EBC 16 Bits */
  108. #define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */
  109. #define SDR0_SDSTP1_BOOT_SEL_MASK 0x00001800 /* Boot device Selection Mask */
  110. #define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */
  111. #define SDR0_SDSTP1_BOOT_SEL_PCI 0x00000800 /* PCI */
  112. #define SDR0_SDSTP1_BOOT_SEL_NDFC 0x00001000 /* NDFC */
  113. /* Serial Device Enabled - Addr = 0xA8 */
  114. #define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
  115. /* Serial Device Enabled - Addr = 0xA4 */
  116. #define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
  117. /* Pin Straps Reg */
  118. #define SDR0_PSTRP0 0x0040
  119. #define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
  120. #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
  121. #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
  122. #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
  123. #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
  124. #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
  125. #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
  126. #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
  127. #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
  128. /*----------------------------------------------------------------------------+
  129. | EBC Configuration Register - EBC0_CFG
  130. +----------------------------------------------------------------------------*/
  131. /* External Bus Three-State Control */
  132. #define EBC0_CFG_EBTC_DRIVEN 0x80000000
  133. /* Device-Paced Time-out Disable */
  134. #define EBC0_CFG_PTD_ENABLED 0x00000000
  135. /* Ready Timeout Count */
  136. #define EBC0_CFG_RTC_MASK 0x38000000
  137. #define EBC0_CFG_RTC_16PERCLK 0x00000000
  138. #define EBC0_CFG_RTC_32PERCLK 0x08000000
  139. #define EBC0_CFG_RTC_64PERCLK 0x10000000
  140. #define EBC0_CFG_RTC_128PERCLK 0x18000000
  141. #define EBC0_CFG_RTC_256PERCLK 0x20000000
  142. #define EBC0_CFG_RTC_512PERCLK 0x28000000
  143. #define EBC0_CFG_RTC_1024PERCLK 0x30000000
  144. #define EBC0_CFG_RTC_2048PERCLK 0x38000000
  145. /* External Master Priority Low */
  146. #define EBC0_CFG_EMPL_LOW 0x00000000
  147. #define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000
  148. #define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000
  149. #define EBC0_CFG_EMPL_HIGH 0x06000000
  150. /* External Master Priority High */
  151. #define EBC0_CFG_EMPH_LOW 0x00000000
  152. #define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000
  153. #define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000
  154. #define EBC0_CFG_EMPH_HIGH 0x01800000
  155. /* Chip Select Three-State Control */
  156. #define EBC0_CFG_CSTC_DRIVEN 0x00400000
  157. /* Burst Prefetch */
  158. #define EBC0_CFG_BPF_ONEDW 0x00000000
  159. #define EBC0_CFG_BPF_TWODW 0x00100000
  160. #define EBC0_CFG_BPF_FOURDW 0x00200000
  161. /* External Master Size */
  162. #define EBC0_CFG_EMS_8BIT 0x00000000
  163. /* Power Management Enable */
  164. #define EBC0_CFG_PME_DISABLED 0x00000000
  165. #define EBC0_CFG_PME_ENABLED 0x00020000
  166. /* Power Management Timer */
  167. #define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
  168. /*----------------------------------------------------------------------------+
  169. | Peripheral Bank Configuration Register - EBC0_BnCR
  170. +----------------------------------------------------------------------------*/
  171. /* BAS - Base Address Select */
  172. #define EBC0_BNCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0)
  173. /* BS - Bank Size */
  174. #define EBC0_BNCR_BS_MASK 0x000E0000
  175. #define EBC0_BNCR_BS_1MB 0x00000000
  176. #define EBC0_BNCR_BS_2MB 0x00020000
  177. #define EBC0_BNCR_BS_4MB 0x00040000
  178. #define EBC0_BNCR_BS_8MB 0x00060000
  179. #define EBC0_BNCR_BS_16MB 0x00080000
  180. #define EBC0_BNCR_BS_32MB 0x000A0000
  181. #define EBC0_BNCR_BS_64MB 0x000C0000
  182. #define EBC0_BNCR_BS_128MB 0x000E0000
  183. /* BU - Bank Usage */
  184. #define EBC0_BNCR_BU_MASK 0x00018000
  185. #define EBC0_BNCR_BU_RO 0x00008000
  186. #define EBC0_BNCR_BU_WO 0x00010000
  187. #define EBC0_BNCR_BU_RW 0x00018000
  188. /* BW - Bus Width */
  189. #define EBC0_BNCR_BW_MASK 0x00006000
  190. #define EBC0_BNCR_BW_8BIT 0x00000000
  191. #define EBC0_BNCR_BW_16BIT 0x00002000
  192. #define EBC0_BNCR_BW_32BIT 0x00004000
  193. /*----------------------------------------------------------------------------+
  194. | Peripheral Bank Access Parameters - EBC0_BnAP
  195. +----------------------------------------------------------------------------*/
  196. /* Burst Mode Enable */
  197. #define EBC0_BNAP_BME_ENABLED 0x80000000
  198. #define EBC0_BNAP_BME_DISABLED 0x00000000
  199. /* Transfert Wait */
  200. #define EBC0_BNAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) /* Bits 1:8 */
  201. /* Chip Select On Timing */
  202. #define EBC0_BNAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) /* Bits 12:13 */
  203. /* Output Enable On Timing */
  204. #define EBC0_BNAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) /* Bits 14:15 */
  205. /* Write Back Enable On Timing */
  206. #define EBC0_BNAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) /* Bits 16:17 */
  207. /* Write Back Enable Off Timing */
  208. #define EBC0_BNAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) /* Bits 18:19 */
  209. /* Transfert Hold */
  210. #define EBC0_BNAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) /* Bits 20:22 */
  211. /* PerReady Enable */
  212. #define EBC0_BNAP_RE_ENABLED 0x00000100
  213. #define EBC0_BNAP_RE_DISABLED 0x00000000
  214. /* Sample On Ready */
  215. #define EBC0_BNAP_SOR_DELAYED 0x00000000
  216. #define EBC0_BNAP_SOR_NOT_DELAYED 0x00000080
  217. /* Byte Enable Mode */
  218. #define EBC0_BNAP_BEM_WRITEONLY 0x00000000
  219. #define EBC0_BNAP_BEM_RW 0x00000040
  220. /* Parity Enable */
  221. #define EBC0_BNAP_PEN_DISABLED 0x00000000
  222. #define EBC0_BNAP_PEN_ENABLED 0x00000020
  223. /*----------------------------------------------------------------------------+
  224. | Define Boot devices
  225. +----------------------------------------------------------------------------*/
  226. /* */
  227. #define BOOT_FROM_SMALL_FLASH 0x00
  228. #define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01
  229. #define BOOT_FROM_NAND_FLASH0 0x02
  230. #define BOOT_FROM_PCI 0x03
  231. #define BOOT_DEVICE_UNKNOWN 0x04
  232. #define PVR_POWERPC_440EP_PASS1 0x42221850
  233. #define PVR_POWERPC_440EP_PASS2 0x422218D3
  234. #define GPIO0 0
  235. #define GPIO1 1
  236. /*#define MAX_SELECTION_NB CORE_NB */
  237. #define MAX_CORE_SELECT_NB 22
  238. /*----------------------------------------------------------------------------+
  239. | PPC440EP GPIOs addresses.
  240. +----------------------------------------------------------------------------*/
  241. #define GPIO0_REAL 0xEF600B00
  242. #define GPIO1_REAL 0xEF600C00
  243. /* Offsets */
  244. #define GPIOx_OR 0x00 /* GPIO Output Register */
  245. #define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
  246. #define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
  247. #define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
  248. #define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
  249. #define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
  250. #define GPIOx_ODR 0x18 /* GPIO Open drain Register */
  251. #define GPIOx_IR 0x1C /* GPIO Input Register */
  252. #define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
  253. #define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
  254. #define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
  255. #define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
  256. #define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
  257. #define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
  258. #define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
  259. #define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
  260. #define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
  261. /* GPIO0 */
  262. #define GPIO0_IS1L (GPIO0_BASE+GPIOx_IS1L)
  263. #define GPIO0_IS1H (GPIO0_BASE+GPIOx_IS1H)
  264. #define GPIO0_IS2L (GPIO0_BASE+GPIOx_IS2L)
  265. #define GPIO0_IS2H (GPIO0_BASE+GPIOx_IS2H)
  266. #define GPIO0_IS3L (GPIO0_BASE+GPIOx_IS3L)
  267. #define GPIO0_IS3H (GPIO0_BASE+GPIOx_IS3L)
  268. /* GPIO1 */
  269. #define GPIO1_IS1L (GPIO1_BASE+GPIOx_IS1L)
  270. #define GPIO1_IS1H (GPIO1_BASE+GPIOx_IS1H)
  271. #define GPIO1_IS2L (GPIO1_BASE+GPIOx_IS2L)
  272. #define GPIO1_IS2H (GPIO1_BASE+GPIOx_IS2H)
  273. #define GPIO1_IS3L (GPIO1_BASE+GPIOx_IS3L)
  274. #define GPIO1_IS3H (GPIO1_BASE+GPIOx_IS3L)
  275. #define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */
  276. #define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
  277. #define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
  278. #define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
  279. #define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
  280. /*----------------------------------------------------------------------------+
  281. | XX XX
  282. |
  283. | XXXXXX XXX XX XXX XXX
  284. | XX XX X XX XX XX
  285. | XX XX X XX XX XX
  286. | XX XX XX XX XX
  287. | XXXXXX XXX XXX XXXX XXXX
  288. +----------------------------------------------------------------------------*/
  289. /*----------------------------------------------------------------------------+
  290. | Defines
  291. +----------------------------------------------------------------------------*/
  292. typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN,
  293. ZMII_CONFIGURATION_IS_MII,
  294. ZMII_CONFIGURATION_IS_RMII,
  295. ZMII_CONFIGURATION_IS_SMII
  296. } zmii_config_t;
  297. /*----------------------------------------------------------------------------+
  298. | Declare Configuration values
  299. +----------------------------------------------------------------------------*/
  300. typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t;
  301. typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t;
  302. typedef enum config_list { IIC_CORE,
  303. SCP_CORE,
  304. DMA_CHANNEL_AB,
  305. UIC_4_9,
  306. USB2_HOST,
  307. DMA_CHANNEL_CD,
  308. USB2_DEVICE,
  309. PACKET_REJ_FUNC_AVAIL,
  310. USB1_DEVICE,
  311. EBC_MASTER,
  312. NAND_FLASH,
  313. UART_CORE0,
  314. UART_CORE1,
  315. UART_CORE2,
  316. UART_CORE3,
  317. MII_SEL,
  318. RMII_SEL,
  319. SMII_SEL,
  320. PACKET_REJ_FUNC_EN,
  321. UIC_0_3,
  322. USB1_HOST,
  323. PCI_PATCH,
  324. CORE_NB
  325. } core_list_t;
  326. typedef enum block3_value { B3_V1, B3_V2, B3_V3, B3_V4, B3_V5,
  327. B3_V6, B3_V7, B3_V8, B3_V9, B3_V10,
  328. B3_V11, B3_V12, B3_V13, B3_V14, B3_V15,
  329. B3_V16, B3_VALUE_UNKNOWN
  330. } block3_value_t;
  331. typedef enum config_validity { CONFIG_IS_VALID,
  332. CONFIG_IS_INVALID
  333. } config_validity_t;