mv_eth.h 28 KB

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  1. /*
  2. * (C) Copyright 2003
  3. * Ingo Assmus <ingo.assmus@keymile.com>
  4. *
  5. * based on - Driver for MV64360X ethernet ports
  6. * Copyright (C) 2002 rabeeh@galileo.co.il
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. /*
  27. * mv_eth.h - header file for the polled mode GT ethernet driver
  28. */
  29. #ifndef __DB64360_ETH_H__
  30. #define __DB64360_ETH_H__
  31. #include <asm/types.h>
  32. #include <asm/io.h>
  33. #include <asm/byteorder.h>
  34. #include <common.h>
  35. #include <net.h>
  36. #include "mv_regs.h"
  37. #include <asm/errno.h>
  38. /*************************************************************************
  39. **************************************************************************
  40. **************************************************************************
  41. * The first part is the high level driver of the gigE ethernet ports. *
  42. **************************************************************************
  43. **************************************************************************
  44. *************************************************************************/
  45. /* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
  46. #ifndef MAX_SKB_FRAGS
  47. #define MAX_SKB_FRAGS 0
  48. #endif
  49. /* Port attributes */
  50. /*#define MAX_RX_QUEUE_NUM 8*/
  51. /*#define MAX_TX_QUEUE_NUM 8*/
  52. #define MAX_RX_QUEUE_NUM 1
  53. #define MAX_TX_QUEUE_NUM 1
  54. /* Use one TX queue and one RX queue */
  55. #define MV64360_TX_QUEUE_NUM 1
  56. #define MV64360_RX_QUEUE_NUM 1
  57. /*
  58. * Number of RX / TX descriptors on RX / TX rings.
  59. * Note that allocating RX descriptors is done by allocating the RX
  60. * ring AND a preallocated RX buffers (skb's) for each descriptor.
  61. * The TX descriptors only allocates the TX descriptors ring,
  62. * with no pre allocated TX buffers (skb's are allocated by higher layers.
  63. */
  64. /* Default TX ring size is 10 descriptors */
  65. #ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
  66. #define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
  67. #else
  68. #define MV64360_TX_QUEUE_SIZE 4
  69. #endif
  70. /* Default RX ring size is 4 descriptors */
  71. #ifdef CONFIG_MV64360_ETH_RXQUEUE_SIZE
  72. #define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
  73. #else
  74. #define MV64360_RX_QUEUE_SIZE 4
  75. #endif
  76. #ifdef CONFIG_RX_BUFFER_SIZE
  77. #define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
  78. #else
  79. #define MV64360_RX_BUFFER_SIZE 1600
  80. #endif
  81. #ifdef CONFIG_TX_BUFFER_SIZE
  82. #define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
  83. #else
  84. #define MV64360_TX_BUFFER_SIZE 1600
  85. #endif
  86. /*
  87. * Network device statistics. Akin to the 2.0 ether stats but
  88. * with byte counters.
  89. */
  90. struct net_device_stats
  91. {
  92. unsigned long rx_packets; /* total packets received */
  93. unsigned long tx_packets; /* total packets transmitted */
  94. unsigned long rx_bytes; /* total bytes received */
  95. unsigned long tx_bytes; /* total bytes transmitted */
  96. unsigned long rx_errors; /* bad packets received */
  97. unsigned long tx_errors; /* packet transmit problems */
  98. unsigned long rx_dropped; /* no space in linux buffers */
  99. unsigned long tx_dropped; /* no space available in linux */
  100. unsigned long multicast; /* multicast packets received */
  101. unsigned long collisions;
  102. /* detailed rx_errors: */
  103. unsigned long rx_length_errors;
  104. unsigned long rx_over_errors; /* receiver ring buff overflow */
  105. unsigned long rx_crc_errors; /* recved pkt with crc error */
  106. unsigned long rx_frame_errors; /* recv'd frame alignment error */
  107. unsigned long rx_fifo_errors; /* recv'r fifo overrun */
  108. unsigned long rx_missed_errors; /* receiver missed packet */
  109. /* detailed tx_errors */
  110. unsigned long tx_aborted_errors;
  111. unsigned long tx_carrier_errors;
  112. unsigned long tx_fifo_errors;
  113. unsigned long tx_heartbeat_errors;
  114. unsigned long tx_window_errors;
  115. /* for cslip etc */
  116. unsigned long rx_compressed;
  117. unsigned long tx_compressed;
  118. };
  119. /* Private data structure used for ethernet device */
  120. struct mv64360_eth_priv {
  121. unsigned int port_num;
  122. struct net_device_stats *stats;
  123. /* to buffer area aligned */
  124. char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */
  125. char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */
  126. /* Size of Tx Ring per queue */
  127. unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
  128. /* Size of Rx Ring per queue */
  129. unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
  130. /* Magic Number for Ethernet running */
  131. unsigned int eth_running;
  132. };
  133. int mv64360_eth_init (struct eth_device *dev);
  134. int mv64360_eth_stop (struct eth_device *dev);
  135. int mv64360_eth_start_xmit(struct eth_device *dev, void *packet, int length);
  136. int mv64360_eth_open (struct eth_device *dev);
  137. /*************************************************************************
  138. **************************************************************************
  139. **************************************************************************
  140. * The second part is the low level driver of the gigE ethernet ports. *
  141. **************************************************************************
  142. **************************************************************************
  143. *************************************************************************/
  144. /********************************************************************************
  145. * Header File for : MV-643xx network interface header
  146. *
  147. * DESCRIPTION:
  148. * This header file contains macros typedefs and function declaration for
  149. * the Marvell Gig Bit Ethernet Controller.
  150. *
  151. * DEPENDENCIES:
  152. * None.
  153. *
  154. *******************************************************************************/
  155. #ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
  156. #ifdef CONFIG_MV64360_SRAM_CACHEABLE
  157. /* In case SRAM is cacheable but not cache coherent */
  158. #define D_CACHE_FLUSH_LINE(addr, offset) \
  159. { \
  160. __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
  161. }
  162. #else
  163. /* In case SRAM is cache coherent or non-cacheable */
  164. #define D_CACHE_FLUSH_LINE(addr, offset) ;
  165. #endif
  166. #else
  167. #ifdef CONFIG_NOT_COHERENT_CACHE
  168. /* In case of descriptors on DDR but not cache coherent */
  169. #define D_CACHE_FLUSH_LINE(addr, offset) \
  170. { \
  171. __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
  172. }
  173. #else
  174. /* In case of descriptors on DDR and cache coherent */
  175. #define D_CACHE_FLUSH_LINE(addr, offset) ;
  176. #endif /* CONFIG_NOT_COHERENT_CACHE */
  177. #endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
  178. #define CPU_PIPE_FLUSH \
  179. { \
  180. __asm__ __volatile__ ("eieio"); \
  181. }
  182. /* defines */
  183. /* Default port configuration value */
  184. #define PORT_CONFIG_VALUE \
  185. ETH_UNICAST_NORMAL_MODE | \
  186. ETH_DEFAULT_RX_QUEUE_0 | \
  187. ETH_DEFAULT_RX_ARP_QUEUE_0 | \
  188. ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
  189. ETH_RECEIVE_BC_IF_IP | \
  190. ETH_RECEIVE_BC_IF_ARP | \
  191. ETH_CAPTURE_TCP_FRAMES_DIS | \
  192. ETH_CAPTURE_UDP_FRAMES_DIS | \
  193. ETH_DEFAULT_RX_TCP_QUEUE_0 | \
  194. ETH_DEFAULT_RX_UDP_QUEUE_0 | \
  195. ETH_DEFAULT_RX_BPDU_QUEUE_0
  196. /* Default port extend configuration value */
  197. #define PORT_CONFIG_EXTEND_VALUE \
  198. ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
  199. ETH_PARTITION_DISABLE
  200. /* Default sdma control value */
  201. #ifdef CONFIG_NOT_COHERENT_CACHE
  202. #define PORT_SDMA_CONFIG_VALUE \
  203. ETH_RX_BURST_SIZE_16_64BIT | \
  204. GT_ETH_IPG_INT_RX(0) | \
  205. ETH_TX_BURST_SIZE_16_64BIT;
  206. #else
  207. #define PORT_SDMA_CONFIG_VALUE \
  208. ETH_RX_BURST_SIZE_4_64BIT | \
  209. GT_ETH_IPG_INT_RX(0) | \
  210. ETH_TX_BURST_SIZE_4_64BIT;
  211. #endif
  212. #define GT_ETH_IPG_INT_RX(value) \
  213. ((value & 0x3fff) << 8)
  214. /* Default port serial control value */
  215. #define PORT_SERIAL_CONTROL_VALUE \
  216. ETH_FORCE_LINK_PASS | \
  217. ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
  218. ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
  219. ETH_ADV_SYMMETRIC_FLOW_CTRL | \
  220. ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
  221. ETH_FORCE_BP_MODE_NO_JAM | \
  222. BIT9 | \
  223. ETH_DO_NOT_FORCE_LINK_FAIL | \
  224. ETH_RETRANSMIT_16_ETTEMPTS | \
  225. ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
  226. ETH_DTE_ADV_0 | \
  227. ETH_DISABLE_AUTO_NEG_BYPASS | \
  228. ETH_AUTO_NEG_NO_CHANGE | \
  229. ETH_MAX_RX_PACKET_1552BYTE | \
  230. ETH_CLR_EXT_LOOPBACK | \
  231. ETH_SET_FULL_DUPLEX_MODE | \
  232. ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
  233. #define RX_BUFFER_MAX_SIZE 0xFFFF
  234. #define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */
  235. #define RX_BUFFER_MIN_SIZE 0x8
  236. #define TX_BUFFER_MIN_SIZE 0x8
  237. /* Tx WRR confoguration macros */
  238. #define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
  239. #define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */
  240. #define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */
  241. /* MAC accepet/reject macros */
  242. #define ACCEPT_MAC_ADDR 0
  243. #define REJECT_MAC_ADDR 1
  244. /* Size of a Tx/Rx descriptor used in chain list data structure */
  245. #define RX_DESC_ALIGNED_SIZE 0x20
  246. #define TX_DESC_ALIGNED_SIZE 0x20
  247. /* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
  248. #define TX_BUF_OFFSET_IN_DESC 0x18
  249. /* Buffer offset from buffer pointer */
  250. #define RX_BUF_OFFSET 0x2
  251. /* Gap define */
  252. #define ETH_BAR_GAP 0x8
  253. #define ETH_SIZE_REG_GAP 0x8
  254. #define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4
  255. #define ETH_PORT_ACCESS_CTRL_GAP 0x4
  256. /* Gigabit Ethernet Unit Global Registers */
  257. /* MIB Counters register definitions */
  258. #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
  259. #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
  260. #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
  261. #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
  262. #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
  263. #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
  264. #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
  265. #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
  266. #define ETH_MIB_FRAMES_64_OCTETS 0x20
  267. #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
  268. #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
  269. #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
  270. #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
  271. #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
  272. #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
  273. #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
  274. #define ETH_MIB_GOOD_FRAMES_SENT 0x40
  275. #define ETH_MIB_EXCESSIVE_COLLISION 0x44
  276. #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
  277. #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
  278. #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
  279. #define ETH_MIB_FC_SENT 0x54
  280. #define ETH_MIB_GOOD_FC_RECEIVED 0x58
  281. #define ETH_MIB_BAD_FC_RECEIVED 0x5c
  282. #define ETH_MIB_UNDERSIZE_RECEIVED 0x60
  283. #define ETH_MIB_FRAGMENTS_RECEIVED 0x64
  284. #define ETH_MIB_OVERSIZE_RECEIVED 0x68
  285. #define ETH_MIB_JABBER_RECEIVED 0x6c
  286. #define ETH_MIB_MAC_RECEIVE_ERROR 0x70
  287. #define ETH_MIB_BAD_CRC_EVENT 0x74
  288. #define ETH_MIB_COLLISION 0x78
  289. #define ETH_MIB_LATE_COLLISION 0x7c
  290. /* Port serial status reg (PSR) */
  291. #define ETH_INTERFACE_GMII_MII 0
  292. #define ETH_INTERFACE_PCM BIT0
  293. #define ETH_LINK_IS_DOWN 0
  294. #define ETH_LINK_IS_UP BIT1
  295. #define ETH_PORT_AT_HALF_DUPLEX 0
  296. #define ETH_PORT_AT_FULL_DUPLEX BIT2
  297. #define ETH_RX_FLOW_CTRL_DISABLED 0
  298. #define ETH_RX_FLOW_CTRL_ENBALED BIT3
  299. #define ETH_GMII_SPEED_100_10 0
  300. #define ETH_GMII_SPEED_1000 BIT4
  301. #define ETH_MII_SPEED_10 0
  302. #define ETH_MII_SPEED_100 BIT5
  303. #define ETH_NO_TX 0
  304. #define ETH_TX_IN_PROGRESS BIT7
  305. #define ETH_BYPASS_NO_ACTIVE 0
  306. #define ETH_BYPASS_ACTIVE BIT8
  307. #define ETH_PORT_NOT_AT_PARTITION_STATE 0
  308. #define ETH_PORT_AT_PARTITION_STATE BIT9
  309. #define ETH_PORT_TX_FIFO_NOT_EMPTY 0
  310. #define ETH_PORT_TX_FIFO_EMPTY BIT10
  311. /* These macros describes the Port configuration reg (Px_cR) bits */
  312. #define ETH_UNICAST_NORMAL_MODE 0
  313. #define ETH_UNICAST_PROMISCUOUS_MODE BIT0
  314. #define ETH_DEFAULT_RX_QUEUE_0 0
  315. #define ETH_DEFAULT_RX_QUEUE_1 BIT1
  316. #define ETH_DEFAULT_RX_QUEUE_2 BIT2
  317. #define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
  318. #define ETH_DEFAULT_RX_QUEUE_4 BIT3
  319. #define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
  320. #define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
  321. #define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
  322. #define ETH_DEFAULT_RX_ARP_QUEUE_0 0
  323. #define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
  324. #define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
  325. #define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
  326. #define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
  327. #define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
  328. #define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
  329. #define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
  330. #define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
  331. #define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
  332. #define ETH_RECEIVE_BC_IF_IP 0
  333. #define ETH_REJECT_BC_IF_IP BIT8
  334. #define ETH_RECEIVE_BC_IF_ARP 0
  335. #define ETH_REJECT_BC_IF_ARP BIT9
  336. #define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
  337. #define ETH_CAPTURE_TCP_FRAMES_DIS 0
  338. #define ETH_CAPTURE_TCP_FRAMES_EN BIT14
  339. #define ETH_CAPTURE_UDP_FRAMES_DIS 0
  340. #define ETH_CAPTURE_UDP_FRAMES_EN BIT15
  341. #define ETH_DEFAULT_RX_TCP_QUEUE_0 0
  342. #define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
  343. #define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
  344. #define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
  345. #define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
  346. #define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
  347. #define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
  348. #define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
  349. #define ETH_DEFAULT_RX_UDP_QUEUE_0 0
  350. #define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
  351. #define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
  352. #define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
  353. #define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
  354. #define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
  355. #define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
  356. #define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
  357. #define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
  358. #define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
  359. #define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
  360. #define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
  361. #define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
  362. #define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
  363. #define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
  364. #define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
  365. /* These macros describes the Port configuration extend reg (Px_cXR) bits*/
  366. #define ETH_CLASSIFY_EN BIT0
  367. #define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
  368. #define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
  369. #define ETH_PARTITION_DISABLE 0
  370. #define ETH_PARTITION_ENABLE BIT2
  371. /* Tx/Rx queue command reg (RQCR/TQCR)*/
  372. #define ETH_QUEUE_0_ENABLE BIT0
  373. #define ETH_QUEUE_1_ENABLE BIT1
  374. #define ETH_QUEUE_2_ENABLE BIT2
  375. #define ETH_QUEUE_3_ENABLE BIT3
  376. #define ETH_QUEUE_4_ENABLE BIT4
  377. #define ETH_QUEUE_5_ENABLE BIT5
  378. #define ETH_QUEUE_6_ENABLE BIT6
  379. #define ETH_QUEUE_7_ENABLE BIT7
  380. #define ETH_QUEUE_0_DISABLE BIT8
  381. #define ETH_QUEUE_1_DISABLE BIT9
  382. #define ETH_QUEUE_2_DISABLE BIT10
  383. #define ETH_QUEUE_3_DISABLE BIT11
  384. #define ETH_QUEUE_4_DISABLE BIT12
  385. #define ETH_QUEUE_5_DISABLE BIT13
  386. #define ETH_QUEUE_6_DISABLE BIT14
  387. #define ETH_QUEUE_7_DISABLE BIT15
  388. /* These macros describes the Port Sdma configuration reg (SDCR) bits */
  389. #define ETH_RIFB BIT0
  390. #define ETH_RX_BURST_SIZE_1_64BIT 0
  391. #define ETH_RX_BURST_SIZE_2_64BIT BIT1
  392. #define ETH_RX_BURST_SIZE_4_64BIT BIT2
  393. #define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
  394. #define ETH_RX_BURST_SIZE_16_64BIT BIT3
  395. #define ETH_BLM_RX_NO_SWAP BIT4
  396. #define ETH_BLM_RX_BYTE_SWAP 0
  397. #define ETH_BLM_TX_NO_SWAP BIT5
  398. #define ETH_BLM_TX_BYTE_SWAP 0
  399. #define ETH_DESCRIPTORS_BYTE_SWAP BIT6
  400. #define ETH_DESCRIPTORS_NO_SWAP 0
  401. #define ETH_TX_BURST_SIZE_1_64BIT 0
  402. #define ETH_TX_BURST_SIZE_2_64BIT BIT22
  403. #define ETH_TX_BURST_SIZE_4_64BIT BIT23
  404. #define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
  405. #define ETH_TX_BURST_SIZE_16_64BIT BIT24
  406. /* These macros describes the Port serial control reg (PSCR) bits */
  407. #define ETH_SERIAL_PORT_DISABLE 0
  408. #define ETH_SERIAL_PORT_ENABLE BIT0
  409. #define ETH_FORCE_LINK_PASS BIT1
  410. #define ETH_DO_NOT_FORCE_LINK_PASS 0
  411. #define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
  412. #define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
  413. #define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
  414. #define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
  415. #define ETH_ADV_NO_FLOW_CTRL 0
  416. #define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
  417. #define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
  418. #define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
  419. #define ETH_FORCE_BP_MODE_NO_JAM 0
  420. #define ETH_FORCE_BP_MODE_JAM_TX BIT7
  421. #define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
  422. #define ETH_FORCE_LINK_FAIL 0
  423. #define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
  424. #define ETH_RETRANSMIT_16_ETTEMPTS 0
  425. #define ETH_RETRANSMIT_FOREVER BIT11
  426. #define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
  427. #define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
  428. #define ETH_DTE_ADV_0 0
  429. #define ETH_DTE_ADV_1 BIT14
  430. #define ETH_DISABLE_AUTO_NEG_BYPASS 0
  431. #define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
  432. #define ETH_AUTO_NEG_NO_CHANGE 0
  433. #define ETH_RESTART_AUTO_NEG BIT16
  434. #define ETH_MAX_RX_PACKET_1518BYTE 0
  435. #define ETH_MAX_RX_PACKET_1522BYTE BIT17
  436. #define ETH_MAX_RX_PACKET_1552BYTE BIT18
  437. #define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
  438. #define ETH_MAX_RX_PACKET_9192BYTE BIT19
  439. #define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
  440. #define ETH_SET_EXT_LOOPBACK BIT20
  441. #define ETH_CLR_EXT_LOOPBACK 0
  442. #define ETH_SET_FULL_DUPLEX_MODE BIT21
  443. #define ETH_SET_HALF_DUPLEX_MODE 0
  444. #define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
  445. #define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
  446. #define ETH_SET_GMII_SPEED_TO_10_100 0
  447. #define ETH_SET_GMII_SPEED_TO_1000 BIT23
  448. #define ETH_SET_MII_SPEED_TO_10 0
  449. #define ETH_SET_MII_SPEED_TO_100 BIT24
  450. /* SMI reg */
  451. #define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
  452. #define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
  453. #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
  454. #define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
  455. /* SDMA command status fields macros */
  456. /* Tx & Rx descriptors status */
  457. #define ETH_ERROR_SUMMARY (BIT0)
  458. /* Tx & Rx descriptors command */
  459. #define ETH_BUFFER_OWNED_BY_DMA (BIT31)
  460. /* Tx descriptors status */
  461. #define ETH_LC_ERROR (0 )
  462. #define ETH_UR_ERROR (BIT1 )
  463. #define ETH_RL_ERROR (BIT2 )
  464. #define ETH_LLC_SNAP_FORMAT (BIT9 )
  465. /* Rx descriptors status */
  466. #define ETH_CRC_ERROR (0 )
  467. #define ETH_OVERRUN_ERROR (BIT1 )
  468. #define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
  469. #define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
  470. #define ETH_VLAN_TAGGED (BIT19)
  471. #define ETH_BPDU_FRAME (BIT20)
  472. #define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
  473. #define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
  474. #define ETH_OTHER_FRAME_TYPE (BIT22)
  475. #define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
  476. #define ETH_FRAME_TYPE_IP_V_4 (BIT24)
  477. #define ETH_FRAME_HEADER_OK (BIT25)
  478. #define ETH_RX_LAST_DESC (BIT26)
  479. #define ETH_RX_FIRST_DESC (BIT27)
  480. #define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
  481. #define ETH_RX_ENABLE_INTERRUPT (BIT29)
  482. #define ETH_LAYER_4_CHECKSUM_OK (BIT30)
  483. /* Rx descriptors byte count */
  484. #define ETH_FRAME_FRAGMENTED (BIT2)
  485. /* Tx descriptors command */
  486. #define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
  487. #define ETH_FRAME_SET_TO_VLAN (BIT15)
  488. #define ETH_TCP_FRAME (0 )
  489. #define ETH_UDP_FRAME (BIT16)
  490. #define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
  491. #define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
  492. #define ETH_ZERO_PADDING (BIT19)
  493. #define ETH_TX_LAST_DESC (BIT20)
  494. #define ETH_TX_FIRST_DESC (BIT21)
  495. #define ETH_GEN_CRC (BIT22)
  496. #define ETH_TX_ENABLE_INTERRUPT (BIT23)
  497. #define ETH_AUTO_MODE (BIT30)
  498. /* Address decode parameters */
  499. /* Ethernet Base Address Register bits */
  500. #define EBAR_TARGET_DRAM 0x00000000
  501. #define EBAR_TARGET_DEVICE 0x00000001
  502. #define EBAR_TARGET_CBS 0x00000002
  503. #define EBAR_TARGET_PCI0 0x00000003
  504. #define EBAR_TARGET_PCI1 0x00000004
  505. #define EBAR_TARGET_CUNIT 0x00000005
  506. #define EBAR_TARGET_AUNIT 0x00000006
  507. #define EBAR_TARGET_GUNIT 0x00000007
  508. /* Window attributes */
  509. #define EBAR_ATTR_DRAM_CS0 0x00000E00
  510. #define EBAR_ATTR_DRAM_CS1 0x00000D00
  511. #define EBAR_ATTR_DRAM_CS2 0x00000B00
  512. #define EBAR_ATTR_DRAM_CS3 0x00000700
  513. /* DRAM Target interface */
  514. #define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000
  515. #define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000
  516. #define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000
  517. /* Device Bus Target interface */
  518. #define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00
  519. #define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00
  520. #define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00
  521. #define EBAR_ATTR_DEVICE_DEVCS3 0x00001700
  522. #define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00
  523. /* PCI Target interface */
  524. #define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000
  525. #define EBAR_ATTR_PCI_NO_SWAP 0x00000100
  526. #define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200
  527. #define EBAR_ATTR_PCI_WORD_SWAP 0x00000300
  528. #define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
  529. #define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400
  530. #define EBAR_ATTR_PCI_IO_SPACE 0x00000000
  531. #define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800
  532. #define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000
  533. #define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000
  534. /* CPU 60x bus or internal SRAM interface */
  535. #define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000
  536. #define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100
  537. #define EBAR_ATTR_CBS_SRAM 0x00000000
  538. #define EBAR_ATTR_CBS_CPU_BUS 0x00000800
  539. /* Window access control */
  540. #define EWIN_ACCESS_NOT_ALLOWED 0
  541. #define EWIN_ACCESS_READ_ONLY BIT0
  542. #define EWIN_ACCESS_FULL (BIT1 | BIT0)
  543. #define EWIN0_ACCESS_MASK 0x0003
  544. #define EWIN1_ACCESS_MASK 0x000C
  545. #define EWIN2_ACCESS_MASK 0x0030
  546. #define EWIN3_ACCESS_MASK 0x00C0
  547. /* typedefs */
  548. typedef enum _eth_port
  549. {
  550. ETH_0 = 0,
  551. ETH_1 = 1,
  552. ETH_2 = 2
  553. }ETH_PORT;
  554. typedef enum _eth_func_ret_status
  555. {
  556. ETH_OK, /* Returned as expected. */
  557. ETH_ERROR, /* Fundamental error. */
  558. ETH_RETRY, /* Could not process request. Try later. */
  559. ETH_END_OF_JOB, /* Ring has nothing to process. */
  560. ETH_QUEUE_FULL, /* Ring resource error. */
  561. ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
  562. }ETH_FUNC_RET_STATUS;
  563. typedef enum _eth_queue
  564. {
  565. ETH_Q0 = 0,
  566. ETH_Q1 = 1,
  567. ETH_Q2 = 2,
  568. ETH_Q3 = 3,
  569. ETH_Q4 = 4,
  570. ETH_Q5 = 5,
  571. ETH_Q6 = 6,
  572. ETH_Q7 = 7
  573. } ETH_QUEUE;
  574. typedef enum _addr_win
  575. {
  576. ETH_WIN0,
  577. ETH_WIN1,
  578. ETH_WIN2,
  579. ETH_WIN3,
  580. ETH_WIN4,
  581. ETH_WIN5
  582. } ETH_ADDR_WIN;
  583. typedef enum _eth_target
  584. {
  585. ETH_TARGET_DRAM ,
  586. ETH_TARGET_DEVICE,
  587. ETH_TARGET_CBS ,
  588. ETH_TARGET_PCI0 ,
  589. ETH_TARGET_PCI1
  590. }ETH_TARGET;
  591. typedef struct _eth_rx_desc
  592. {
  593. unsigned short byte_cnt ; /* Descriptor buffer byte count */
  594. unsigned short buf_size ; /* Buffer size */
  595. unsigned int cmd_sts ; /* Descriptor command status */
  596. unsigned int next_desc_ptr; /* Next descriptor pointer */
  597. unsigned int buf_ptr ; /* Descriptor buffer pointer */
  598. unsigned int return_info ; /* User resource return information */
  599. } ETH_RX_DESC;
  600. typedef struct _eth_tx_desc
  601. {
  602. unsigned short byte_cnt ; /* Descriptor buffer byte count */
  603. unsigned short l4i_chk ; /* CPU provided TCP Checksum */
  604. unsigned int cmd_sts ; /* Descriptor command status */
  605. unsigned int next_desc_ptr; /* Next descriptor pointer */
  606. unsigned int buf_ptr ; /* Descriptor buffer pointer */
  607. unsigned int return_info ; /* User resource return information */
  608. } ETH_TX_DESC;
  609. /* Unified struct for Rx and Tx operations. The user is not required to */
  610. /* be familier with neither Tx nor Rx descriptors. */
  611. typedef struct _pkt_info
  612. {
  613. unsigned short byte_cnt ; /* Descriptor buffer byte count */
  614. unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */
  615. unsigned int cmd_sts ; /* Descriptor command status */
  616. unsigned int buf_ptr ; /* Descriptor buffer pointer */
  617. unsigned int return_info ; /* User resource return information */
  618. } PKT_INFO;
  619. typedef struct _eth_win_param
  620. {
  621. ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */
  622. ETH_TARGET target; /* System targets. See ETH_TARGET enum */
  623. unsigned short attributes; /* BAR attributes. See above macros. */
  624. unsigned int base_addr; /* Window base address in unsigned int form */
  625. unsigned int high_addr; /* Window high address in unsigned int form */
  626. unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
  627. bool enable; /* Enable/disable access to the window. */
  628. unsigned short access_ctrl; /* Access ctrl register. see above macros */
  629. } ETH_WIN_PARAM;
  630. /* Ethernet port specific infomation */
  631. typedef struct _eth_port_ctrl
  632. {
  633. ETH_PORT port_num; /* User Ethernet port number */
  634. int port_phy_addr; /* User phy address of Ethrnet port */
  635. unsigned char port_mac_addr[6]; /* User defined port MAC address. */
  636. unsigned int port_config; /* User port configuration value */
  637. unsigned int port_config_extend; /* User port config extend value */
  638. unsigned int port_sdma_config; /* User port SDMA config value */
  639. unsigned int port_serial_control; /* User port serial control value */
  640. unsigned int port_tx_queue_command; /* Port active Tx queues summary */
  641. unsigned int port_rx_queue_command; /* Port active Rx queues summary */
  642. /* User function to cast virtual address to CPU bus address */
  643. unsigned int (*port_virt_to_phys)(unsigned int addr);
  644. /* User scratch pad for user specific data structures */
  645. void *port_private;
  646. bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
  647. bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
  648. /* Tx/Rx rings managment indexes fields. For driver use */
  649. /* Next available Rx resource */
  650. volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
  651. /* Returning Rx resource */
  652. volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
  653. /* Next available Tx resource */
  654. volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
  655. /* Returning Tx resource */
  656. volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
  657. /* An extra Tx index to support transmit of multiple buffers per packet */
  658. volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
  659. /* Tx/Rx rings size and base variables fields. For driver use */
  660. volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
  661. unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM];
  662. char *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
  663. volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
  664. unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM];
  665. char *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
  666. } ETH_PORT_INFO;
  667. /* ethernet.h API list */
  668. /* Port operation control routines */
  669. static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
  670. static void eth_port_reset(ETH_PORT eth_port_num);
  671. static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
  672. /* Port MAC address routines */
  673. static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
  674. unsigned char *p_addr,
  675. ETH_QUEUE queue);
  676. #if 0 /* FIXME */
  677. static void eth_port_mc_addr (ETH_PORT eth_port_num,
  678. unsigned char *p_addr,
  679. ETH_QUEUE queue,
  680. int option);
  681. #endif
  682. /* PHY and MIB routines */
  683. static bool ethernet_phy_reset(ETH_PORT eth_port_num);
  684. static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
  685. unsigned int phy_reg,
  686. unsigned int value);
  687. static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
  688. unsigned int phy_reg,
  689. unsigned int* value);
  690. static void eth_clear_mib_counters(ETH_PORT eth_port_num);
  691. /* Port data flow control routines */
  692. static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl,
  693. ETH_QUEUE tx_queue,
  694. PKT_INFO *p_pkt_info);
  695. static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
  696. ETH_QUEUE tx_queue,
  697. PKT_INFO *p_pkt_info);
  698. static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
  699. ETH_QUEUE rx_queue,
  700. PKT_INFO *p_pkt_info);
  701. static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
  702. ETH_QUEUE rx_queue,
  703. PKT_INFO *p_pkt_info);
  704. static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
  705. ETH_QUEUE tx_queue,
  706. int tx_desc_num,
  707. int tx_buff_size,
  708. unsigned int tx_desc_base_addr,
  709. unsigned int tx_buff_base_addr);
  710. static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
  711. ETH_QUEUE rx_queue,
  712. int rx_desc_num,
  713. int rx_buff_size,
  714. unsigned int rx_desc_base_addr,
  715. unsigned int rx_buff_base_addr);
  716. #endif /* MV64360_ETH_ */