44x_spd_ddr2.c 99 KB

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  1. /*
  2. * arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
  3. * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
  4. * DDR2 controller (non Denali Core). Those currently are:
  5. *
  6. * 405: 405EX(r)
  7. * 440/460: 440SP/440SPe/460EX/460GT
  8. *
  9. * Copyright (c) 2008 Nuovation System Designs, LLC
  10. * Grant Erickson <gerickson@nuovations.com>
  11. * (C) Copyright 2007-2009
  12. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  13. *
  14. * COPYRIGHT AMCC CORPORATION 2004
  15. *
  16. * See file CREDITS for list of people who contributed to this
  17. * project.
  18. *
  19. * This program is free software; you can redistribute it and/or
  20. * modify it under the terms of the GNU General Public License as
  21. * published by the Free Software Foundation; either version 2 of
  22. * the License, or (at your option) any later version.
  23. *
  24. * This program is distributed in the hope that it will be useful,
  25. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  27. * GNU General Public License for more details.
  28. *
  29. * You should have received a copy of the GNU General Public License
  30. * along with this program; if not, write to the Free Software
  31. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32. * MA 02111-1307 USA
  33. *
  34. */
  35. /* define DEBUG for debugging output (obviously ;-)) */
  36. #if 0
  37. #define DEBUG
  38. #endif
  39. #include <common.h>
  40. #include <command.h>
  41. #include <asm/ppc4xx.h>
  42. #include <i2c.h>
  43. #include <asm/io.h>
  44. #include <asm/processor.h>
  45. #include <asm/mmu.h>
  46. #include <asm/cache.h>
  47. #include "ecc.h"
  48. #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \
  49. do { \
  50. u32 data; \
  51. mfsdram(SDRAM_##mnemonic, data); \
  52. printf("%20s[%02x] = 0x%08X\n", \
  53. "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
  54. } while (0)
  55. #define PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(mnemonic) \
  56. do { \
  57. u32 data; \
  58. data = mfdcr(SDRAM_##mnemonic); \
  59. printf("%20s[%02x] = 0x%08X\n", \
  60. "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
  61. } while (0)
  62. #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  63. static void update_rdcc(void)
  64. {
  65. u32 val;
  66. /*
  67. * Complete RDSS configuration as mentioned on page 7 of the AMCC
  68. * PowerPC440SP/SPe DDR2 application note:
  69. * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
  70. *
  71. * Or item #10 "10. Complete RDSS configuration" in chapter
  72. * "22.2.9 SDRAM Initialization" of AMCC PPC460EX/EXr/GT users
  73. * manual.
  74. */
  75. mfsdram(SDRAM_RTSR, val);
  76. if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
  77. mfsdram(SDRAM_RDCC, val);
  78. if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
  79. val += 0x40000000;
  80. mtsdram(SDRAM_RDCC, val);
  81. }
  82. }
  83. }
  84. #endif
  85. #if defined(CONFIG_440)
  86. /*
  87. * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
  88. * memory region. Right now the cache should still be disabled in U-Boot
  89. * because of the EMAC driver, that need its buffer descriptor to be located
  90. * in non cached memory.
  91. *
  92. * If at some time this restriction doesn't apply anymore, just define
  93. * CONFIG_4xx_DCACHE in the board config file and this code should setup
  94. * everything correctly.
  95. */
  96. #ifdef CONFIG_4xx_DCACHE
  97. /* enable caching on SDRAM */
  98. #define MY_TLB_WORD2_I_ENABLE 0
  99. #else
  100. /* disable caching on SDRAM */
  101. #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
  102. #endif /* CONFIG_4xx_DCACHE */
  103. void dcbz_area(u32 start_address, u32 num_bytes);
  104. #endif /* CONFIG_440 */
  105. #define MAXRANKS 4
  106. #define MAXBXCF 4
  107. #define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
  108. #if !defined(CONFIG_NAND_SPL)
  109. /*-----------------------------------------------------------------------------+
  110. * sdram_memsize
  111. *-----------------------------------------------------------------------------*/
  112. phys_size_t sdram_memsize(void)
  113. {
  114. phys_size_t mem_size;
  115. unsigned long mcopt2;
  116. unsigned long mcstat;
  117. unsigned long mb0cf;
  118. unsigned long sdsz;
  119. unsigned long i;
  120. mem_size = 0;
  121. mfsdram(SDRAM_MCOPT2, mcopt2);
  122. mfsdram(SDRAM_MCSTAT, mcstat);
  123. /* DDR controller must be enabled and not in self-refresh. */
  124. /* Otherwise memsize is zero. */
  125. if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
  126. && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
  127. && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
  128. == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
  129. for (i = 0; i < MAXBXCF; i++) {
  130. mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
  131. /* Banks enabled */
  132. if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
  133. #if defined(CONFIG_440)
  134. sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
  135. #else
  136. sdsz = mb0cf & SDRAM_RXBAS_SDSZ_MASK;
  137. #endif
  138. switch(sdsz) {
  139. case SDRAM_RXBAS_SDSZ_8:
  140. mem_size+=8;
  141. break;
  142. case SDRAM_RXBAS_SDSZ_16:
  143. mem_size+=16;
  144. break;
  145. case SDRAM_RXBAS_SDSZ_32:
  146. mem_size+=32;
  147. break;
  148. case SDRAM_RXBAS_SDSZ_64:
  149. mem_size+=64;
  150. break;
  151. case SDRAM_RXBAS_SDSZ_128:
  152. mem_size+=128;
  153. break;
  154. case SDRAM_RXBAS_SDSZ_256:
  155. mem_size+=256;
  156. break;
  157. case SDRAM_RXBAS_SDSZ_512:
  158. mem_size+=512;
  159. break;
  160. case SDRAM_RXBAS_SDSZ_1024:
  161. mem_size+=1024;
  162. break;
  163. case SDRAM_RXBAS_SDSZ_2048:
  164. mem_size+=2048;
  165. break;
  166. case SDRAM_RXBAS_SDSZ_4096:
  167. mem_size+=4096;
  168. break;
  169. default:
  170. printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
  171. , sdsz);
  172. mem_size=0;
  173. break;
  174. }
  175. }
  176. }
  177. }
  178. return mem_size << 20;
  179. }
  180. /*-----------------------------------------------------------------------------+
  181. * is_ecc_enabled
  182. *-----------------------------------------------------------------------------*/
  183. static unsigned long is_ecc_enabled(void)
  184. {
  185. unsigned long val;
  186. mfsdram(SDRAM_MCOPT1, val);
  187. return SDRAM_MCOPT1_MCHK_CHK_DECODE(val);
  188. }
  189. /*-----------------------------------------------------------------------------+
  190. * board_add_ram_info
  191. *-----------------------------------------------------------------------------*/
  192. void board_add_ram_info(int use_default)
  193. {
  194. PPC4xx_SYS_INFO board_cfg;
  195. u32 val;
  196. if (is_ecc_enabled())
  197. puts(" (ECC");
  198. else
  199. puts(" (ECC not");
  200. get_sys_info(&board_cfg);
  201. #if defined(CONFIG_405EX)
  202. val = board_cfg.freqPLB;
  203. #else
  204. mfsdr(SDR0_DDR0, val);
  205. val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
  206. #endif
  207. printf(" enabled, %d MHz", (val * 2) / 1000000);
  208. mfsdram(SDRAM_MMODE, val);
  209. val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
  210. printf(", CL%d)", val);
  211. }
  212. #endif /* !CONFIG_NAND_SPL */
  213. #if defined(CONFIG_SPD_EEPROM)
  214. /*-----------------------------------------------------------------------------+
  215. * Defines
  216. *-----------------------------------------------------------------------------*/
  217. #define SDRAM_DDR1 1
  218. #define SDRAM_DDR2 2
  219. #define SDRAM_NONE 0
  220. #define MAXDIMMS 2
  221. #define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
  222. #define ONE_BILLION 1000000000
  223. #define CMD_NOP (7 << 19)
  224. #define CMD_PRECHARGE (2 << 19)
  225. #define CMD_REFRESH (1 << 19)
  226. #define CMD_EMR (0 << 19)
  227. #define CMD_READ (5 << 19)
  228. #define CMD_WRITE (4 << 19)
  229. #define SELECT_MR (0 << 16)
  230. #define SELECT_EMR (1 << 16)
  231. #define SELECT_EMR2 (2 << 16)
  232. #define SELECT_EMR3 (3 << 16)
  233. /* MR */
  234. #define DLL_RESET 0x00000100
  235. #define WRITE_RECOV_2 (1 << 9)
  236. #define WRITE_RECOV_3 (2 << 9)
  237. #define WRITE_RECOV_4 (3 << 9)
  238. #define WRITE_RECOV_5 (4 << 9)
  239. #define WRITE_RECOV_6 (5 << 9)
  240. #define BURST_LEN_4 0x00000002
  241. /* EMR */
  242. #define ODT_0_OHM 0x00000000
  243. #define ODT_50_OHM 0x00000044
  244. #define ODT_75_OHM 0x00000004
  245. #define ODT_150_OHM 0x00000040
  246. #define ODS_FULL 0x00000000
  247. #define ODS_REDUCED 0x00000002
  248. #define OCD_CALIB_DEF 0x00000380
  249. /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
  250. #define ODT_EB0R (0x80000000 >> 8)
  251. #define ODT_EB0W (0x80000000 >> 7)
  252. #define CALC_ODT_R(n) (ODT_EB0R << (n << 1))
  253. #define CALC_ODT_W(n) (ODT_EB0W << (n << 1))
  254. #define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n))
  255. /* Defines for the Read Cycle Delay test */
  256. #define NUMMEMTESTS 8
  257. #define NUMMEMWORDS 8
  258. #define NUMLOOPS 64 /* memory test loops */
  259. /*
  260. * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
  261. * To support such configurations, we "only" map the first 2GB via the TLB's. We
  262. * need some free virtual address space for the remaining peripherals like, SoC
  263. * devices, FLASH etc.
  264. *
  265. * Note that ECC is currently not supported on configurations with more than 2GB
  266. * SDRAM. This is because we only map the first 2GB on such systems, and therefore
  267. * the ECC parity byte of the remaining area can't be written.
  268. */
  269. /*
  270. * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
  271. */
  272. void __spd_ddr_init_hang (void)
  273. {
  274. hang ();
  275. }
  276. void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
  277. /*
  278. * To provide an interface for board specific config values in this common
  279. * DDR setup code, we implement he "weak" default functions here. They return
  280. * the default value back to the caller.
  281. *
  282. * Please see include/configs/yucca.h for an example fora board specific
  283. * implementation.
  284. */
  285. u32 __ddr_wrdtr(u32 default_val)
  286. {
  287. return default_val;
  288. }
  289. u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
  290. u32 __ddr_clktr(u32 default_val)
  291. {
  292. return default_val;
  293. }
  294. u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
  295. /* Private Structure Definitions */
  296. /* enum only to ease code for cas latency setting */
  297. typedef enum ddr_cas_id {
  298. DDR_CAS_2 = 20,
  299. DDR_CAS_2_5 = 25,
  300. DDR_CAS_3 = 30,
  301. DDR_CAS_4 = 40,
  302. DDR_CAS_5 = 50
  303. } ddr_cas_id_t;
  304. /*-----------------------------------------------------------------------------+
  305. * Prototypes
  306. *-----------------------------------------------------------------------------*/
  307. static void get_spd_info(unsigned long *dimm_populated,
  308. unsigned char *iic0_dimm_addr,
  309. unsigned long num_dimm_banks);
  310. static void check_mem_type(unsigned long *dimm_populated,
  311. unsigned char *iic0_dimm_addr,
  312. unsigned long num_dimm_banks);
  313. static void check_frequency(unsigned long *dimm_populated,
  314. unsigned char *iic0_dimm_addr,
  315. unsigned long num_dimm_banks);
  316. static void check_rank_number(unsigned long *dimm_populated,
  317. unsigned char *iic0_dimm_addr,
  318. unsigned long num_dimm_banks);
  319. static void check_voltage_type(unsigned long *dimm_populated,
  320. unsigned char *iic0_dimm_addr,
  321. unsigned long num_dimm_banks);
  322. static void program_memory_queue(unsigned long *dimm_populated,
  323. unsigned char *iic0_dimm_addr,
  324. unsigned long num_dimm_banks);
  325. static void program_codt(unsigned long *dimm_populated,
  326. unsigned char *iic0_dimm_addr,
  327. unsigned long num_dimm_banks);
  328. static void program_mode(unsigned long *dimm_populated,
  329. unsigned char *iic0_dimm_addr,
  330. unsigned long num_dimm_banks,
  331. ddr_cas_id_t *selected_cas,
  332. int *write_recovery);
  333. static void program_tr(unsigned long *dimm_populated,
  334. unsigned char *iic0_dimm_addr,
  335. unsigned long num_dimm_banks);
  336. static void program_rtr(unsigned long *dimm_populated,
  337. unsigned char *iic0_dimm_addr,
  338. unsigned long num_dimm_banks);
  339. static void program_bxcf(unsigned long *dimm_populated,
  340. unsigned char *iic0_dimm_addr,
  341. unsigned long num_dimm_banks);
  342. static void program_copt1(unsigned long *dimm_populated,
  343. unsigned char *iic0_dimm_addr,
  344. unsigned long num_dimm_banks);
  345. static void program_initplr(unsigned long *dimm_populated,
  346. unsigned char *iic0_dimm_addr,
  347. unsigned long num_dimm_banks,
  348. ddr_cas_id_t selected_cas,
  349. int write_recovery);
  350. #ifdef CONFIG_DDR_ECC
  351. static void program_ecc(unsigned long *dimm_populated,
  352. unsigned char *iic0_dimm_addr,
  353. unsigned long num_dimm_banks,
  354. unsigned long tlb_word2_i_value);
  355. #endif
  356. #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
  357. static void program_DQS_calibration(unsigned long *dimm_populated,
  358. unsigned char *iic0_dimm_addr,
  359. unsigned long num_dimm_banks);
  360. #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
  361. static void test(void);
  362. #else
  363. static void DQS_calibration_process(void);
  364. #endif
  365. #endif
  366. static unsigned char spd_read(uchar chip, uint addr)
  367. {
  368. unsigned char data[2];
  369. if (i2c_probe(chip) == 0)
  370. if (i2c_read(chip, addr, 1, data, 1) == 0)
  371. return data[0];
  372. return 0;
  373. }
  374. /*-----------------------------------------------------------------------------+
  375. * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
  376. * Note: This routine runs from flash with a stack set up in the chip's
  377. * sram space. It is important that the routine does not require .sbss, .bss or
  378. * .data sections. It also cannot call routines that require these sections.
  379. *-----------------------------------------------------------------------------*/
  380. /*-----------------------------------------------------------------------------
  381. * Function: initdram
  382. * Description: Configures SDRAM memory banks for DDR operation.
  383. * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
  384. * via the IIC bus and then configures the DDR SDRAM memory
  385. * banks appropriately. If Auto Memory Configuration is
  386. * not used, it is assumed that no DIMM is plugged
  387. *-----------------------------------------------------------------------------*/
  388. phys_size_t initdram(int board_type)
  389. {
  390. unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
  391. unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
  392. unsigned long num_dimm_banks; /* on board dimm banks */
  393. unsigned long val;
  394. ddr_cas_id_t selected_cas = DDR_CAS_5; /* preset to silence compiler */
  395. int write_recovery;
  396. phys_size_t dram_size = 0;
  397. num_dimm_banks = sizeof(iic0_dimm_addr);
  398. /*------------------------------------------------------------------
  399. * Reset the DDR-SDRAM controller.
  400. *-----------------------------------------------------------------*/
  401. mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
  402. mtsdr(SDR0_SRST, 0x00000000);
  403. /*
  404. * Make sure I2C controller is initialized
  405. * before continuing.
  406. */
  407. /* switch to correct I2C bus */
  408. I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
  409. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  410. /*------------------------------------------------------------------
  411. * Clear out the serial presence detect buffers.
  412. * Perform IIC reads from the dimm. Fill in the spds.
  413. * Check to see if the dimm slots are populated
  414. *-----------------------------------------------------------------*/
  415. get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  416. /*------------------------------------------------------------------
  417. * Check the memory type for the dimms plugged.
  418. *-----------------------------------------------------------------*/
  419. check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  420. /*------------------------------------------------------------------
  421. * Check the frequency supported for the dimms plugged.
  422. *-----------------------------------------------------------------*/
  423. check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  424. /*------------------------------------------------------------------
  425. * Check the total rank number.
  426. *-----------------------------------------------------------------*/
  427. check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  428. /*------------------------------------------------------------------
  429. * Check the voltage type for the dimms plugged.
  430. *-----------------------------------------------------------------*/
  431. check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  432. /*------------------------------------------------------------------
  433. * Program SDRAM controller options 2 register
  434. * Except Enabling of the memory controller.
  435. *-----------------------------------------------------------------*/
  436. mfsdram(SDRAM_MCOPT2, val);
  437. mtsdram(SDRAM_MCOPT2,
  438. (val &
  439. ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
  440. SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
  441. SDRAM_MCOPT2_ISIE_MASK))
  442. | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
  443. SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
  444. SDRAM_MCOPT2_ISIE_ENABLE));
  445. /*------------------------------------------------------------------
  446. * Program SDRAM controller options 1 register
  447. * Note: Does not enable the memory controller.
  448. *-----------------------------------------------------------------*/
  449. program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  450. /*------------------------------------------------------------------
  451. * Set the SDRAM Controller On Die Termination Register
  452. *-----------------------------------------------------------------*/
  453. program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  454. /*------------------------------------------------------------------
  455. * Program SDRAM refresh register.
  456. *-----------------------------------------------------------------*/
  457. program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  458. /*------------------------------------------------------------------
  459. * Program SDRAM mode register.
  460. *-----------------------------------------------------------------*/
  461. program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
  462. &selected_cas, &write_recovery);
  463. /*------------------------------------------------------------------
  464. * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
  465. *-----------------------------------------------------------------*/
  466. mfsdram(SDRAM_WRDTR, val);
  467. mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
  468. ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
  469. /*------------------------------------------------------------------
  470. * Set the SDRAM Clock Timing Register
  471. *-----------------------------------------------------------------*/
  472. mfsdram(SDRAM_CLKTR, val);
  473. mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
  474. ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
  475. /*------------------------------------------------------------------
  476. * Program the BxCF registers.
  477. *-----------------------------------------------------------------*/
  478. program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  479. /*------------------------------------------------------------------
  480. * Program SDRAM timing registers.
  481. *-----------------------------------------------------------------*/
  482. program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  483. /*------------------------------------------------------------------
  484. * Set the Extended Mode register
  485. *-----------------------------------------------------------------*/
  486. mfsdram(SDRAM_MEMODE, val);
  487. mtsdram(SDRAM_MEMODE,
  488. (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
  489. SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
  490. (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
  491. | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
  492. /*------------------------------------------------------------------
  493. * Program Initialization preload registers.
  494. *-----------------------------------------------------------------*/
  495. program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
  496. selected_cas, write_recovery);
  497. /*------------------------------------------------------------------
  498. * Delay to ensure 200usec have elapsed since reset.
  499. *-----------------------------------------------------------------*/
  500. udelay(400);
  501. /*------------------------------------------------------------------
  502. * Set the memory queue core base addr.
  503. *-----------------------------------------------------------------*/
  504. program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  505. /*------------------------------------------------------------------
  506. * Program SDRAM controller options 2 register
  507. * Enable the memory controller.
  508. *-----------------------------------------------------------------*/
  509. mfsdram(SDRAM_MCOPT2, val);
  510. mtsdram(SDRAM_MCOPT2,
  511. (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
  512. SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
  513. SDRAM_MCOPT2_IPTR_EXECUTE);
  514. /*------------------------------------------------------------------
  515. * Wait for IPTR_EXECUTE init sequence to complete.
  516. *-----------------------------------------------------------------*/
  517. do {
  518. mfsdram(SDRAM_MCSTAT, val);
  519. } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
  520. /* enable the controller only after init sequence completes */
  521. mfsdram(SDRAM_MCOPT2, val);
  522. mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE));
  523. /* Make sure delay-line calibration is done before proceeding */
  524. do {
  525. mfsdram(SDRAM_DLCR, val);
  526. } while (!(val & SDRAM_DLCR_DLCS_COMPLETE));
  527. /* get installed memory size */
  528. dram_size = sdram_memsize();
  529. /*
  530. * Limit size to 2GB
  531. */
  532. if (dram_size > CONFIG_MAX_MEM_MAPPED)
  533. dram_size = CONFIG_MAX_MEM_MAPPED;
  534. /* and program tlb entries for this size (dynamic) */
  535. /*
  536. * Program TLB entries with caches enabled, for best performace
  537. * while auto-calibrating and ECC generation
  538. */
  539. program_tlb(0, 0, dram_size, 0);
  540. /*------------------------------------------------------------------
  541. * DQS calibration.
  542. *-----------------------------------------------------------------*/
  543. #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
  544. DQS_autocalibration();
  545. #else
  546. program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  547. #endif
  548. /*
  549. * Now complete RDSS configuration as mentioned on page 7 of the AMCC
  550. * PowerPC440SP/SPe DDR2 application note:
  551. * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
  552. */
  553. update_rdcc();
  554. #ifdef CONFIG_DDR_ECC
  555. /*------------------------------------------------------------------
  556. * If ecc is enabled, initialize the parity bits.
  557. *-----------------------------------------------------------------*/
  558. program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
  559. #endif
  560. /*
  561. * Flush the dcache before removing the TLB with caches
  562. * enabled. Otherwise this might lead to problems later on,
  563. * e.g. while booting Linux (as seen on ICON-440SPe).
  564. */
  565. flush_dcache();
  566. /*
  567. * Now after initialization (auto-calibration and ECC generation)
  568. * remove the TLB entries with caches enabled and program again with
  569. * desired cache functionality
  570. */
  571. remove_tlb(0, dram_size);
  572. program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
  573. ppc4xx_ibm_ddr2_register_dump();
  574. /*
  575. * Clear potential errors resulting from auto-calibration.
  576. * If not done, then we could get an interrupt later on when
  577. * exceptions are enabled.
  578. */
  579. set_mcsr(get_mcsr());
  580. return sdram_memsize();
  581. }
  582. static void get_spd_info(unsigned long *dimm_populated,
  583. unsigned char *iic0_dimm_addr,
  584. unsigned long num_dimm_banks)
  585. {
  586. unsigned long dimm_num;
  587. unsigned long dimm_found;
  588. unsigned char num_of_bytes;
  589. unsigned char total_size;
  590. dimm_found = false;
  591. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  592. num_of_bytes = 0;
  593. total_size = 0;
  594. num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
  595. debug("\nspd_read(0x%x) returned %d\n",
  596. iic0_dimm_addr[dimm_num], num_of_bytes);
  597. total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
  598. debug("spd_read(0x%x) returned %d\n",
  599. iic0_dimm_addr[dimm_num], total_size);
  600. if ((num_of_bytes != 0) && (total_size != 0)) {
  601. dimm_populated[dimm_num] = true;
  602. dimm_found = true;
  603. debug("DIMM slot %lu: populated\n", dimm_num);
  604. } else {
  605. dimm_populated[dimm_num] = false;
  606. debug("DIMM slot %lu: Not populated\n", dimm_num);
  607. }
  608. }
  609. if (dimm_found == false) {
  610. printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
  611. spd_ddr_init_hang ();
  612. }
  613. }
  614. /*------------------------------------------------------------------
  615. * For the memory DIMMs installed, this routine verifies that they
  616. * really are DDR specific DIMMs.
  617. *-----------------------------------------------------------------*/
  618. static void check_mem_type(unsigned long *dimm_populated,
  619. unsigned char *iic0_dimm_addr,
  620. unsigned long num_dimm_banks)
  621. {
  622. unsigned long dimm_num;
  623. unsigned long dimm_type;
  624. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  625. if (dimm_populated[dimm_num] == true) {
  626. dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
  627. switch (dimm_type) {
  628. case 1:
  629. printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
  630. "slot %d.\n", (unsigned int)dimm_num);
  631. printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
  632. printf("Replace the DIMM module with a supported DIMM.\n\n");
  633. spd_ddr_init_hang ();
  634. break;
  635. case 2:
  636. printf("ERROR: EDO DIMM detected in slot %d.\n",
  637. (unsigned int)dimm_num);
  638. printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
  639. printf("Replace the DIMM module with a supported DIMM.\n\n");
  640. spd_ddr_init_hang ();
  641. break;
  642. case 3:
  643. printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
  644. (unsigned int)dimm_num);
  645. printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
  646. printf("Replace the DIMM module with a supported DIMM.\n\n");
  647. spd_ddr_init_hang ();
  648. break;
  649. case 4:
  650. printf("ERROR: SDRAM DIMM detected in slot %d.\n",
  651. (unsigned int)dimm_num);
  652. printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
  653. printf("Replace the DIMM module with a supported DIMM.\n\n");
  654. spd_ddr_init_hang ();
  655. break;
  656. case 5:
  657. printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
  658. (unsigned int)dimm_num);
  659. printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
  660. printf("Replace the DIMM module with a supported DIMM.\n\n");
  661. spd_ddr_init_hang ();
  662. break;
  663. case 6:
  664. printf("ERROR: SGRAM DIMM detected in slot %d.\n",
  665. (unsigned int)dimm_num);
  666. printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
  667. printf("Replace the DIMM module with a supported DIMM.\n\n");
  668. spd_ddr_init_hang ();
  669. break;
  670. case 7:
  671. debug("DIMM slot %lu: DDR1 SDRAM detected\n", dimm_num);
  672. dimm_populated[dimm_num] = SDRAM_DDR1;
  673. break;
  674. case 8:
  675. debug("DIMM slot %lu: DDR2 SDRAM detected\n", dimm_num);
  676. dimm_populated[dimm_num] = SDRAM_DDR2;
  677. break;
  678. default:
  679. printf("ERROR: Unknown DIMM detected in slot %d.\n",
  680. (unsigned int)dimm_num);
  681. printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
  682. printf("Replace the DIMM module with a supported DIMM.\n\n");
  683. spd_ddr_init_hang ();
  684. break;
  685. }
  686. }
  687. }
  688. for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
  689. if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
  690. && (dimm_populated[dimm_num] != SDRAM_NONE)
  691. && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
  692. printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
  693. spd_ddr_init_hang ();
  694. }
  695. }
  696. }
  697. /*------------------------------------------------------------------
  698. * For the memory DIMMs installed, this routine verifies that
  699. * frequency previously calculated is supported.
  700. *-----------------------------------------------------------------*/
  701. static void check_frequency(unsigned long *dimm_populated,
  702. unsigned char *iic0_dimm_addr,
  703. unsigned long num_dimm_banks)
  704. {
  705. unsigned long dimm_num;
  706. unsigned long tcyc_reg;
  707. unsigned long cycle_time;
  708. unsigned long calc_cycle_time;
  709. unsigned long sdram_freq;
  710. unsigned long sdr_ddrpll;
  711. PPC4xx_SYS_INFO board_cfg;
  712. /*------------------------------------------------------------------
  713. * Get the board configuration info.
  714. *-----------------------------------------------------------------*/
  715. get_sys_info(&board_cfg);
  716. mfsdr(SDR0_DDR0, sdr_ddrpll);
  717. sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
  718. /*
  719. * calc_cycle_time is calculated from DDR frequency set by board/chip
  720. * and is expressed in multiple of 10 picoseconds
  721. * to match the way DIMM cycle time is calculated below.
  722. */
  723. calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
  724. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  725. if (dimm_populated[dimm_num] != SDRAM_NONE) {
  726. tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
  727. /*
  728. * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
  729. * the higher order nibble (bits 4-7) designates the cycle time
  730. * to a granularity of 1ns;
  731. * the value presented by the lower order nibble (bits 0-3)
  732. * has a granularity of .1ns and is added to the value designated
  733. * by the higher nibble. In addition, four lines of the lower order
  734. * nibble are assigned to support +.25,+.33, +.66 and +.75.
  735. */
  736. /* Convert from hex to decimal */
  737. if ((tcyc_reg & 0x0F) == 0x0D)
  738. cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
  739. else if ((tcyc_reg & 0x0F) == 0x0C)
  740. cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
  741. else if ((tcyc_reg & 0x0F) == 0x0B)
  742. cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
  743. else if ((tcyc_reg & 0x0F) == 0x0A)
  744. cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
  745. else
  746. cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
  747. ((tcyc_reg & 0x0F)*10);
  748. debug("cycle_time=%lu [10 picoseconds]\n", cycle_time);
  749. if (cycle_time > (calc_cycle_time + 10)) {
  750. /*
  751. * the provided sdram cycle_time is too small
  752. * for the available DIMM cycle_time.
  753. * The additionnal 100ps is here to accept a small incertainty.
  754. */
  755. printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
  756. "slot %d \n while calculated cycle time is %d ps.\n",
  757. (unsigned int)(cycle_time*10),
  758. (unsigned int)dimm_num,
  759. (unsigned int)(calc_cycle_time*10));
  760. printf("Replace the DIMM, or change DDR frequency via "
  761. "strapping bits.\n\n");
  762. spd_ddr_init_hang ();
  763. }
  764. }
  765. }
  766. }
  767. /*------------------------------------------------------------------
  768. * For the memory DIMMs installed, this routine verifies two
  769. * ranks/banks maximum are availables.
  770. *-----------------------------------------------------------------*/
  771. static void check_rank_number(unsigned long *dimm_populated,
  772. unsigned char *iic0_dimm_addr,
  773. unsigned long num_dimm_banks)
  774. {
  775. unsigned long dimm_num;
  776. unsigned long dimm_rank;
  777. unsigned long total_rank = 0;
  778. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  779. if (dimm_populated[dimm_num] != SDRAM_NONE) {
  780. dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
  781. if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
  782. dimm_rank = (dimm_rank & 0x0F) +1;
  783. else
  784. dimm_rank = dimm_rank & 0x0F;
  785. if (dimm_rank > MAXRANKS) {
  786. printf("ERROR: DRAM DIMM detected with %lu ranks in "
  787. "slot %lu is not supported.\n", dimm_rank, dimm_num);
  788. printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
  789. printf("Replace the DIMM module with a supported DIMM.\n\n");
  790. spd_ddr_init_hang ();
  791. } else
  792. total_rank += dimm_rank;
  793. }
  794. if (total_rank > MAXRANKS) {
  795. printf("ERROR: DRAM DIMM detected with a total of %d ranks "
  796. "for all slots.\n", (unsigned int)total_rank);
  797. printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
  798. printf("Remove one of the DIMM modules.\n\n");
  799. spd_ddr_init_hang ();
  800. }
  801. }
  802. }
  803. /*------------------------------------------------------------------
  804. * only support 2.5V modules.
  805. * This routine verifies this.
  806. *-----------------------------------------------------------------*/
  807. static void check_voltage_type(unsigned long *dimm_populated,
  808. unsigned char *iic0_dimm_addr,
  809. unsigned long num_dimm_banks)
  810. {
  811. unsigned long dimm_num;
  812. unsigned long voltage_type;
  813. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  814. if (dimm_populated[dimm_num] != SDRAM_NONE) {
  815. voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
  816. switch (voltage_type) {
  817. case 0x00:
  818. printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
  819. printf("This DIMM is 5.0 Volt/TTL.\n");
  820. printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
  821. (unsigned int)dimm_num);
  822. spd_ddr_init_hang ();
  823. break;
  824. case 0x01:
  825. printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
  826. printf("This DIMM is LVTTL.\n");
  827. printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
  828. (unsigned int)dimm_num);
  829. spd_ddr_init_hang ();
  830. break;
  831. case 0x02:
  832. printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
  833. printf("This DIMM is 1.5 Volt.\n");
  834. printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
  835. (unsigned int)dimm_num);
  836. spd_ddr_init_hang ();
  837. break;
  838. case 0x03:
  839. printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
  840. printf("This DIMM is 3.3 Volt/TTL.\n");
  841. printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
  842. (unsigned int)dimm_num);
  843. spd_ddr_init_hang ();
  844. break;
  845. case 0x04:
  846. /* 2.5 Voltage only for DDR1 */
  847. break;
  848. case 0x05:
  849. /* 1.8 Voltage only for DDR2 */
  850. break;
  851. default:
  852. printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
  853. printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
  854. (unsigned int)dimm_num);
  855. spd_ddr_init_hang ();
  856. break;
  857. }
  858. }
  859. }
  860. }
  861. /*-----------------------------------------------------------------------------+
  862. * program_copt1.
  863. *-----------------------------------------------------------------------------*/
  864. static void program_copt1(unsigned long *dimm_populated,
  865. unsigned char *iic0_dimm_addr,
  866. unsigned long num_dimm_banks)
  867. {
  868. unsigned long dimm_num;
  869. unsigned long mcopt1;
  870. unsigned long ecc_enabled;
  871. unsigned long ecc = 0;
  872. unsigned long data_width = 0;
  873. unsigned long dimm_32bit;
  874. unsigned long dimm_64bit;
  875. unsigned long registered = 0;
  876. unsigned long attribute = 0;
  877. unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
  878. unsigned long bankcount;
  879. unsigned long val;
  880. #ifdef CONFIG_DDR_ECC
  881. ecc_enabled = true;
  882. #else
  883. ecc_enabled = false;
  884. #endif
  885. dimm_32bit = false;
  886. dimm_64bit = false;
  887. buf0 = false;
  888. buf1 = false;
  889. /*------------------------------------------------------------------
  890. * Set memory controller options reg 1, SDRAM_MCOPT1.
  891. *-----------------------------------------------------------------*/
  892. mfsdram(SDRAM_MCOPT1, val);
  893. mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
  894. SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK |
  895. SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
  896. SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
  897. SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
  898. SDRAM_MCOPT1_DREF_MASK);
  899. mcopt1 |= SDRAM_MCOPT1_QDEP;
  900. mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
  901. mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
  902. mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
  903. mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
  904. mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
  905. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  906. if (dimm_populated[dimm_num] != SDRAM_NONE) {
  907. /* test ecc support */
  908. ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
  909. if (ecc != 0x02) /* ecc not supported */
  910. ecc_enabled = false;
  911. /* test bank count */
  912. bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
  913. if (bankcount == 0x04) /* bank count = 4 */
  914. mcopt1 |= SDRAM_MCOPT1_4_BANKS;
  915. else /* bank count = 8 */
  916. mcopt1 |= SDRAM_MCOPT1_8_BANKS;
  917. /* test for buffered/unbuffered, registered, differential clocks */
  918. registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
  919. attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
  920. /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
  921. if (dimm_num == 0) {
  922. if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
  923. mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
  924. if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
  925. mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
  926. if (registered == 1) { /* DDR2 always buffered */
  927. /* TODO: what about above comments ? */
  928. mcopt1 |= SDRAM_MCOPT1_RDEN;
  929. buf0 = true;
  930. } else {
  931. /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
  932. if ((attribute & 0x02) == 0x00) {
  933. /* buffered not supported */
  934. buf0 = false;
  935. } else {
  936. mcopt1 |= SDRAM_MCOPT1_RDEN;
  937. buf0 = true;
  938. }
  939. }
  940. }
  941. else if (dimm_num == 1) {
  942. if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
  943. mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
  944. if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
  945. mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
  946. if (registered == 1) {
  947. /* DDR2 always buffered */
  948. mcopt1 |= SDRAM_MCOPT1_RDEN;
  949. buf1 = true;
  950. } else {
  951. if ((attribute & 0x02) == 0x00) {
  952. /* buffered not supported */
  953. buf1 = false;
  954. } else {
  955. mcopt1 |= SDRAM_MCOPT1_RDEN;
  956. buf1 = true;
  957. }
  958. }
  959. }
  960. /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
  961. data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
  962. (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
  963. switch (data_width) {
  964. case 72:
  965. case 64:
  966. dimm_64bit = true;
  967. break;
  968. case 40:
  969. case 32:
  970. dimm_32bit = true;
  971. break;
  972. default:
  973. printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
  974. data_width);
  975. printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
  976. break;
  977. }
  978. }
  979. }
  980. /* verify matching properties */
  981. if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
  982. if (buf0 != buf1) {
  983. printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
  984. spd_ddr_init_hang ();
  985. }
  986. }
  987. if ((dimm_64bit == true) && (dimm_32bit == true)) {
  988. printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
  989. spd_ddr_init_hang ();
  990. } else if ((dimm_64bit == true) && (dimm_32bit == false)) {
  991. mcopt1 |= SDRAM_MCOPT1_DMWD_64;
  992. } else if ((dimm_64bit == false) && (dimm_32bit == true)) {
  993. mcopt1 |= SDRAM_MCOPT1_DMWD_32;
  994. } else {
  995. printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
  996. spd_ddr_init_hang ();
  997. }
  998. if (ecc_enabled == true)
  999. mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
  1000. else
  1001. mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
  1002. mtsdram(SDRAM_MCOPT1, mcopt1);
  1003. }
  1004. /*-----------------------------------------------------------------------------+
  1005. * program_codt.
  1006. *-----------------------------------------------------------------------------*/
  1007. static void program_codt(unsigned long *dimm_populated,
  1008. unsigned char *iic0_dimm_addr,
  1009. unsigned long num_dimm_banks)
  1010. {
  1011. unsigned long codt;
  1012. unsigned long modt0 = 0;
  1013. unsigned long modt1 = 0;
  1014. unsigned long modt2 = 0;
  1015. unsigned long modt3 = 0;
  1016. unsigned char dimm_num;
  1017. unsigned char dimm_rank;
  1018. unsigned char total_rank = 0;
  1019. unsigned char total_dimm = 0;
  1020. unsigned char dimm_type = 0;
  1021. unsigned char firstSlot = 0;
  1022. /*------------------------------------------------------------------
  1023. * Set the SDRAM Controller On Die Termination Register
  1024. *-----------------------------------------------------------------*/
  1025. mfsdram(SDRAM_CODT, codt);
  1026. codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END);
  1027. codt |= SDRAM_CODT_IO_NMODE;
  1028. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  1029. if (dimm_populated[dimm_num] != SDRAM_NONE) {
  1030. dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
  1031. if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
  1032. dimm_rank = (dimm_rank & 0x0F) + 1;
  1033. dimm_type = SDRAM_DDR2;
  1034. } else {
  1035. dimm_rank = dimm_rank & 0x0F;
  1036. dimm_type = SDRAM_DDR1;
  1037. }
  1038. total_rank += dimm_rank;
  1039. total_dimm++;
  1040. if ((dimm_num == 0) && (total_dimm == 1))
  1041. firstSlot = true;
  1042. else
  1043. firstSlot = false;
  1044. }
  1045. }
  1046. if (dimm_type == SDRAM_DDR2) {
  1047. codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
  1048. if ((total_dimm == 1) && (firstSlot == true)) {
  1049. if (total_rank == 1) { /* PUUU */
  1050. codt |= CALC_ODT_R(0);
  1051. modt0 = CALC_ODT_W(0);
  1052. modt1 = 0x00000000;
  1053. modt2 = 0x00000000;
  1054. modt3 = 0x00000000;
  1055. }
  1056. if (total_rank == 2) { /* PPUU */
  1057. codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
  1058. modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
  1059. modt1 = 0x00000000;
  1060. modt2 = 0x00000000;
  1061. modt3 = 0x00000000;
  1062. }
  1063. } else if ((total_dimm == 1) && (firstSlot != true)) {
  1064. if (total_rank == 1) { /* UUPU */
  1065. codt |= CALC_ODT_R(2);
  1066. modt0 = 0x00000000;
  1067. modt1 = 0x00000000;
  1068. modt2 = CALC_ODT_W(2);
  1069. modt3 = 0x00000000;
  1070. }
  1071. if (total_rank == 2) { /* UUPP */
  1072. codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
  1073. modt0 = 0x00000000;
  1074. modt1 = 0x00000000;
  1075. modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
  1076. modt3 = 0x00000000;
  1077. }
  1078. }
  1079. if (total_dimm == 2) {
  1080. if (total_rank == 2) { /* PUPU */
  1081. codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
  1082. modt0 = CALC_ODT_RW(2);
  1083. modt1 = 0x00000000;
  1084. modt2 = CALC_ODT_RW(0);
  1085. modt3 = 0x00000000;
  1086. }
  1087. if (total_rank == 4) { /* PPPP */
  1088. codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
  1089. CALC_ODT_R(2) | CALC_ODT_R(3);
  1090. modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
  1091. modt1 = 0x00000000;
  1092. modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
  1093. modt3 = 0x00000000;
  1094. }
  1095. }
  1096. } else {
  1097. codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
  1098. modt0 = 0x00000000;
  1099. modt1 = 0x00000000;
  1100. modt2 = 0x00000000;
  1101. modt3 = 0x00000000;
  1102. if (total_dimm == 1) {
  1103. if (total_rank == 1)
  1104. codt |= 0x00800000;
  1105. if (total_rank == 2)
  1106. codt |= 0x02800000;
  1107. }
  1108. if (total_dimm == 2) {
  1109. if (total_rank == 2)
  1110. codt |= 0x08800000;
  1111. if (total_rank == 4)
  1112. codt |= 0x2a800000;
  1113. }
  1114. }
  1115. debug("nb of dimm %d\n", total_dimm);
  1116. debug("nb of rank %d\n", total_rank);
  1117. if (total_dimm == 1)
  1118. debug("dimm in slot %d\n", firstSlot);
  1119. mtsdram(SDRAM_CODT, codt);
  1120. mtsdram(SDRAM_MODT0, modt0);
  1121. mtsdram(SDRAM_MODT1, modt1);
  1122. mtsdram(SDRAM_MODT2, modt2);
  1123. mtsdram(SDRAM_MODT3, modt3);
  1124. }
  1125. /*-----------------------------------------------------------------------------+
  1126. * program_initplr.
  1127. *-----------------------------------------------------------------------------*/
  1128. static void program_initplr(unsigned long *dimm_populated,
  1129. unsigned char *iic0_dimm_addr,
  1130. unsigned long num_dimm_banks,
  1131. ddr_cas_id_t selected_cas,
  1132. int write_recovery)
  1133. {
  1134. u32 cas = 0;
  1135. u32 odt = 0;
  1136. u32 ods = 0;
  1137. u32 mr;
  1138. u32 wr;
  1139. u32 emr;
  1140. u32 emr2;
  1141. u32 emr3;
  1142. int dimm_num;
  1143. int total_dimm = 0;
  1144. /******************************************************
  1145. ** Assumption: if more than one DIMM, all DIMMs are the same
  1146. ** as already checked in check_memory_type
  1147. ******************************************************/
  1148. if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
  1149. mtsdram(SDRAM_INITPLR0, 0x81B80000);
  1150. mtsdram(SDRAM_INITPLR1, 0x81900400);
  1151. mtsdram(SDRAM_INITPLR2, 0x81810000);
  1152. mtsdram(SDRAM_INITPLR3, 0xff800162);
  1153. mtsdram(SDRAM_INITPLR4, 0x81900400);
  1154. mtsdram(SDRAM_INITPLR5, 0x86080000);
  1155. mtsdram(SDRAM_INITPLR6, 0x86080000);
  1156. mtsdram(SDRAM_INITPLR7, 0x81000062);
  1157. } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
  1158. switch (selected_cas) {
  1159. case DDR_CAS_3:
  1160. cas = 3 << 4;
  1161. break;
  1162. case DDR_CAS_4:
  1163. cas = 4 << 4;
  1164. break;
  1165. case DDR_CAS_5:
  1166. cas = 5 << 4;
  1167. break;
  1168. default:
  1169. printf("ERROR: ucode error on selected_cas value %d", selected_cas);
  1170. spd_ddr_init_hang ();
  1171. break;
  1172. }
  1173. #if 0
  1174. /*
  1175. * ToDo - Still a problem with the write recovery:
  1176. * On the Corsair CM2X512-5400C4 module, setting write recovery
  1177. * in the INITPLR reg to the value calculated in program_mode()
  1178. * results in not correctly working DDR2 memory (crash after
  1179. * relocation).
  1180. *
  1181. * So for now, set the write recovery to 3. This seems to work
  1182. * on the Corair module too.
  1183. *
  1184. * 2007-03-01, sr
  1185. */
  1186. switch (write_recovery) {
  1187. case 3:
  1188. wr = WRITE_RECOV_3;
  1189. break;
  1190. case 4:
  1191. wr = WRITE_RECOV_4;
  1192. break;
  1193. case 5:
  1194. wr = WRITE_RECOV_5;
  1195. break;
  1196. case 6:
  1197. wr = WRITE_RECOV_6;
  1198. break;
  1199. default:
  1200. printf("ERROR: write recovery not support (%d)", write_recovery);
  1201. spd_ddr_init_hang ();
  1202. break;
  1203. }
  1204. #else
  1205. wr = WRITE_RECOV_3; /* test-only, see description above */
  1206. #endif
  1207. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
  1208. if (dimm_populated[dimm_num] != SDRAM_NONE)
  1209. total_dimm++;
  1210. if (total_dimm == 1) {
  1211. odt = ODT_150_OHM;
  1212. ods = ODS_FULL;
  1213. } else if (total_dimm == 2) {
  1214. odt = ODT_75_OHM;
  1215. ods = ODS_REDUCED;
  1216. } else {
  1217. printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
  1218. spd_ddr_init_hang ();
  1219. }
  1220. mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
  1221. emr = CMD_EMR | SELECT_EMR | odt | ods;
  1222. emr2 = CMD_EMR | SELECT_EMR2;
  1223. emr3 = CMD_EMR | SELECT_EMR3;
  1224. /* NOP - Wait 106 MemClk cycles */
  1225. mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP |
  1226. SDRAM_INITPLR_IMWT_ENCODE(106));
  1227. udelay(1000);
  1228. /* precharge 4 MemClk cycles */
  1229. mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
  1230. SDRAM_INITPLR_IMWT_ENCODE(4));
  1231. /* EMR2 - Wait tMRD (2 MemClk cycles) */
  1232. mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 |
  1233. SDRAM_INITPLR_IMWT_ENCODE(2));
  1234. /* EMR3 - Wait tMRD (2 MemClk cycles) */
  1235. mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 |
  1236. SDRAM_INITPLR_IMWT_ENCODE(2));
  1237. /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
  1238. mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr |
  1239. SDRAM_INITPLR_IMWT_ENCODE(2));
  1240. /* MR w/ DLL reset - 200 cycle wait for DLL reset */
  1241. mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET |
  1242. SDRAM_INITPLR_IMWT_ENCODE(200));
  1243. udelay(1000);
  1244. /* precharge 4 MemClk cycles */
  1245. mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
  1246. SDRAM_INITPLR_IMWT_ENCODE(4));
  1247. /* Refresh 25 MemClk cycles */
  1248. mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
  1249. SDRAM_INITPLR_IMWT_ENCODE(25));
  1250. /* Refresh 25 MemClk cycles */
  1251. mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
  1252. SDRAM_INITPLR_IMWT_ENCODE(25));
  1253. /* Refresh 25 MemClk cycles */
  1254. mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
  1255. SDRAM_INITPLR_IMWT_ENCODE(25));
  1256. /* Refresh 25 MemClk cycles */
  1257. mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
  1258. SDRAM_INITPLR_IMWT_ENCODE(25));
  1259. /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
  1260. mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr |
  1261. SDRAM_INITPLR_IMWT_ENCODE(2));
  1262. /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
  1263. mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF |
  1264. SDRAM_INITPLR_IMWT_ENCODE(2) | emr);
  1265. /* EMR OCD Exit */
  1266. mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr |
  1267. SDRAM_INITPLR_IMWT_ENCODE(2));
  1268. } else {
  1269. printf("ERROR: ucode error as unknown DDR type in program_initplr");
  1270. spd_ddr_init_hang ();
  1271. }
  1272. }
  1273. /*------------------------------------------------------------------
  1274. * This routine programs the SDRAM_MMODE register.
  1275. * the selected_cas is an output parameter, that will be passed
  1276. * by caller to call the above program_initplr( )
  1277. *-----------------------------------------------------------------*/
  1278. static void program_mode(unsigned long *dimm_populated,
  1279. unsigned char *iic0_dimm_addr,
  1280. unsigned long num_dimm_banks,
  1281. ddr_cas_id_t *selected_cas,
  1282. int *write_recovery)
  1283. {
  1284. unsigned long dimm_num;
  1285. unsigned long sdram_ddr1;
  1286. unsigned long t_wr_ns;
  1287. unsigned long t_wr_clk;
  1288. unsigned long cas_bit;
  1289. unsigned long cas_index;
  1290. unsigned long sdram_freq;
  1291. unsigned long ddr_check;
  1292. unsigned long mmode;
  1293. unsigned long tcyc_reg;
  1294. unsigned long cycle_2_0_clk;
  1295. unsigned long cycle_2_5_clk;
  1296. unsigned long cycle_3_0_clk;
  1297. unsigned long cycle_4_0_clk;
  1298. unsigned long cycle_5_0_clk;
  1299. unsigned long max_2_0_tcyc_ns_x_100;
  1300. unsigned long max_2_5_tcyc_ns_x_100;
  1301. unsigned long max_3_0_tcyc_ns_x_100;
  1302. unsigned long max_4_0_tcyc_ns_x_100;
  1303. unsigned long max_5_0_tcyc_ns_x_100;
  1304. unsigned long cycle_time_ns_x_100[3];
  1305. PPC4xx_SYS_INFO board_cfg;
  1306. unsigned char cas_2_0_available;
  1307. unsigned char cas_2_5_available;
  1308. unsigned char cas_3_0_available;
  1309. unsigned char cas_4_0_available;
  1310. unsigned char cas_5_0_available;
  1311. unsigned long sdr_ddrpll;
  1312. /*------------------------------------------------------------------
  1313. * Get the board configuration info.
  1314. *-----------------------------------------------------------------*/
  1315. get_sys_info(&board_cfg);
  1316. mfsdr(SDR0_DDR0, sdr_ddrpll);
  1317. sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
  1318. debug("sdram_freq=%lu\n", sdram_freq);
  1319. /*------------------------------------------------------------------
  1320. * Handle the timing. We need to find the worst case timing of all
  1321. * the dimm modules installed.
  1322. *-----------------------------------------------------------------*/
  1323. t_wr_ns = 0;
  1324. cas_2_0_available = true;
  1325. cas_2_5_available = true;
  1326. cas_3_0_available = true;
  1327. cas_4_0_available = true;
  1328. cas_5_0_available = true;
  1329. max_2_0_tcyc_ns_x_100 = 10;
  1330. max_2_5_tcyc_ns_x_100 = 10;
  1331. max_3_0_tcyc_ns_x_100 = 10;
  1332. max_4_0_tcyc_ns_x_100 = 10;
  1333. max_5_0_tcyc_ns_x_100 = 10;
  1334. sdram_ddr1 = true;
  1335. /* loop through all the DIMM slots on the board */
  1336. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  1337. /* If a dimm is installed in a particular slot ... */
  1338. if (dimm_populated[dimm_num] != SDRAM_NONE) {
  1339. if (dimm_populated[dimm_num] == SDRAM_DDR1)
  1340. sdram_ddr1 = true;
  1341. else
  1342. sdram_ddr1 = false;
  1343. cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
  1344. debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
  1345. /* For a particular DIMM, grab the three CAS values it supports */
  1346. for (cas_index = 0; cas_index < 3; cas_index++) {
  1347. switch (cas_index) {
  1348. case 0:
  1349. tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
  1350. break;
  1351. case 1:
  1352. tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
  1353. break;
  1354. default:
  1355. tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
  1356. break;
  1357. }
  1358. if ((tcyc_reg & 0x0F) >= 10) {
  1359. if ((tcyc_reg & 0x0F) == 0x0D) {
  1360. /* Convert from hex to decimal */
  1361. cycle_time_ns_x_100[cas_index] =
  1362. (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
  1363. } else {
  1364. printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
  1365. "in slot %d\n", (unsigned int)dimm_num);
  1366. spd_ddr_init_hang ();
  1367. }
  1368. } else {
  1369. /* Convert from hex to decimal */
  1370. cycle_time_ns_x_100[cas_index] =
  1371. (((tcyc_reg & 0xF0) >> 4) * 100) +
  1372. ((tcyc_reg & 0x0F)*10);
  1373. }
  1374. debug("cas_index=%lu: cycle_time_ns_x_100=%lu\n", cas_index,
  1375. cycle_time_ns_x_100[cas_index]);
  1376. }
  1377. /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
  1378. /* supported for a particular DIMM. */
  1379. cas_index = 0;
  1380. if (sdram_ddr1) {
  1381. /*
  1382. * DDR devices use the following bitmask for CAS latency:
  1383. * Bit 7 6 5 4 3 2 1 0
  1384. * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0
  1385. */
  1386. if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
  1387. (cycle_time_ns_x_100[cas_index] != 0)) {
  1388. max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
  1389. cycle_time_ns_x_100[cas_index]);
  1390. cas_index++;
  1391. } else {
  1392. if (cas_index != 0)
  1393. cas_index++;
  1394. cas_4_0_available = false;
  1395. }
  1396. if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
  1397. (cycle_time_ns_x_100[cas_index] != 0)) {
  1398. max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
  1399. cycle_time_ns_x_100[cas_index]);
  1400. cas_index++;
  1401. } else {
  1402. if (cas_index != 0)
  1403. cas_index++;
  1404. cas_3_0_available = false;
  1405. }
  1406. if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
  1407. (cycle_time_ns_x_100[cas_index] != 0)) {
  1408. max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
  1409. cycle_time_ns_x_100[cas_index]);
  1410. cas_index++;
  1411. } else {
  1412. if (cas_index != 0)
  1413. cas_index++;
  1414. cas_2_5_available = false;
  1415. }
  1416. if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
  1417. (cycle_time_ns_x_100[cas_index] != 0)) {
  1418. max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
  1419. cycle_time_ns_x_100[cas_index]);
  1420. cas_index++;
  1421. } else {
  1422. if (cas_index != 0)
  1423. cas_index++;
  1424. cas_2_0_available = false;
  1425. }
  1426. } else {
  1427. /*
  1428. * DDR2 devices use the following bitmask for CAS latency:
  1429. * Bit 7 6 5 4 3 2 1 0
  1430. * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
  1431. */
  1432. if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
  1433. (cycle_time_ns_x_100[cas_index] != 0)) {
  1434. max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
  1435. cycle_time_ns_x_100[cas_index]);
  1436. cas_index++;
  1437. } else {
  1438. if (cas_index != 0)
  1439. cas_index++;
  1440. cas_5_0_available = false;
  1441. }
  1442. if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
  1443. (cycle_time_ns_x_100[cas_index] != 0)) {
  1444. max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
  1445. cycle_time_ns_x_100[cas_index]);
  1446. cas_index++;
  1447. } else {
  1448. if (cas_index != 0)
  1449. cas_index++;
  1450. cas_4_0_available = false;
  1451. }
  1452. if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
  1453. (cycle_time_ns_x_100[cas_index] != 0)) {
  1454. max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
  1455. cycle_time_ns_x_100[cas_index]);
  1456. cas_index++;
  1457. } else {
  1458. if (cas_index != 0)
  1459. cas_index++;
  1460. cas_3_0_available = false;
  1461. }
  1462. }
  1463. }
  1464. }
  1465. /*------------------------------------------------------------------
  1466. * Set the SDRAM mode, SDRAM_MMODE
  1467. *-----------------------------------------------------------------*/
  1468. mfsdram(SDRAM_MMODE, mmode);
  1469. mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
  1470. /* add 10 here because of rounding problems */
  1471. cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
  1472. cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
  1473. cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
  1474. cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
  1475. cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
  1476. debug("cycle_3_0_clk=%lu\n", cycle_3_0_clk);
  1477. debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk);
  1478. debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk);
  1479. if (sdram_ddr1 == true) { /* DDR1 */
  1480. if ((cas_2_0_available == true) &&
  1481. (sdram_freq <= cycle_2_0_clk)) {
  1482. mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
  1483. *selected_cas = DDR_CAS_2;
  1484. } else if ((cas_2_5_available == true) &&
  1485. (sdram_freq <= cycle_2_5_clk)) {
  1486. mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
  1487. *selected_cas = DDR_CAS_2_5;
  1488. } else if ((cas_3_0_available == true) &&
  1489. (sdram_freq <= cycle_3_0_clk)) {
  1490. mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
  1491. *selected_cas = DDR_CAS_3;
  1492. } else {
  1493. printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
  1494. printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
  1495. printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
  1496. spd_ddr_init_hang ();
  1497. }
  1498. } else { /* DDR2 */
  1499. debug("cas_3_0_available=%d\n", cas_3_0_available);
  1500. debug("cas_4_0_available=%d\n", cas_4_0_available);
  1501. debug("cas_5_0_available=%d\n", cas_5_0_available);
  1502. if ((cas_3_0_available == true) &&
  1503. (sdram_freq <= cycle_3_0_clk)) {
  1504. mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
  1505. *selected_cas = DDR_CAS_3;
  1506. } else if ((cas_4_0_available == true) &&
  1507. (sdram_freq <= cycle_4_0_clk)) {
  1508. mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
  1509. *selected_cas = DDR_CAS_4;
  1510. } else if ((cas_5_0_available == true) &&
  1511. (sdram_freq <= cycle_5_0_clk)) {
  1512. mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
  1513. *selected_cas = DDR_CAS_5;
  1514. } else {
  1515. printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
  1516. printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
  1517. printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
  1518. printf("cas3=%d cas4=%d cas5=%d\n",
  1519. cas_3_0_available, cas_4_0_available, cas_5_0_available);
  1520. printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
  1521. sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
  1522. spd_ddr_init_hang ();
  1523. }
  1524. }
  1525. if (sdram_ddr1 == true)
  1526. mmode |= SDRAM_MMODE_WR_DDR1;
  1527. else {
  1528. /* loop through all the DIMM slots on the board */
  1529. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  1530. /* If a dimm is installed in a particular slot ... */
  1531. if (dimm_populated[dimm_num] != SDRAM_NONE)
  1532. t_wr_ns = max(t_wr_ns,
  1533. spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
  1534. }
  1535. /*
  1536. * convert from nanoseconds to ddr clocks
  1537. * round up if necessary
  1538. */
  1539. t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
  1540. ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
  1541. if (sdram_freq != ddr_check)
  1542. t_wr_clk++;
  1543. switch (t_wr_clk) {
  1544. case 0:
  1545. case 1:
  1546. case 2:
  1547. case 3:
  1548. mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
  1549. break;
  1550. case 4:
  1551. mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
  1552. break;
  1553. case 5:
  1554. mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
  1555. break;
  1556. default:
  1557. mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
  1558. break;
  1559. }
  1560. *write_recovery = t_wr_clk;
  1561. }
  1562. debug("CAS latency = %d\n", *selected_cas);
  1563. debug("Write recovery = %d\n", *write_recovery);
  1564. mtsdram(SDRAM_MMODE, mmode);
  1565. }
  1566. /*-----------------------------------------------------------------------------+
  1567. * program_rtr.
  1568. *-----------------------------------------------------------------------------*/
  1569. static void program_rtr(unsigned long *dimm_populated,
  1570. unsigned char *iic0_dimm_addr,
  1571. unsigned long num_dimm_banks)
  1572. {
  1573. PPC4xx_SYS_INFO board_cfg;
  1574. unsigned long max_refresh_rate;
  1575. unsigned long dimm_num;
  1576. unsigned long refresh_rate_type;
  1577. unsigned long refresh_rate;
  1578. unsigned long rint;
  1579. unsigned long sdram_freq;
  1580. unsigned long sdr_ddrpll;
  1581. unsigned long val;
  1582. /*------------------------------------------------------------------
  1583. * Get the board configuration info.
  1584. *-----------------------------------------------------------------*/
  1585. get_sys_info(&board_cfg);
  1586. /*------------------------------------------------------------------
  1587. * Set the SDRAM Refresh Timing Register, SDRAM_RTR
  1588. *-----------------------------------------------------------------*/
  1589. mfsdr(SDR0_DDR0, sdr_ddrpll);
  1590. sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
  1591. max_refresh_rate = 0;
  1592. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  1593. if (dimm_populated[dimm_num] != SDRAM_NONE) {
  1594. refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
  1595. refresh_rate_type &= 0x7F;
  1596. switch (refresh_rate_type) {
  1597. case 0:
  1598. refresh_rate = 15625;
  1599. break;
  1600. case 1:
  1601. refresh_rate = 3906;
  1602. break;
  1603. case 2:
  1604. refresh_rate = 7812;
  1605. break;
  1606. case 3:
  1607. refresh_rate = 31250;
  1608. break;
  1609. case 4:
  1610. refresh_rate = 62500;
  1611. break;
  1612. case 5:
  1613. refresh_rate = 125000;
  1614. break;
  1615. default:
  1616. refresh_rate = 0;
  1617. printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
  1618. (unsigned int)dimm_num);
  1619. printf("Replace the DIMM module with a supported DIMM.\n\n");
  1620. spd_ddr_init_hang ();
  1621. break;
  1622. }
  1623. max_refresh_rate = max(max_refresh_rate, refresh_rate);
  1624. }
  1625. }
  1626. rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
  1627. mfsdram(SDRAM_RTR, val);
  1628. mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
  1629. (SDRAM_RTR_RINT_ENCODE(rint)));
  1630. }
  1631. /*------------------------------------------------------------------
  1632. * This routine programs the SDRAM_TRx registers.
  1633. *-----------------------------------------------------------------*/
  1634. static void program_tr(unsigned long *dimm_populated,
  1635. unsigned char *iic0_dimm_addr,
  1636. unsigned long num_dimm_banks)
  1637. {
  1638. unsigned long dimm_num;
  1639. unsigned long sdram_ddr1;
  1640. unsigned long t_rp_ns;
  1641. unsigned long t_rcd_ns;
  1642. unsigned long t_rrd_ns;
  1643. unsigned long t_ras_ns;
  1644. unsigned long t_rc_ns;
  1645. unsigned long t_rfc_ns;
  1646. unsigned long t_wpc_ns;
  1647. unsigned long t_wtr_ns;
  1648. unsigned long t_rpc_ns;
  1649. unsigned long t_rp_clk;
  1650. unsigned long t_rcd_clk;
  1651. unsigned long t_rrd_clk;
  1652. unsigned long t_ras_clk;
  1653. unsigned long t_rc_clk;
  1654. unsigned long t_rfc_clk;
  1655. unsigned long t_wpc_clk;
  1656. unsigned long t_wtr_clk;
  1657. unsigned long t_rpc_clk;
  1658. unsigned long sdtr1, sdtr2, sdtr3;
  1659. unsigned long ddr_check;
  1660. unsigned long sdram_freq;
  1661. unsigned long sdr_ddrpll;
  1662. PPC4xx_SYS_INFO board_cfg;
  1663. /*------------------------------------------------------------------
  1664. * Get the board configuration info.
  1665. *-----------------------------------------------------------------*/
  1666. get_sys_info(&board_cfg);
  1667. mfsdr(SDR0_DDR0, sdr_ddrpll);
  1668. sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
  1669. /*------------------------------------------------------------------
  1670. * Handle the timing. We need to find the worst case timing of all
  1671. * the dimm modules installed.
  1672. *-----------------------------------------------------------------*/
  1673. t_rp_ns = 0;
  1674. t_rrd_ns = 0;
  1675. t_rcd_ns = 0;
  1676. t_ras_ns = 0;
  1677. t_rc_ns = 0;
  1678. t_rfc_ns = 0;
  1679. t_wpc_ns = 0;
  1680. t_wtr_ns = 0;
  1681. t_rpc_ns = 0;
  1682. sdram_ddr1 = true;
  1683. /* loop through all the DIMM slots on the board */
  1684. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  1685. /* If a dimm is installed in a particular slot ... */
  1686. if (dimm_populated[dimm_num] != SDRAM_NONE) {
  1687. if (dimm_populated[dimm_num] == SDRAM_DDR2)
  1688. sdram_ddr1 = true;
  1689. else
  1690. sdram_ddr1 = false;
  1691. t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
  1692. t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
  1693. t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
  1694. t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
  1695. t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41));
  1696. t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
  1697. }
  1698. }
  1699. /*------------------------------------------------------------------
  1700. * Set the SDRAM Timing Reg 1, SDRAM_TR1
  1701. *-----------------------------------------------------------------*/
  1702. mfsdram(SDRAM_SDTR1, sdtr1);
  1703. sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
  1704. SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
  1705. /* default values */
  1706. sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
  1707. sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
  1708. /* normal operations */
  1709. sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
  1710. sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
  1711. mtsdram(SDRAM_SDTR1, sdtr1);
  1712. /*------------------------------------------------------------------
  1713. * Set the SDRAM Timing Reg 2, SDRAM_TR2
  1714. *-----------------------------------------------------------------*/
  1715. mfsdram(SDRAM_SDTR2, sdtr2);
  1716. sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK |
  1717. SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
  1718. SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK |
  1719. SDRAM_SDTR2_RRD_MASK);
  1720. /*
  1721. * convert t_rcd from nanoseconds to ddr clocks
  1722. * round up if necessary
  1723. */
  1724. t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
  1725. ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
  1726. if (sdram_freq != ddr_check)
  1727. t_rcd_clk++;
  1728. switch (t_rcd_clk) {
  1729. case 0:
  1730. case 1:
  1731. sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
  1732. break;
  1733. case 2:
  1734. sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
  1735. break;
  1736. case 3:
  1737. sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
  1738. break;
  1739. case 4:
  1740. sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
  1741. break;
  1742. default:
  1743. sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
  1744. break;
  1745. }
  1746. if (sdram_ddr1 == true) { /* DDR1 */
  1747. if (sdram_freq < 200000000) {
  1748. sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
  1749. sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
  1750. sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
  1751. } else {
  1752. sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
  1753. sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
  1754. sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
  1755. }
  1756. } else { /* DDR2 */
  1757. /* loop through all the DIMM slots on the board */
  1758. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  1759. /* If a dimm is installed in a particular slot ... */
  1760. if (dimm_populated[dimm_num] != SDRAM_NONE) {
  1761. t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
  1762. t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
  1763. t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
  1764. }
  1765. }
  1766. /*
  1767. * convert from nanoseconds to ddr clocks
  1768. * round up if necessary
  1769. */
  1770. t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
  1771. ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
  1772. if (sdram_freq != ddr_check)
  1773. t_wpc_clk++;
  1774. switch (t_wpc_clk) {
  1775. case 0:
  1776. case 1:
  1777. case 2:
  1778. sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
  1779. break;
  1780. case 3:
  1781. sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
  1782. break;
  1783. case 4:
  1784. sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
  1785. break;
  1786. case 5:
  1787. sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
  1788. break;
  1789. default:
  1790. sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
  1791. break;
  1792. }
  1793. /*
  1794. * convert from nanoseconds to ddr clocks
  1795. * round up if necessary
  1796. */
  1797. t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
  1798. ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
  1799. if (sdram_freq != ddr_check)
  1800. t_wtr_clk++;
  1801. switch (t_wtr_clk) {
  1802. case 0:
  1803. case 1:
  1804. sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
  1805. break;
  1806. case 2:
  1807. sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
  1808. break;
  1809. case 3:
  1810. sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
  1811. break;
  1812. default:
  1813. sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
  1814. break;
  1815. }
  1816. /*
  1817. * convert from nanoseconds to ddr clocks
  1818. * round up if necessary
  1819. */
  1820. t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
  1821. ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
  1822. if (sdram_freq != ddr_check)
  1823. t_rpc_clk++;
  1824. switch (t_rpc_clk) {
  1825. case 0:
  1826. case 1:
  1827. case 2:
  1828. sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
  1829. break;
  1830. case 3:
  1831. sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
  1832. break;
  1833. default:
  1834. sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
  1835. break;
  1836. }
  1837. }
  1838. /* default value */
  1839. sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
  1840. /*
  1841. * convert t_rrd from nanoseconds to ddr clocks
  1842. * round up if necessary
  1843. */
  1844. t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
  1845. ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
  1846. if (sdram_freq != ddr_check)
  1847. t_rrd_clk++;
  1848. if (t_rrd_clk == 3)
  1849. sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
  1850. else
  1851. sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
  1852. /*
  1853. * convert t_rp from nanoseconds to ddr clocks
  1854. * round up if necessary
  1855. */
  1856. t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
  1857. ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
  1858. if (sdram_freq != ddr_check)
  1859. t_rp_clk++;
  1860. switch (t_rp_clk) {
  1861. case 0:
  1862. case 1:
  1863. case 2:
  1864. case 3:
  1865. sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
  1866. break;
  1867. case 4:
  1868. sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
  1869. break;
  1870. case 5:
  1871. sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
  1872. break;
  1873. case 6:
  1874. sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
  1875. break;
  1876. default:
  1877. sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
  1878. break;
  1879. }
  1880. mtsdram(SDRAM_SDTR2, sdtr2);
  1881. /*------------------------------------------------------------------
  1882. * Set the SDRAM Timing Reg 3, SDRAM_TR3
  1883. *-----------------------------------------------------------------*/
  1884. mfsdram(SDRAM_SDTR3, sdtr3);
  1885. sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK |
  1886. SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
  1887. /*
  1888. * convert t_ras from nanoseconds to ddr clocks
  1889. * round up if necessary
  1890. */
  1891. t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
  1892. ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
  1893. if (sdram_freq != ddr_check)
  1894. t_ras_clk++;
  1895. sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
  1896. /*
  1897. * convert t_rc from nanoseconds to ddr clocks
  1898. * round up if necessary
  1899. */
  1900. t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
  1901. ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
  1902. if (sdram_freq != ddr_check)
  1903. t_rc_clk++;
  1904. sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
  1905. /* default xcs value */
  1906. sdtr3 |= SDRAM_SDTR3_XCS;
  1907. /*
  1908. * convert t_rfc from nanoseconds to ddr clocks
  1909. * round up if necessary
  1910. */
  1911. t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
  1912. ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
  1913. if (sdram_freq != ddr_check)
  1914. t_rfc_clk++;
  1915. sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
  1916. mtsdram(SDRAM_SDTR3, sdtr3);
  1917. }
  1918. /*-----------------------------------------------------------------------------+
  1919. * program_bxcf.
  1920. *-----------------------------------------------------------------------------*/
  1921. static void program_bxcf(unsigned long *dimm_populated,
  1922. unsigned char *iic0_dimm_addr,
  1923. unsigned long num_dimm_banks)
  1924. {
  1925. unsigned long dimm_num;
  1926. unsigned long num_col_addr;
  1927. unsigned long num_ranks;
  1928. unsigned long num_banks;
  1929. unsigned long mode;
  1930. unsigned long ind_rank;
  1931. unsigned long ind;
  1932. unsigned long ind_bank;
  1933. unsigned long bank_0_populated;
  1934. /*------------------------------------------------------------------
  1935. * Set the BxCF regs. First, wipe out the bank config registers.
  1936. *-----------------------------------------------------------------*/
  1937. mtsdram(SDRAM_MB0CF, 0x00000000);
  1938. mtsdram(SDRAM_MB1CF, 0x00000000);
  1939. mtsdram(SDRAM_MB2CF, 0x00000000);
  1940. mtsdram(SDRAM_MB3CF, 0x00000000);
  1941. mode = SDRAM_BXCF_M_BE_ENABLE;
  1942. bank_0_populated = 0;
  1943. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  1944. if (dimm_populated[dimm_num] != SDRAM_NONE) {
  1945. num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
  1946. num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
  1947. if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
  1948. num_ranks = (num_ranks & 0x0F) +1;
  1949. else
  1950. num_ranks = num_ranks & 0x0F;
  1951. num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
  1952. for (ind_bank = 0; ind_bank < 2; ind_bank++) {
  1953. if (num_banks == 4)
  1954. ind = 0;
  1955. else
  1956. ind = 5 << 8;
  1957. switch (num_col_addr) {
  1958. case 0x08:
  1959. mode |= (SDRAM_BXCF_M_AM_0 + ind);
  1960. break;
  1961. case 0x09:
  1962. mode |= (SDRAM_BXCF_M_AM_1 + ind);
  1963. break;
  1964. case 0x0A:
  1965. mode |= (SDRAM_BXCF_M_AM_2 + ind);
  1966. break;
  1967. case 0x0B:
  1968. mode |= (SDRAM_BXCF_M_AM_3 + ind);
  1969. break;
  1970. case 0x0C:
  1971. mode |= (SDRAM_BXCF_M_AM_4 + ind);
  1972. break;
  1973. default:
  1974. printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
  1975. (unsigned int)dimm_num);
  1976. printf("ERROR: Unsupported value for number of "
  1977. "column addresses: %d.\n", (unsigned int)num_col_addr);
  1978. printf("Replace the DIMM module with a supported DIMM.\n\n");
  1979. spd_ddr_init_hang ();
  1980. }
  1981. }
  1982. if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
  1983. bank_0_populated = 1;
  1984. for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
  1985. mtsdram(SDRAM_MB0CF +
  1986. ((dimm_num + bank_0_populated + ind_rank) << 2),
  1987. mode);
  1988. }
  1989. }
  1990. }
  1991. }
  1992. /*------------------------------------------------------------------
  1993. * program memory queue.
  1994. *-----------------------------------------------------------------*/
  1995. static void program_memory_queue(unsigned long *dimm_populated,
  1996. unsigned char *iic0_dimm_addr,
  1997. unsigned long num_dimm_banks)
  1998. {
  1999. unsigned long dimm_num;
  2000. phys_size_t rank_base_addr;
  2001. unsigned long rank_reg;
  2002. phys_size_t rank_size_bytes;
  2003. unsigned long rank_size_id;
  2004. unsigned long num_ranks;
  2005. unsigned long baseadd_size;
  2006. unsigned long i;
  2007. unsigned long bank_0_populated = 0;
  2008. phys_size_t total_size = 0;
  2009. /*------------------------------------------------------------------
  2010. * Reset the rank_base_address.
  2011. *-----------------------------------------------------------------*/
  2012. rank_reg = SDRAM_R0BAS;
  2013. rank_base_addr = 0x00000000;
  2014. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  2015. if (dimm_populated[dimm_num] != SDRAM_NONE) {
  2016. num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
  2017. if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
  2018. num_ranks = (num_ranks & 0x0F) + 1;
  2019. else
  2020. num_ranks = num_ranks & 0x0F;
  2021. rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
  2022. /*------------------------------------------------------------------
  2023. * Set the sizes
  2024. *-----------------------------------------------------------------*/
  2025. baseadd_size = 0;
  2026. switch (rank_size_id) {
  2027. case 0x01:
  2028. baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
  2029. total_size = 1024;
  2030. break;
  2031. case 0x02:
  2032. baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
  2033. total_size = 2048;
  2034. break;
  2035. case 0x04:
  2036. baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
  2037. total_size = 4096;
  2038. break;
  2039. case 0x08:
  2040. baseadd_size |= SDRAM_RXBAS_SDSZ_32;
  2041. total_size = 32;
  2042. break;
  2043. case 0x10:
  2044. baseadd_size |= SDRAM_RXBAS_SDSZ_64;
  2045. total_size = 64;
  2046. break;
  2047. case 0x20:
  2048. baseadd_size |= SDRAM_RXBAS_SDSZ_128;
  2049. total_size = 128;
  2050. break;
  2051. case 0x40:
  2052. baseadd_size |= SDRAM_RXBAS_SDSZ_256;
  2053. total_size = 256;
  2054. break;
  2055. case 0x80:
  2056. baseadd_size |= SDRAM_RXBAS_SDSZ_512;
  2057. total_size = 512;
  2058. break;
  2059. default:
  2060. printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
  2061. (unsigned int)dimm_num);
  2062. printf("ERROR: Unsupported value for the banksize: %d.\n",
  2063. (unsigned int)rank_size_id);
  2064. printf("Replace the DIMM module with a supported DIMM.\n\n");
  2065. spd_ddr_init_hang ();
  2066. }
  2067. rank_size_bytes = total_size << 20;
  2068. if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
  2069. bank_0_populated = 1;
  2070. for (i = 0; i < num_ranks; i++) {
  2071. mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
  2072. (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
  2073. baseadd_size));
  2074. rank_base_addr += rank_size_bytes;
  2075. }
  2076. }
  2077. }
  2078. #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  2079. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  2080. defined(CONFIG_460SX)
  2081. /*
  2082. * Enable high bandwidth access
  2083. * This is currently not used, but with this setup
  2084. * it is possible to use it later on in e.g. the Linux
  2085. * EMAC driver for performance gain.
  2086. */
  2087. mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
  2088. mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
  2089. /*
  2090. * Set optimal value for Memory Queue HB/LL Configuration registers
  2091. */
  2092. mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
  2093. SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
  2094. SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
  2095. mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
  2096. SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
  2097. SDRAM_CONF1LL_RPLM);
  2098. mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
  2099. #endif
  2100. }
  2101. #ifdef CONFIG_DDR_ECC
  2102. /*-----------------------------------------------------------------------------+
  2103. * program_ecc.
  2104. *-----------------------------------------------------------------------------*/
  2105. static void program_ecc(unsigned long *dimm_populated,
  2106. unsigned char *iic0_dimm_addr,
  2107. unsigned long num_dimm_banks,
  2108. unsigned long tlb_word2_i_value)
  2109. {
  2110. unsigned long dimm_num;
  2111. unsigned long ecc;
  2112. ecc = 0;
  2113. /* loop through all the DIMM slots on the board */
  2114. for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
  2115. /* If a dimm is installed in a particular slot ... */
  2116. if (dimm_populated[dimm_num] != SDRAM_NONE)
  2117. ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
  2118. }
  2119. if (ecc == 0)
  2120. return;
  2121. do_program_ecc(tlb_word2_i_value);
  2122. }
  2123. #endif
  2124. #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
  2125. /*-----------------------------------------------------------------------------+
  2126. * program_DQS_calibration.
  2127. *-----------------------------------------------------------------------------*/
  2128. static void program_DQS_calibration(unsigned long *dimm_populated,
  2129. unsigned char *iic0_dimm_addr,
  2130. unsigned long num_dimm_banks)
  2131. {
  2132. unsigned long val;
  2133. #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
  2134. mtsdram(SDRAM_RQDC, 0x80000037);
  2135. mtsdram(SDRAM_RDCC, 0x40000000);
  2136. mtsdram(SDRAM_RFDC, 0x000001DF);
  2137. test();
  2138. #else
  2139. /*------------------------------------------------------------------
  2140. * Program RDCC register
  2141. * Read sample cycle auto-update enable
  2142. *-----------------------------------------------------------------*/
  2143. mfsdram(SDRAM_RDCC, val);
  2144. mtsdram(SDRAM_RDCC,
  2145. (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
  2146. | SDRAM_RDCC_RSAE_ENABLE);
  2147. /*------------------------------------------------------------------
  2148. * Program RQDC register
  2149. * Internal DQS delay mechanism enable
  2150. *-----------------------------------------------------------------*/
  2151. mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
  2152. /*------------------------------------------------------------------
  2153. * Program RFDC register
  2154. * Set Feedback Fractional Oversample
  2155. * Auto-detect read sample cycle enable
  2156. * Set RFOS to 1/4 of memclk cycle (0x3f)
  2157. *-----------------------------------------------------------------*/
  2158. mfsdram(SDRAM_RFDC, val);
  2159. mtsdram(SDRAM_RFDC,
  2160. (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
  2161. SDRAM_RFDC_RFFD_MASK))
  2162. | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) |
  2163. SDRAM_RFDC_RFFD_ENCODE(0)));
  2164. DQS_calibration_process();
  2165. #endif
  2166. }
  2167. static int short_mem_test(void)
  2168. {
  2169. u32 *membase;
  2170. u32 bxcr_num;
  2171. u32 bxcf;
  2172. int i;
  2173. int j;
  2174. phys_size_t base_addr;
  2175. u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
  2176. {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
  2177. 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
  2178. {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
  2179. 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
  2180. {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
  2181. 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
  2182. {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
  2183. 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
  2184. {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
  2185. 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
  2186. {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
  2187. 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
  2188. {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
  2189. 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
  2190. {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
  2191. 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
  2192. int l;
  2193. for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
  2194. mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
  2195. /* Banks enabled */
  2196. if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
  2197. /* Bank is enabled */
  2198. /*
  2199. * Only run test on accessable memory (below 2GB)
  2200. */
  2201. base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
  2202. if (base_addr >= CONFIG_MAX_MEM_MAPPED)
  2203. continue;
  2204. /*------------------------------------------------------------------
  2205. * Run the short memory test.
  2206. *-----------------------------------------------------------------*/
  2207. membase = (u32 *)(u32)base_addr;
  2208. for (i = 0; i < NUMMEMTESTS; i++) {
  2209. for (j = 0; j < NUMMEMWORDS; j++) {
  2210. membase[j] = test[i][j];
  2211. ppcDcbf((u32)&(membase[j]));
  2212. }
  2213. sync();
  2214. for (l=0; l<NUMLOOPS; l++) {
  2215. for (j = 0; j < NUMMEMWORDS; j++) {
  2216. if (membase[j] != test[i][j]) {
  2217. ppcDcbf((u32)&(membase[j]));
  2218. return 0;
  2219. }
  2220. ppcDcbf((u32)&(membase[j]));
  2221. }
  2222. sync();
  2223. }
  2224. }
  2225. } /* if bank enabled */
  2226. } /* for bxcf_num */
  2227. return 1;
  2228. }
  2229. #ifndef HARD_CODED_DQS
  2230. /*-----------------------------------------------------------------------------+
  2231. * DQS_calibration_process.
  2232. *-----------------------------------------------------------------------------*/
  2233. static void DQS_calibration_process(void)
  2234. {
  2235. unsigned long rfdc_reg;
  2236. unsigned long rffd;
  2237. unsigned long val;
  2238. long rffd_average;
  2239. long max_start;
  2240. unsigned long dlycal;
  2241. unsigned long dly_val;
  2242. unsigned long max_pass_length;
  2243. unsigned long current_pass_length;
  2244. unsigned long current_fail_length;
  2245. unsigned long current_start;
  2246. long max_end;
  2247. unsigned char fail_found;
  2248. unsigned char pass_found;
  2249. #if !defined(CONFIG_DDR_RQDC_FIXED)
  2250. int window_found;
  2251. u32 rqdc_reg;
  2252. u32 rqfd;
  2253. u32 rqfd_start;
  2254. u32 rqfd_average;
  2255. int loopi = 0;
  2256. char str[] = "Auto calibration -";
  2257. char slash[] = "\\|/-\\|/-";
  2258. /*------------------------------------------------------------------
  2259. * Test to determine the best read clock delay tuning bits.
  2260. *
  2261. * Before the DDR controller can be used, the read clock delay needs to be
  2262. * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
  2263. * This value cannot be hardcoded into the program because it changes
  2264. * depending on the board's setup and environment.
  2265. * To do this, all delay values are tested to see if they
  2266. * work or not. By doing this, you get groups of fails with groups of
  2267. * passing values. The idea is to find the start and end of a passing
  2268. * window and take the center of it to use as the read clock delay.
  2269. *
  2270. * A failure has to be seen first so that when we hit a pass, we know
  2271. * that it is truely the start of the window. If we get passing values
  2272. * to start off with, we don't know if we are at the start of the window.
  2273. *
  2274. * The code assumes that a failure will always be found.
  2275. * If a failure is not found, there is no easy way to get the middle
  2276. * of the passing window. I guess we can pretty much pick any value
  2277. * but some values will be better than others. Since the lowest speed
  2278. * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
  2279. * from experimentation it is safe to say you will always have a failure.
  2280. *-----------------------------------------------------------------*/
  2281. /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
  2282. rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
  2283. puts(str);
  2284. calibration_loop:
  2285. mfsdram(SDRAM_RQDC, rqdc_reg);
  2286. mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
  2287. SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
  2288. #else /* CONFIG_DDR_RQDC_FIXED */
  2289. /*
  2290. * On Katmai the complete auto-calibration somehow doesn't seem to
  2291. * produce the best results, meaning optimal values for RQFD/RFFD.
  2292. * This was discovered by GDA using a high bandwidth scope,
  2293. * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
  2294. * so now on Katmai "only" RFFD is auto-calibrated.
  2295. */
  2296. mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
  2297. #endif /* CONFIG_DDR_RQDC_FIXED */
  2298. max_start = 0;
  2299. max_pass_length = 0;
  2300. max_start = 0;
  2301. max_end = 0;
  2302. current_pass_length = 0;
  2303. current_fail_length = 0;
  2304. current_start = 0;
  2305. fail_found = false;
  2306. pass_found = false;
  2307. /*
  2308. * get the delay line calibration register value
  2309. */
  2310. mfsdram(SDRAM_DLCR, dlycal);
  2311. dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
  2312. for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
  2313. mfsdram(SDRAM_RFDC, rfdc_reg);
  2314. rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
  2315. /*------------------------------------------------------------------
  2316. * Set the timing reg for the test.
  2317. *-----------------------------------------------------------------*/
  2318. mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
  2319. /*------------------------------------------------------------------
  2320. * See if the rffd value passed.
  2321. *-----------------------------------------------------------------*/
  2322. if (short_mem_test()) {
  2323. if (fail_found == true) {
  2324. pass_found = true;
  2325. if (current_pass_length == 0)
  2326. current_start = rffd;
  2327. current_fail_length = 0;
  2328. current_pass_length++;
  2329. if (current_pass_length > max_pass_length) {
  2330. max_pass_length = current_pass_length;
  2331. max_start = current_start;
  2332. max_end = rffd;
  2333. }
  2334. }
  2335. } else {
  2336. current_pass_length = 0;
  2337. current_fail_length++;
  2338. if (current_fail_length >= (dly_val >> 2)) {
  2339. if (fail_found == false)
  2340. fail_found = true;
  2341. else if (pass_found == true)
  2342. break;
  2343. }
  2344. }
  2345. } /* for rffd */
  2346. /*------------------------------------------------------------------
  2347. * Set the average RFFD value
  2348. *-----------------------------------------------------------------*/
  2349. rffd_average = ((max_start + max_end) >> 1);
  2350. if (rffd_average < 0)
  2351. rffd_average = 0;
  2352. if (rffd_average > SDRAM_RFDC_RFFD_MAX)
  2353. rffd_average = SDRAM_RFDC_RFFD_MAX;
  2354. /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
  2355. mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
  2356. #if !defined(CONFIG_DDR_RQDC_FIXED)
  2357. max_pass_length = 0;
  2358. max_start = 0;
  2359. max_end = 0;
  2360. current_pass_length = 0;
  2361. current_fail_length = 0;
  2362. current_start = 0;
  2363. window_found = false;
  2364. fail_found = false;
  2365. pass_found = false;
  2366. for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
  2367. mfsdram(SDRAM_RQDC, rqdc_reg);
  2368. rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
  2369. /*------------------------------------------------------------------
  2370. * Set the timing reg for the test.
  2371. *-----------------------------------------------------------------*/
  2372. mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
  2373. /*------------------------------------------------------------------
  2374. * See if the rffd value passed.
  2375. *-----------------------------------------------------------------*/
  2376. if (short_mem_test()) {
  2377. if (fail_found == true) {
  2378. pass_found = true;
  2379. if (current_pass_length == 0)
  2380. current_start = rqfd;
  2381. current_fail_length = 0;
  2382. current_pass_length++;
  2383. if (current_pass_length > max_pass_length) {
  2384. max_pass_length = current_pass_length;
  2385. max_start = current_start;
  2386. max_end = rqfd;
  2387. }
  2388. }
  2389. } else {
  2390. current_pass_length = 0;
  2391. current_fail_length++;
  2392. if (fail_found == false) {
  2393. fail_found = true;
  2394. } else if (pass_found == true) {
  2395. window_found = true;
  2396. break;
  2397. }
  2398. }
  2399. }
  2400. rqfd_average = ((max_start + max_end) >> 1);
  2401. /*------------------------------------------------------------------
  2402. * Make sure we found the valid read passing window. Halt if not
  2403. *-----------------------------------------------------------------*/
  2404. if (window_found == false) {
  2405. if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
  2406. putc('\b');
  2407. putc(slash[loopi++ % 8]);
  2408. /* try again from with a different RQFD start value */
  2409. rqfd_start++;
  2410. goto calibration_loop;
  2411. }
  2412. printf("\nERROR: Cannot determine a common read delay for the "
  2413. "DIMM(s) installed.\n");
  2414. debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
  2415. ppc4xx_ibm_ddr2_register_dump();
  2416. spd_ddr_init_hang ();
  2417. }
  2418. if (rqfd_average < 0)
  2419. rqfd_average = 0;
  2420. if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
  2421. rqfd_average = SDRAM_RQDC_RQFD_MAX;
  2422. mtsdram(SDRAM_RQDC,
  2423. (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
  2424. SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
  2425. blank_string(strlen(str));
  2426. #endif /* CONFIG_DDR_RQDC_FIXED */
  2427. mfsdram(SDRAM_DLCR, val);
  2428. debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val);
  2429. mfsdram(SDRAM_RQDC, val);
  2430. debug("%s[%d] RQDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
  2431. mfsdram(SDRAM_RFDC, val);
  2432. debug("%s[%d] RFDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
  2433. mfsdram(SDRAM_RDCC, val);
  2434. debug("%s[%d] RDCC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
  2435. }
  2436. #else /* calibration test with hardvalues */
  2437. /*-----------------------------------------------------------------------------+
  2438. * DQS_calibration_process.
  2439. *-----------------------------------------------------------------------------*/
  2440. static void test(void)
  2441. {
  2442. unsigned long dimm_num;
  2443. unsigned long ecc_temp;
  2444. unsigned long i, j;
  2445. unsigned long *membase;
  2446. unsigned long bxcf[MAXRANKS];
  2447. unsigned long val;
  2448. char window_found;
  2449. char begin_found[MAXDIMMS];
  2450. char end_found[MAXDIMMS];
  2451. char search_end[MAXDIMMS];
  2452. unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
  2453. {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
  2454. 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
  2455. {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
  2456. 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
  2457. {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
  2458. 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
  2459. {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
  2460. 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
  2461. {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
  2462. 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
  2463. {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
  2464. 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
  2465. {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
  2466. 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
  2467. {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
  2468. 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
  2469. /*------------------------------------------------------------------
  2470. * Test to determine the best read clock delay tuning bits.
  2471. *
  2472. * Before the DDR controller can be used, the read clock delay needs to be
  2473. * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
  2474. * This value cannot be hardcoded into the program because it changes
  2475. * depending on the board's setup and environment.
  2476. * To do this, all delay values are tested to see if they
  2477. * work or not. By doing this, you get groups of fails with groups of
  2478. * passing values. The idea is to find the start and end of a passing
  2479. * window and take the center of it to use as the read clock delay.
  2480. *
  2481. * A failure has to be seen first so that when we hit a pass, we know
  2482. * that it is truely the start of the window. If we get passing values
  2483. * to start off with, we don't know if we are at the start of the window.
  2484. *
  2485. * The code assumes that a failure will always be found.
  2486. * If a failure is not found, there is no easy way to get the middle
  2487. * of the passing window. I guess we can pretty much pick any value
  2488. * but some values will be better than others. Since the lowest speed
  2489. * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
  2490. * from experimentation it is safe to say you will always have a failure.
  2491. *-----------------------------------------------------------------*/
  2492. mfsdram(SDRAM_MCOPT1, ecc_temp);
  2493. ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
  2494. mfsdram(SDRAM_MCOPT1, val);
  2495. mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
  2496. SDRAM_MCOPT1_MCHK_NON);
  2497. window_found = false;
  2498. begin_found[0] = false;
  2499. end_found[0] = false;
  2500. search_end[0] = false;
  2501. begin_found[1] = false;
  2502. end_found[1] = false;
  2503. search_end[1] = false;
  2504. for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
  2505. mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
  2506. /* Banks enabled */
  2507. if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
  2508. /* Bank is enabled */
  2509. membase =
  2510. (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
  2511. /*------------------------------------------------------------------
  2512. * Run the short memory test.
  2513. *-----------------------------------------------------------------*/
  2514. for (i = 0; i < NUMMEMTESTS; i++) {
  2515. for (j = 0; j < NUMMEMWORDS; j++) {
  2516. membase[j] = test[i][j];
  2517. ppcDcbf((u32)&(membase[j]));
  2518. }
  2519. sync();
  2520. for (j = 0; j < NUMMEMWORDS; j++) {
  2521. if (membase[j] != test[i][j]) {
  2522. ppcDcbf((u32)&(membase[j]));
  2523. break;
  2524. }
  2525. ppcDcbf((u32)&(membase[j]));
  2526. }
  2527. sync();
  2528. if (j < NUMMEMWORDS)
  2529. break;
  2530. }
  2531. /*------------------------------------------------------------------
  2532. * See if the rffd value passed.
  2533. *-----------------------------------------------------------------*/
  2534. if (i < NUMMEMTESTS) {
  2535. if ((end_found[dimm_num] == false) &&
  2536. (search_end[dimm_num] == true)) {
  2537. end_found[dimm_num] = true;
  2538. }
  2539. if ((end_found[0] == true) &&
  2540. (end_found[1] == true))
  2541. break;
  2542. } else {
  2543. if (begin_found[dimm_num] == false) {
  2544. begin_found[dimm_num] = true;
  2545. search_end[dimm_num] = true;
  2546. }
  2547. }
  2548. } else {
  2549. begin_found[dimm_num] = true;
  2550. end_found[dimm_num] = true;
  2551. }
  2552. }
  2553. if ((begin_found[0] == true) && (begin_found[1] == true))
  2554. window_found = true;
  2555. /*------------------------------------------------------------------
  2556. * Make sure we found the valid read passing window. Halt if not
  2557. *-----------------------------------------------------------------*/
  2558. if (window_found == false) {
  2559. printf("ERROR: Cannot determine a common read delay for the "
  2560. "DIMM(s) installed.\n");
  2561. spd_ddr_init_hang ();
  2562. }
  2563. /*------------------------------------------------------------------
  2564. * Restore the ECC variable to what it originally was
  2565. *-----------------------------------------------------------------*/
  2566. mtsdram(SDRAM_MCOPT1,
  2567. (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
  2568. | ecc_temp);
  2569. }
  2570. #endif /* !HARD_CODED_DQS */
  2571. #endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
  2572. #else /* CONFIG_SPD_EEPROM */
  2573. /*-----------------------------------------------------------------------------
  2574. * Function: initdram
  2575. * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
  2576. * The configuration is performed using static, compile-
  2577. * time parameters.
  2578. * Configures the PPC405EX(r) and PPC460EX/GT
  2579. *---------------------------------------------------------------------------*/
  2580. phys_size_t initdram(int board_type)
  2581. {
  2582. /*
  2583. * Only run this SDRAM init code once. For NAND booting
  2584. * targets like Kilauea, we call initdram() early from the
  2585. * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
  2586. * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
  2587. * which calls initdram() again. This time the controller
  2588. * mustn't be reconfigured again since we're already running
  2589. * from SDRAM.
  2590. */
  2591. #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  2592. unsigned long val;
  2593. #if defined(CONFIG_440)
  2594. mtdcr(SDRAM_R0BAS, CONFIG_SYS_SDRAM_R0BAS);
  2595. mtdcr(SDRAM_R1BAS, CONFIG_SYS_SDRAM_R1BAS);
  2596. mtdcr(SDRAM_R2BAS, CONFIG_SYS_SDRAM_R2BAS);
  2597. mtdcr(SDRAM_R3BAS, CONFIG_SYS_SDRAM_R3BAS);
  2598. mtdcr(SDRAM_PLBADDULL, CONFIG_SYS_SDRAM_PLBADDULL); /* MQ0_BAUL */
  2599. mtdcr(SDRAM_PLBADDUHB, CONFIG_SYS_SDRAM_PLBADDUHB); /* MQ0_BAUH */
  2600. mtdcr(SDRAM_CONF1LL, CONFIG_SYS_SDRAM_CONF1LL);
  2601. mtdcr(SDRAM_CONF1HB, CONFIG_SYS_SDRAM_CONF1HB);
  2602. mtdcr(SDRAM_CONFPATHB, CONFIG_SYS_SDRAM_CONFPATHB);
  2603. #endif
  2604. /* Set Memory Bank Configuration Registers */
  2605. mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
  2606. mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
  2607. mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
  2608. mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
  2609. /* Set Memory Clock Timing Register */
  2610. mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
  2611. /* Set Refresh Time Register */
  2612. mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
  2613. /* Set SDRAM Timing Registers */
  2614. mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
  2615. mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
  2616. mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
  2617. /* Set Mode and Extended Mode Registers */
  2618. mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
  2619. mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
  2620. /* Set Memory Controller Options 1 Register */
  2621. mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
  2622. /* Set Manual Initialization Control Registers */
  2623. mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
  2624. mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
  2625. mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
  2626. mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
  2627. mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
  2628. mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
  2629. mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
  2630. mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
  2631. mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
  2632. mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
  2633. mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
  2634. mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
  2635. mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
  2636. mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
  2637. mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
  2638. mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
  2639. /* Set On-Die Termination Registers */
  2640. mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
  2641. mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
  2642. mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
  2643. /* Set Write Timing Register */
  2644. mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
  2645. /*
  2646. * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
  2647. * SDRAM0_MCOPT2[IPTR] = 1
  2648. */
  2649. mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
  2650. SDRAM_MCOPT2_IPTR_EXECUTE));
  2651. /*
  2652. * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
  2653. * completion of initialization.
  2654. */
  2655. do {
  2656. mfsdram(SDRAM_MCSTAT, val);
  2657. } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
  2658. /* Set Delay Control Registers */
  2659. mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
  2660. #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
  2661. mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
  2662. mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
  2663. mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
  2664. #endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
  2665. /*
  2666. * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
  2667. */
  2668. mfsdram(SDRAM_MCOPT2, val);
  2669. mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
  2670. #if defined(CONFIG_440)
  2671. /*
  2672. * Program TLB entries with caches enabled, for best performace
  2673. * while auto-calibrating and ECC generation
  2674. */
  2675. program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
  2676. #endif
  2677. #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
  2678. #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  2679. /*------------------------------------------------------------------
  2680. | DQS calibration.
  2681. +-----------------------------------------------------------------*/
  2682. DQS_autocalibration();
  2683. #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
  2684. #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
  2685. /*
  2686. * Now complete RDSS configuration as mentioned on page 7 of the AMCC
  2687. * PowerPC440SP/SPe DDR2 application note:
  2688. * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
  2689. */
  2690. update_rdcc();
  2691. #if defined(CONFIG_DDR_ECC)
  2692. do_program_ecc(0);
  2693. #endif /* defined(CONFIG_DDR_ECC) */
  2694. #if defined(CONFIG_440)
  2695. /*
  2696. * Now after initialization (auto-calibration and ECC generation)
  2697. * remove the TLB entries with caches enabled and program again with
  2698. * desired cache functionality
  2699. */
  2700. remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
  2701. program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
  2702. #endif
  2703. ppc4xx_ibm_ddr2_register_dump();
  2704. #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
  2705. /*
  2706. * Clear potential errors resulting from auto-calibration.
  2707. * If not done, then we could get an interrupt later on when
  2708. * exceptions are enabled.
  2709. */
  2710. set_mcsr(get_mcsr());
  2711. #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
  2712. #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
  2713. return (CONFIG_SYS_MBYTES_SDRAM << 20);
  2714. }
  2715. #endif /* CONFIG_SPD_EEPROM */
  2716. #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  2717. #if defined(CONFIG_440)
  2718. u32 mfdcr_any(u32 dcr)
  2719. {
  2720. u32 val;
  2721. switch (dcr) {
  2722. case SDRAM_R0BAS + 0:
  2723. val = mfdcr(SDRAM_R0BAS + 0);
  2724. break;
  2725. case SDRAM_R0BAS + 1:
  2726. val = mfdcr(SDRAM_R0BAS + 1);
  2727. break;
  2728. case SDRAM_R0BAS + 2:
  2729. val = mfdcr(SDRAM_R0BAS + 2);
  2730. break;
  2731. case SDRAM_R0BAS + 3:
  2732. val = mfdcr(SDRAM_R0BAS + 3);
  2733. break;
  2734. default:
  2735. printf("DCR %d not defined in case statement!!!\n", dcr);
  2736. val = 0; /* just to satisfy the compiler */
  2737. }
  2738. return val;
  2739. }
  2740. void mtdcr_any(u32 dcr, u32 val)
  2741. {
  2742. switch (dcr) {
  2743. case SDRAM_R0BAS + 0:
  2744. mtdcr(SDRAM_R0BAS + 0, val);
  2745. break;
  2746. case SDRAM_R0BAS + 1:
  2747. mtdcr(SDRAM_R0BAS + 1, val);
  2748. break;
  2749. case SDRAM_R0BAS + 2:
  2750. mtdcr(SDRAM_R0BAS + 2, val);
  2751. break;
  2752. case SDRAM_R0BAS + 3:
  2753. mtdcr(SDRAM_R0BAS + 3, val);
  2754. break;
  2755. default:
  2756. printf("DCR %d not defined in case statement!!!\n", dcr);
  2757. }
  2758. }
  2759. #endif /* defined(CONFIG_440) */
  2760. #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
  2761. inline void ppc4xx_ibm_ddr2_register_dump(void)
  2762. {
  2763. #if defined(DEBUG)
  2764. printf("\nPPC4xx IBM DDR2 Register Dump:\n");
  2765. #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  2766. defined(CONFIG_460EX) || defined(CONFIG_460GT))
  2767. PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R0BAS);
  2768. PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R1BAS);
  2769. PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R2BAS);
  2770. PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R3BAS);
  2771. #endif /* (defined(CONFIG_440SP) || ... */
  2772. #if defined(CONFIG_405EX)
  2773. PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
  2774. PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
  2775. PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
  2776. PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
  2777. PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
  2778. PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
  2779. #endif /* defined(CONFIG_405EX) */
  2780. PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
  2781. PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
  2782. PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
  2783. PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
  2784. PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
  2785. PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
  2786. PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
  2787. PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
  2788. PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
  2789. PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
  2790. PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
  2791. PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
  2792. #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  2793. defined(CONFIG_460EX) || defined(CONFIG_460GT))
  2794. PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
  2795. PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
  2796. /*
  2797. * OPART is only used as a trigger register.
  2798. *
  2799. * No data is contained in this register, and reading or writing
  2800. * to is can cause bad things to happen (hangs). Just skip it and
  2801. * report "N/A".
  2802. */
  2803. printf("%20s = N/A\n", "SDRAM_OPART");
  2804. #endif /* defined(CONFIG_440SP) || ... */
  2805. PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
  2806. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
  2807. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
  2808. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
  2809. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
  2810. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
  2811. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
  2812. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
  2813. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
  2814. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
  2815. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
  2816. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
  2817. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
  2818. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
  2819. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
  2820. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
  2821. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
  2822. PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
  2823. PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
  2824. PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
  2825. PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
  2826. PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
  2827. PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
  2828. PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
  2829. PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
  2830. PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
  2831. PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
  2832. PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
  2833. PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCES);
  2834. #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  2835. defined(CONFIG_460EX) || defined(CONFIG_460GT))
  2836. PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
  2837. #endif /* defined(CONFIG_440SP) || ... */
  2838. PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
  2839. PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
  2840. PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
  2841. #endif /* defined(DEBUG) */
  2842. }