spear600.c 5.2 KB

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  1. /*
  2. * (C) Copyright 2000-2009
  3. * Viresh Kumar, ST Microelectronics, viresh.kumar@st.com
  4. * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. #include <common.h>
  25. #include <asm/hardware.h>
  26. #include <asm/io.h>
  27. #include <asm/arch/spr_misc.h>
  28. #include <asm/arch/spr_defs.h>
  29. static void sel_1v8(void)
  30. {
  31. struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  32. u32 ddr1v8, ddr2v5;
  33. ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
  34. ddr2v5 &= 0x8080ffc0;
  35. ddr2v5 |= 0x78000003;
  36. writel(ddr2v5, &misc_p->ddr_2v5_compensation);
  37. ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
  38. ddr1v8 &= 0x8080ffc0;
  39. ddr1v8 |= 0x78000010;
  40. writel(ddr1v8, &misc_p->ddr_1v8_compensation);
  41. while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))
  42. ;
  43. }
  44. static void sel_2v5(void)
  45. {
  46. struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  47. u32 ddr1v8, ddr2v5;
  48. ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
  49. ddr1v8 &= 0x8080ffc0;
  50. ddr1v8 |= 0x78000003;
  51. writel(ddr1v8, &misc_p->ddr_1v8_compensation);
  52. ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
  53. ddr2v5 &= 0x8080ffc0;
  54. ddr2v5 |= 0x78000010;
  55. writel(ddr2v5, &misc_p->ddr_2v5_compensation);
  56. while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))
  57. ;
  58. }
  59. /*
  60. * plat_ddr_init:
  61. */
  62. void plat_ddr_init(void)
  63. {
  64. struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  65. u32 ddrpad;
  66. u32 core3v3, ddr1v8, ddr2v5;
  67. /* DDR pad register configurations */
  68. ddrpad = readl(&misc_p->ddr_pad);
  69. ddrpad &= ~DDR_PAD_CNF_MSK;
  70. #if (CONFIG_DDR_HCLK)
  71. ddrpad |= 0xEAAB;
  72. #elif (CONFIG_DDR_2HCLK)
  73. ddrpad |= 0xEAAD;
  74. #elif (CONFIG_DDR_PLL2)
  75. ddrpad |= 0xEAAD;
  76. #endif
  77. writel(ddrpad, &misc_p->ddr_pad);
  78. /* Compensation register configurations */
  79. core3v3 = readl(&misc_p->core_3v3_compensation);
  80. core3v3 &= 0x8080ffe0;
  81. core3v3 |= 0x78000002;
  82. writel(core3v3, &misc_p->core_3v3_compensation);
  83. ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
  84. ddr1v8 &= 0x8080ffc0;
  85. ddr1v8 |= 0x78000004;
  86. writel(ddr1v8, &misc_p->ddr_1v8_compensation);
  87. ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
  88. ddr2v5 &= 0x8080ffc0;
  89. ddr2v5 |= 0x78000004;
  90. writel(ddr2v5, &misc_p->ddr_2v5_compensation);
  91. if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {
  92. /* Software memory configuration */
  93. if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)
  94. sel_1v8();
  95. else
  96. sel_2v5();
  97. } else {
  98. /* Hardware memory configuration */
  99. if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)
  100. sel_1v8();
  101. else
  102. sel_2v5();
  103. }
  104. }
  105. /*
  106. * soc_init:
  107. */
  108. void soc_init(void)
  109. {
  110. /* Nothing to be done for SPEAr600 */
  111. }
  112. /*
  113. * xxx_boot_selected:
  114. *
  115. * return true if the particular booting option is selected
  116. * return false otherwise
  117. */
  118. static u32 read_bootstrap(void)
  119. {
  120. return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT)
  121. & CONFIG_SPEAR_BOOTSTRAPMASK;
  122. }
  123. int snor_boot_selected(void)
  124. {
  125. u32 bootstrap = read_bootstrap();
  126. if (SNOR_BOOT_SUPPORTED) {
  127. /* Check whether SNOR boot is selected */
  128. if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
  129. CONFIG_SPEAR_ONLYSNORBOOT)
  130. return true;
  131. if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
  132. CONFIG_SPEAR_NORNAND8BOOT)
  133. return true;
  134. if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
  135. CONFIG_SPEAR_NORNAND16BOOT)
  136. return true;
  137. }
  138. return false;
  139. }
  140. int nand_boot_selected(void)
  141. {
  142. u32 bootstrap = read_bootstrap();
  143. if (NAND_BOOT_SUPPORTED) {
  144. /* Check whether NAND boot is selected */
  145. if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
  146. CONFIG_SPEAR_NORNAND8BOOT)
  147. return true;
  148. if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
  149. CONFIG_SPEAR_NORNAND16BOOT)
  150. return true;
  151. }
  152. return false;
  153. }
  154. int pnor_boot_selected(void)
  155. {
  156. /* Parallel NOR boot is not selected in any SPEAr600 revision */
  157. return false;
  158. }
  159. int usb_boot_selected(void)
  160. {
  161. u32 bootstrap = read_bootstrap();
  162. if (USB_BOOT_SUPPORTED) {
  163. /* Check whether USB boot is selected */
  164. if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
  165. return true;
  166. }
  167. return false;
  168. }
  169. int tftp_boot_selected(void)
  170. {
  171. /* TFTP boot is not selected in any SPEAr600 revision */
  172. return false;
  173. }
  174. int uart_boot_selected(void)
  175. {
  176. /* UART boot is not selected in any SPEAr600 revision */
  177. return false;
  178. }
  179. int spi_boot_selected(void)
  180. {
  181. /* SPI boot is not selected in any SPEAr600 revision */
  182. return false;
  183. }
  184. int i2c_boot_selected(void)
  185. {
  186. /* I2C boot is not selected in any SPEAr600 revision */
  187. return false;
  188. }
  189. int mmc_boot_selected(void)
  190. {
  191. return false;
  192. }
  193. void plat_late_init(void)
  194. {
  195. spear_late_init();
  196. }