miiphy.c 2.7 KB

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  1. /*
  2. * SPDX-License-Identifier: GPL-2.0 ibm-pibs
  3. */
  4. /*-----------------------------------------------------------------------------+
  5. |
  6. | File Name: miiphy.c
  7. |
  8. | Function: This module has utilities for accessing the MII PHY through
  9. | the EMAC3 macro.
  10. |
  11. | Author: Mark Wisner
  12. |
  13. | Change Activity-
  14. |
  15. | Date Description of Change BY
  16. | --------- --------------------- ---
  17. | 05-May-99 Created MKW
  18. | 01-Jul-99 Changed clock setting of sta_reg from 66MHz to 50MHz to
  19. | better match OPB speed. Also modified delay times. JWB
  20. | 29-Jul-99 Added Full duplex support MKW
  21. | 24-Aug-99 Removed printf from dp83843_duplex() JWB
  22. | 19-Jul-00 Ported to esd cpci405 sr
  23. | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS
  24. | <travis.sawyer@sandburst.com>
  25. |
  26. +-----------------------------------------------------------------------------*/
  27. #include <common.h>
  28. #include <miiphy.h>
  29. #include "IxOsal.h"
  30. #include "IxEthAcc.h"
  31. #include "IxEthAcc_p.h"
  32. #include "IxEthAccMac_p.h"
  33. #include "IxEthAccMii_p.h"
  34. /***********************************************************/
  35. /* Dump out to the screen PHY regs */
  36. /***********************************************************/
  37. void miiphy_dump (char *devname, unsigned char addr)
  38. {
  39. unsigned long i;
  40. unsigned short data;
  41. for (i = 0; i < 0x1A; i++) {
  42. if (miiphy_read (devname, addr, i, &data)) {
  43. printf ("read error for reg %lx\n", i);
  44. return;
  45. }
  46. printf ("Phy reg %lx ==> %4x\n", i, data);
  47. /* jump to the next set of regs */
  48. if (i == 0x07)
  49. i = 0x0f;
  50. } /* end for loop */
  51. } /* end dump */
  52. /***********************************************************/
  53. /* (Re)start autonegotiation */
  54. /***********************************************************/
  55. int phy_setup_aneg (char *devname, unsigned char addr)
  56. {
  57. unsigned short ctl, adv;
  58. /* Setup standard advertise */
  59. miiphy_read (devname, addr, MII_ADVERTISE, &adv);
  60. adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 |
  61. LPA_100FULL | LPA_100HALF | LPA_10FULL |
  62. LPA_10HALF);
  63. miiphy_write (devname, addr, MII_ADVERTISE, adv);
  64. /* Start/Restart aneg */
  65. miiphy_read (devname, addr, MII_BMCR, &ctl);
  66. ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
  67. miiphy_write (devname, addr, MII_BMCR, ctl);
  68. return 0;
  69. }
  70. int npe_miiphy_read (const char *devname, unsigned char addr,
  71. unsigned char reg, unsigned short *value)
  72. {
  73. u16 val;
  74. ixEthAccMiiReadRtn(addr, reg, &val);
  75. *value = val;
  76. return 0;
  77. } /* phy_read */
  78. int npe_miiphy_write (const char *devname, unsigned char addr,
  79. unsigned char reg, unsigned short value)
  80. {
  81. ixEthAccMiiWriteRtn(addr, reg, value);
  82. return 0;
  83. } /* phy_write */