4xx_enet.c 61 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059
  1. /*
  2. * SPDX-License-Identifier: GPL-2.0 ibm-pibs
  3. */
  4. /*-----------------------------------------------------------------------------+
  5. *
  6. * File Name: enetemac.c
  7. *
  8. * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
  9. *
  10. * Author: Mark Wisner
  11. *
  12. * Change Activity-
  13. *
  14. * Date Description of Change BY
  15. * --------- --------------------- ---
  16. * 05-May-99 Created MKW
  17. * 27-Jun-99 Clean up JWB
  18. * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
  19. * 29-Jul-99 Added Full duplex support MKW
  20. * 06-Aug-99 Changed names for Mal CR reg MKW
  21. * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
  22. * 24-Aug-99 Marked descriptor empty after call_xlc MKW
  23. * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
  24. * to avoid chaining maximum sized packets. Push starting
  25. * RX descriptor address up to the next cache line boundary.
  26. * 16-Jan-00 Added support for booting with IP of 0x0 MKW
  27. * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
  28. * EMAC0_RXM register. JWB
  29. * 12-Mar-01 anne-sophie.harnois@nextream.fr
  30. * - Variables are compatible with those already defined in
  31. * include/net.h
  32. * - Receive buffer descriptor ring is used to send buffers
  33. * to the user
  34. * - Info print about send/received/handled packet number if
  35. * INFO_405_ENET is set
  36. * 17-Apr-01 stefan.roese@esd-electronics.com
  37. * - MAL reset in "eth_halt" included
  38. * - Enet speed and duplex output now in one line
  39. * 08-May-01 stefan.roese@esd-electronics.com
  40. * - MAL error handling added (eth_init called again)
  41. * 13-Nov-01 stefan.roese@esd-electronics.com
  42. * - Set IST bit in EMAC0_MR1 reg upon 100MBit or full duplex
  43. * 04-Jan-02 stefan.roese@esd-electronics.com
  44. * - Wait for PHY auto negotiation to complete added
  45. * 06-Feb-02 stefan.roese@esd-electronics.com
  46. * - Bug fixed in waiting for auto negotiation to complete
  47. * 26-Feb-02 stefan.roese@esd-electronics.com
  48. * - rx and tx buffer descriptors now allocated (no fixed address
  49. * used anymore)
  50. * 17-Jun-02 stefan.roese@esd-electronics.com
  51. * - MAL error debug printf 'M' removed (rx de interrupt may
  52. * occur upon many incoming packets with only 4 rx buffers).
  53. *-----------------------------------------------------------------------------*
  54. * 17-Nov-03 travis.sawyer@sandburst.com
  55. * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
  56. * in the 440GX. This port should work with the 440GP
  57. * (2 EMACs) also
  58. * 15-Aug-05 sr@denx.de
  59. * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
  60. now handling all 4xx cpu's.
  61. *-----------------------------------------------------------------------------*/
  62. #include <config.h>
  63. #include <common.h>
  64. #include <net.h>
  65. #include <asm/processor.h>
  66. #include <asm/io.h>
  67. #include <asm/cache.h>
  68. #include <asm/mmu.h>
  69. #include <commproc.h>
  70. #include <asm/ppc4xx.h>
  71. #include <asm/ppc4xx-emac.h>
  72. #include <asm/ppc4xx-mal.h>
  73. #include <miiphy.h>
  74. #include <malloc.h>
  75. #include <linux/compiler.h>
  76. #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
  77. #error "CONFIG_MII has to be defined!"
  78. #endif
  79. #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
  80. #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */
  81. /* Ethernet Transmit and Receive Buffers */
  82. /* AS.HARNOIS
  83. * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
  84. * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
  85. */
  86. #define ENET_MAX_MTU PKTSIZE
  87. #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
  88. /*-----------------------------------------------------------------------------+
  89. * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
  90. * Interrupt Controller).
  91. *-----------------------------------------------------------------------------*/
  92. #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS))
  93. #if defined(CONFIG_HAS_ETH3)
  94. #if !defined(CONFIG_440GX)
  95. #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
  96. UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
  97. #else
  98. /* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */
  99. #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
  100. #define UIC_ETHxB (UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
  101. #endif /* !defined(CONFIG_440GX) */
  102. #elif defined(CONFIG_HAS_ETH2)
  103. #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
  104. UIC_MASK(ETH_IRQ_NUM(2)))
  105. #elif defined(CONFIG_HAS_ETH1)
  106. #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
  107. #else
  108. #define UIC_ETHx UIC_MASK(ETH_IRQ_NUM(0))
  109. #endif
  110. /*
  111. * Define a default version for UIC_ETHxB for non 440GX so that we can
  112. * use common code for all 4xx variants
  113. */
  114. #if !defined(UIC_ETHxB)
  115. #define UIC_ETHxB 0
  116. #endif
  117. #define UIC_MAL_SERR UIC_MASK(VECNUM_MAL_SERR)
  118. #define UIC_MAL_TXDE UIC_MASK(VECNUM_MAL_TXDE)
  119. #define UIC_MAL_RXDE UIC_MASK(VECNUM_MAL_RXDE)
  120. #define UIC_MAL_TXEOB UIC_MASK(VECNUM_MAL_TXEOB)
  121. #define UIC_MAL_RXEOB UIC_MASK(VECNUM_MAL_RXEOB)
  122. #define MAL_UIC_ERR (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
  123. #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
  124. /*
  125. * We have 3 different interrupt types:
  126. * - MAL interrupts indicating successful transfer
  127. * - MAL error interrupts indicating MAL related errors
  128. * - EMAC interrupts indicating EMAC related errors
  129. *
  130. * All those interrupts can be on different UIC's, but since
  131. * now at least all interrupts from one type are on the same
  132. * UIC. Only exception is 440GX where the EMAC interrupts are
  133. * spread over two UIC's!
  134. */
  135. #if defined(CONFIG_440GX)
  136. #define UIC_BASE_MAL UIC1_DCR_BASE
  137. #define UIC_BASE_MAL_ERR UIC2_DCR_BASE
  138. #define UIC_BASE_EMAC UIC2_DCR_BASE
  139. #define UIC_BASE_EMAC_B UIC3_DCR_BASE
  140. #else
  141. #define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10))
  142. #define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10))
  143. #define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
  144. #define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
  145. #endif
  146. #undef INFO_4XX_ENET
  147. #define BI_PHYMODE_NONE 0
  148. #define BI_PHYMODE_ZMII 1
  149. #define BI_PHYMODE_RGMII 2
  150. #define BI_PHYMODE_GMII 3
  151. #define BI_PHYMODE_RTBI 4
  152. #define BI_PHYMODE_TBI 5
  153. #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  154. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  155. defined(CONFIG_405EX)
  156. #define BI_PHYMODE_SMII 6
  157. #define BI_PHYMODE_MII 7
  158. #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  159. #define BI_PHYMODE_RMII 8
  160. #endif
  161. #endif
  162. #define BI_PHYMODE_SGMII 9
  163. #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  164. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  165. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  166. defined(CONFIG_405EX)
  167. #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
  168. #endif
  169. #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  170. #define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n))
  171. #endif
  172. #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  173. #define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */
  174. #else
  175. #define MAL_RX_CHAN_MUL 1
  176. #endif
  177. /*--------------------------------------------------------------------+
  178. * Fixed PHY (PHY-less) support for Ethernet Ports.
  179. *--------------------------------------------------------------------*/
  180. /*
  181. * Some boards do not have a PHY for each ethernet port. These ports
  182. * are known as Fixed PHY (or PHY-less) ports. For such ports, set
  183. * the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and
  184. * then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and
  185. * duplex should be for these ports in the board configuration
  186. * file.
  187. *
  188. * For Example:
  189. * #define CONFIG_FIXED_PHY 0xFFFFFFFF
  190. *
  191. * #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
  192. * #define CONFIG_PHY1_ADDR 1
  193. * #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY
  194. * #define CONFIG_PHY3_ADDR 3
  195. *
  196. * #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \
  197. * {devnum, speed, duplex},
  198. *
  199. * #define CONFIG_SYS_FIXED_PHY_PORTS \
  200. * CONFIG_SYS_FIXED_PHY_PORT(0,1000,FULL) \
  201. * CONFIG_SYS_FIXED_PHY_PORT(2,100,HALF)
  202. */
  203. #ifndef CONFIG_FIXED_PHY
  204. #define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
  205. #endif
  206. #ifndef CONFIG_SYS_FIXED_PHY_PORTS
  207. #define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */
  208. #endif
  209. struct fixed_phy_port {
  210. unsigned int devnum; /* ethernet port */
  211. unsigned int speed; /* specified speed 10,100 or 1000 */
  212. unsigned int duplex; /* specified duplex FULL or HALF */
  213. };
  214. static const struct fixed_phy_port fixed_phy_port[] = {
  215. CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
  216. };
  217. /*-----------------------------------------------------------------------------+
  218. * Global variables. TX and RX descriptors and buffers.
  219. *-----------------------------------------------------------------------------*/
  220. /*
  221. * Get count of EMAC devices (doesn't have to be the max. possible number
  222. * supported by the cpu)
  223. *
  224. * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
  225. * EMAC count is possible. As it is needed for the Kilauea/Haleakala
  226. * 405EX/405EXr eval board, using the same binary.
  227. */
  228. #if defined(CONFIG_BOARD_EMAC_COUNT)
  229. #define LAST_EMAC_NUM board_emac_count()
  230. #else /* CONFIG_BOARD_EMAC_COUNT */
  231. #if defined(CONFIG_HAS_ETH3)
  232. #define LAST_EMAC_NUM 4
  233. #elif defined(CONFIG_HAS_ETH2)
  234. #define LAST_EMAC_NUM 3
  235. #elif defined(CONFIG_HAS_ETH1)
  236. #define LAST_EMAC_NUM 2
  237. #else
  238. #define LAST_EMAC_NUM 1
  239. #endif
  240. #endif /* CONFIG_BOARD_EMAC_COUNT */
  241. /* normal boards start with EMAC0 */
  242. #if !defined(CONFIG_EMAC_NR_START)
  243. #define CONFIG_EMAC_NR_START 0
  244. #endif
  245. #define MAL_RX_DESC_SIZE 2048
  246. #define MAL_TX_DESC_SIZE 2048
  247. #define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
  248. /*-----------------------------------------------------------------------------+
  249. * Prototypes and externals.
  250. *-----------------------------------------------------------------------------*/
  251. static void enet_rcv (struct eth_device *dev, unsigned long malisr);
  252. int enetInt (struct eth_device *dev);
  253. static void mal_err (struct eth_device *dev, unsigned long isr,
  254. unsigned long uic, unsigned long maldef,
  255. unsigned long mal_errr);
  256. static void emac_err (struct eth_device *dev, unsigned long isr);
  257. extern int phy_setup_aneg (char *devname, unsigned char addr);
  258. extern int emac4xx_miiphy_read (const char *devname, unsigned char addr,
  259. unsigned char reg, unsigned short *value);
  260. extern int emac4xx_miiphy_write (const char *devname, unsigned char addr,
  261. unsigned char reg, unsigned short value);
  262. int board_emac_count(void);
  263. static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p)
  264. {
  265. #if defined(CONFIG_440SPE) || \
  266. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  267. defined(CONFIG_405EX)
  268. u32 val;
  269. mfsdr(SDR0_MFR, val);
  270. val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
  271. mtsdr(SDR0_MFR, val);
  272. #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
  273. u32 val;
  274. mfsdr(SDR0_ETH_CFG, val);
  275. val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
  276. mtsdr(SDR0_ETH_CFG, val);
  277. #endif
  278. }
  279. static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p)
  280. {
  281. #if defined(CONFIG_440SPE) || \
  282. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  283. defined(CONFIG_405EX)
  284. u32 val;
  285. mfsdr(SDR0_MFR, val);
  286. val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
  287. mtsdr(SDR0_MFR, val);
  288. #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
  289. u32 val;
  290. mfsdr(SDR0_ETH_CFG, val);
  291. val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
  292. mtsdr(SDR0_ETH_CFG, val);
  293. #endif
  294. }
  295. /*-----------------------------------------------------------------------------+
  296. | ppc_4xx_eth_halt
  297. | Disable MAL channel, and EMACn
  298. +-----------------------------------------------------------------------------*/
  299. static void ppc_4xx_eth_halt (struct eth_device *dev)
  300. {
  301. EMAC_4XX_HW_PST hw_p = dev->priv;
  302. u32 val = 10000;
  303. out_be32((void *)EMAC0_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
  304. /* 1st reset MAL channel */
  305. /* Note: writing a 0 to a channel has no effect */
  306. #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
  307. mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
  308. #else
  309. mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> hw_p->devnum));
  310. #endif
  311. mtdcr (MAL0_RXCARR, (MAL_CR_MMSR >> hw_p->devnum));
  312. /* wait for reset */
  313. while (mfdcr (MAL0_RXCASR) & (MAL_CR_MMSR >> hw_p->devnum)) {
  314. udelay (1000); /* Delay 1 MS so as not to hammer the register */
  315. val--;
  316. if (val == 0)
  317. break;
  318. }
  319. /* provide clocks for EMAC internal loopback */
  320. emac_loopback_enable(hw_p);
  321. /* EMAC RESET */
  322. out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST);
  323. /* remove clocks for EMAC internal loopback */
  324. emac_loopback_disable(hw_p);
  325. #ifndef CONFIG_NETCONSOLE
  326. hw_p->print_speed = 1; /* print speed message again next time */
  327. #endif
  328. #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  329. /* don't bypass the TAHOE0/TAHOE1 cores for Linux */
  330. mfsdr(SDR0_ETH_CFG, val);
  331. val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
  332. mtsdr(SDR0_ETH_CFG, val);
  333. #endif
  334. return;
  335. }
  336. #if defined (CONFIG_440GX)
  337. int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
  338. {
  339. unsigned long pfc1;
  340. unsigned long zmiifer;
  341. unsigned long rmiifer;
  342. mfsdr(SDR0_PFC1, pfc1);
  343. pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
  344. zmiifer = 0;
  345. rmiifer = 0;
  346. switch (pfc1) {
  347. case 1:
  348. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
  349. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
  350. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
  351. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
  352. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  353. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  354. bis->bi_phymode[2] = BI_PHYMODE_ZMII;
  355. bis->bi_phymode[3] = BI_PHYMODE_ZMII;
  356. break;
  357. case 2:
  358. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
  359. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
  360. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
  361. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
  362. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  363. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  364. bis->bi_phymode[2] = BI_PHYMODE_ZMII;
  365. bis->bi_phymode[3] = BI_PHYMODE_ZMII;
  366. break;
  367. case 3:
  368. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
  369. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
  370. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  371. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  372. bis->bi_phymode[2] = BI_PHYMODE_RGMII;
  373. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  374. break;
  375. case 4:
  376. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
  377. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
  378. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
  379. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
  380. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  381. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  382. bis->bi_phymode[2] = BI_PHYMODE_RGMII;
  383. bis->bi_phymode[3] = BI_PHYMODE_RGMII;
  384. break;
  385. case 5:
  386. zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
  387. zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
  388. zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
  389. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
  390. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  391. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  392. bis->bi_phymode[2] = BI_PHYMODE_ZMII;
  393. bis->bi_phymode[3] = BI_PHYMODE_RGMII;
  394. break;
  395. case 6:
  396. zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
  397. zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
  398. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
  399. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  400. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  401. bis->bi_phymode[2] = BI_PHYMODE_RGMII;
  402. break;
  403. case 0:
  404. default:
  405. zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
  406. rmiifer = 0x0;
  407. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  408. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  409. bis->bi_phymode[2] = BI_PHYMODE_ZMII;
  410. bis->bi_phymode[3] = BI_PHYMODE_ZMII;
  411. break;
  412. }
  413. /* Ensure we setup mdio for this devnum and ONLY this devnum */
  414. zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
  415. out_be32((void *)ZMII0_FER, zmiifer);
  416. out_be32((void *)RGMII_FER, rmiifer);
  417. return ((int)pfc1);
  418. }
  419. #endif /* CONFIG_440_GX */
  420. #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  421. int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
  422. {
  423. unsigned long zmiifer=0x0;
  424. unsigned long pfc1;
  425. mfsdr(SDR0_PFC1, pfc1);
  426. pfc1 &= SDR0_PFC1_SELECT_MASK;
  427. switch (pfc1) {
  428. case SDR0_PFC1_SELECT_CONFIG_2:
  429. /* 1 x GMII port */
  430. out_be32((void *)ZMII0_FER, 0x00);
  431. out_be32((void *)RGMII_FER, 0x00000037);
  432. bis->bi_phymode[0] = BI_PHYMODE_GMII;
  433. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  434. break;
  435. case SDR0_PFC1_SELECT_CONFIG_4:
  436. /* 2 x RGMII ports */
  437. out_be32((void *)ZMII0_FER, 0x00);
  438. out_be32((void *)RGMII_FER, 0x00000055);
  439. bis->bi_phymode[0] = BI_PHYMODE_RGMII;
  440. bis->bi_phymode[1] = BI_PHYMODE_RGMII;
  441. break;
  442. case SDR0_PFC1_SELECT_CONFIG_6:
  443. /* 2 x SMII ports */
  444. out_be32((void *)ZMII0_FER,
  445. ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
  446. ((ZMII_FER_SMII) << ZMII_FER_V(1)));
  447. out_be32((void *)RGMII_FER, 0x00000000);
  448. bis->bi_phymode[0] = BI_PHYMODE_SMII;
  449. bis->bi_phymode[1] = BI_PHYMODE_SMII;
  450. break;
  451. case SDR0_PFC1_SELECT_CONFIG_1_2:
  452. /* only 1 x MII supported */
  453. out_be32((void *)ZMII0_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
  454. out_be32((void *)RGMII_FER, 0x00000000);
  455. bis->bi_phymode[0] = BI_PHYMODE_MII;
  456. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  457. break;
  458. default:
  459. break;
  460. }
  461. /* Ensure we setup mdio for this devnum and ONLY this devnum */
  462. zmiifer = in_be32((void *)ZMII0_FER);
  463. zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
  464. out_be32((void *)ZMII0_FER, zmiifer);
  465. return ((int)0x0);
  466. }
  467. #endif /* CONFIG_440EPX */
  468. #if defined(CONFIG_405EX)
  469. int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
  470. {
  471. u32 rgmiifer = 0;
  472. /*
  473. * The 405EX(r)'s RGMII bridge can operate in one of several
  474. * modes, only one of which (2 x RGMII) allows the
  475. * simultaneous use of both EMACs on the 405EX.
  476. */
  477. switch (CONFIG_EMAC_PHY_MODE) {
  478. case EMAC_PHY_MODE_NONE:
  479. /* No ports */
  480. rgmiifer |= RGMII_FER_DIS << 0;
  481. rgmiifer |= RGMII_FER_DIS << 4;
  482. out_be32((void *)RGMII_FER, rgmiifer);
  483. bis->bi_phymode[0] = BI_PHYMODE_NONE;
  484. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  485. break;
  486. case EMAC_PHY_MODE_NONE_RGMII:
  487. /* 1 x RGMII port on channel 0 */
  488. rgmiifer |= RGMII_FER_RGMII << 0;
  489. rgmiifer |= RGMII_FER_DIS << 4;
  490. out_be32((void *)RGMII_FER, rgmiifer);
  491. bis->bi_phymode[0] = BI_PHYMODE_RGMII;
  492. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  493. break;
  494. case EMAC_PHY_MODE_RGMII_NONE:
  495. /* 1 x RGMII port on channel 1 */
  496. rgmiifer |= RGMII_FER_DIS << 0;
  497. rgmiifer |= RGMII_FER_RGMII << 4;
  498. out_be32((void *)RGMII_FER, rgmiifer);
  499. bis->bi_phymode[0] = BI_PHYMODE_NONE;
  500. bis->bi_phymode[1] = BI_PHYMODE_RGMII;
  501. break;
  502. case EMAC_PHY_MODE_RGMII_RGMII:
  503. /* 2 x RGMII ports */
  504. rgmiifer |= RGMII_FER_RGMII << 0;
  505. rgmiifer |= RGMII_FER_RGMII << 4;
  506. out_be32((void *)RGMII_FER, rgmiifer);
  507. bis->bi_phymode[0] = BI_PHYMODE_RGMII;
  508. bis->bi_phymode[1] = BI_PHYMODE_RGMII;
  509. break;
  510. case EMAC_PHY_MODE_NONE_GMII:
  511. /* 1 x GMII port on channel 0 */
  512. rgmiifer |= RGMII_FER_GMII << 0;
  513. rgmiifer |= RGMII_FER_DIS << 4;
  514. out_be32((void *)RGMII_FER, rgmiifer);
  515. bis->bi_phymode[0] = BI_PHYMODE_GMII;
  516. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  517. break;
  518. case EMAC_PHY_MODE_NONE_MII:
  519. /* 1 x MII port on channel 0 */
  520. rgmiifer |= RGMII_FER_MII << 0;
  521. rgmiifer |= RGMII_FER_DIS << 4;
  522. out_be32((void *)RGMII_FER, rgmiifer);
  523. bis->bi_phymode[0] = BI_PHYMODE_MII;
  524. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  525. break;
  526. case EMAC_PHY_MODE_GMII_NONE:
  527. /* 1 x GMII port on channel 1 */
  528. rgmiifer |= RGMII_FER_DIS << 0;
  529. rgmiifer |= RGMII_FER_GMII << 4;
  530. out_be32((void *)RGMII_FER, rgmiifer);
  531. bis->bi_phymode[0] = BI_PHYMODE_NONE;
  532. bis->bi_phymode[1] = BI_PHYMODE_GMII;
  533. break;
  534. case EMAC_PHY_MODE_MII_NONE:
  535. /* 1 x MII port on channel 1 */
  536. rgmiifer |= RGMII_FER_DIS << 0;
  537. rgmiifer |= RGMII_FER_MII << 4;
  538. out_be32((void *)RGMII_FER, rgmiifer);
  539. bis->bi_phymode[0] = BI_PHYMODE_NONE;
  540. bis->bi_phymode[1] = BI_PHYMODE_MII;
  541. break;
  542. default:
  543. break;
  544. }
  545. /* Ensure we setup mdio for this devnum and ONLY this devnum */
  546. rgmiifer = in_be32((void *)RGMII_FER);
  547. rgmiifer |= (1 << (19-devnum));
  548. out_be32((void *)RGMII_FER, rgmiifer);
  549. return ((int)0x0);
  550. }
  551. #endif /* CONFIG_405EX */
  552. #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  553. int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
  554. {
  555. u32 eth_cfg;
  556. u32 zmiifer; /* ZMII0_FER reg. */
  557. u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */
  558. u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */
  559. int mode;
  560. zmiifer = 0;
  561. rmiifer = 0;
  562. rmiifer1 = 0;
  563. #if defined(CONFIG_460EX)
  564. mode = 9;
  565. mfsdr(SDR0_ETH_CFG, eth_cfg);
  566. if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
  567. ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0))
  568. mode = 11; /* config SGMII */
  569. #else
  570. mode = 10;
  571. mfsdr(SDR0_ETH_CFG, eth_cfg);
  572. if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
  573. ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0) &&
  574. ((eth_cfg & SDR0_ETH_CFG_SGMII2_ENABLE) > 0))
  575. mode = 12; /* config SGMII */
  576. #endif
  577. /* TODO:
  578. * NOTE: 460GT has 2 RGMII bridge cores:
  579. * emac0 ------ RGMII0_BASE
  580. * |
  581. * emac1 -----+
  582. *
  583. * emac2 ------ RGMII1_BASE
  584. * |
  585. * emac3 -----+
  586. *
  587. * 460EX has 1 RGMII bridge core:
  588. * and RGMII1_BASE is disabled
  589. * emac0 ------ RGMII0_BASE
  590. * |
  591. * emac1 -----+
  592. */
  593. /*
  594. * Right now only 2*RGMII is supported. Please extend when needed.
  595. * sr - 2008-02-19
  596. * Add SGMII support.
  597. * vg - 2008-07-28
  598. */
  599. switch (mode) {
  600. case 1:
  601. /* 1 MII - 460EX */
  602. /* GMC0 EMAC4_0, ZMII Bridge */
  603. zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
  604. bis->bi_phymode[0] = BI_PHYMODE_MII;
  605. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  606. bis->bi_phymode[2] = BI_PHYMODE_NONE;
  607. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  608. break;
  609. case 2:
  610. /* 2 MII - 460GT */
  611. /* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */
  612. zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
  613. zmiifer |= ZMII_FER_MII << ZMII_FER_V(2);
  614. bis->bi_phymode[0] = BI_PHYMODE_MII;
  615. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  616. bis->bi_phymode[2] = BI_PHYMODE_MII;
  617. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  618. break;
  619. case 3:
  620. /* 2 RMII - 460EX */
  621. /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
  622. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
  623. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
  624. bis->bi_phymode[0] = BI_PHYMODE_RMII;
  625. bis->bi_phymode[1] = BI_PHYMODE_RMII;
  626. bis->bi_phymode[2] = BI_PHYMODE_NONE;
  627. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  628. break;
  629. case 4:
  630. /* 4 RMII - 460GT */
  631. /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */
  632. /* ZMII Bridge */
  633. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
  634. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
  635. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
  636. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
  637. bis->bi_phymode[0] = BI_PHYMODE_RMII;
  638. bis->bi_phymode[1] = BI_PHYMODE_RMII;
  639. bis->bi_phymode[2] = BI_PHYMODE_RMII;
  640. bis->bi_phymode[3] = BI_PHYMODE_RMII;
  641. break;
  642. case 5:
  643. /* 2 SMII - 460EX */
  644. /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
  645. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
  646. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
  647. bis->bi_phymode[0] = BI_PHYMODE_SMII;
  648. bis->bi_phymode[1] = BI_PHYMODE_SMII;
  649. bis->bi_phymode[2] = BI_PHYMODE_NONE;
  650. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  651. break;
  652. case 6:
  653. /* 4 SMII - 460GT */
  654. /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */
  655. /* ZMII Bridge */
  656. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
  657. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
  658. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
  659. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
  660. bis->bi_phymode[0] = BI_PHYMODE_SMII;
  661. bis->bi_phymode[1] = BI_PHYMODE_SMII;
  662. bis->bi_phymode[2] = BI_PHYMODE_SMII;
  663. bis->bi_phymode[3] = BI_PHYMODE_SMII;
  664. break;
  665. case 7:
  666. /* This is the default mode that we want for board bringup - Maple */
  667. /* 1 GMII - 460EX */
  668. /* GMC0 EMAC4_0, RGMII Bridge 0 */
  669. rmiifer |= RGMII_FER_MDIO(0);
  670. if (devnum == 0) {
  671. rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
  672. bis->bi_phymode[0] = BI_PHYMODE_GMII;
  673. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  674. bis->bi_phymode[2] = BI_PHYMODE_NONE;
  675. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  676. } else {
  677. rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */
  678. bis->bi_phymode[0] = BI_PHYMODE_NONE;
  679. bis->bi_phymode[1] = BI_PHYMODE_GMII;
  680. bis->bi_phymode[2] = BI_PHYMODE_NONE;
  681. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  682. }
  683. break;
  684. case 8:
  685. /* 2 GMII - 460GT */
  686. /* GMC0 EMAC4_0, RGMII Bridge 0 */
  687. /* GMC1 EMAC4_2, RGMII Bridge 1 */
  688. rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
  689. rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC2 */
  690. rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
  691. rmiifer1 |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */
  692. bis->bi_phymode[0] = BI_PHYMODE_GMII;
  693. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  694. bis->bi_phymode[2] = BI_PHYMODE_GMII;
  695. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  696. break;
  697. case 9:
  698. /* 2 RGMII - 460EX */
  699. /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
  700. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
  701. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
  702. rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
  703. bis->bi_phymode[0] = BI_PHYMODE_RGMII;
  704. bis->bi_phymode[1] = BI_PHYMODE_RGMII;
  705. bis->bi_phymode[2] = BI_PHYMODE_NONE;
  706. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  707. break;
  708. case 10:
  709. /* 4 RGMII - 460GT */
  710. /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
  711. /* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */
  712. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
  713. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
  714. rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2);
  715. rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3);
  716. bis->bi_phymode[0] = BI_PHYMODE_RGMII;
  717. bis->bi_phymode[1] = BI_PHYMODE_RGMII;
  718. bis->bi_phymode[2] = BI_PHYMODE_RGMII;
  719. bis->bi_phymode[3] = BI_PHYMODE_RGMII;
  720. break;
  721. case 11:
  722. /* 2 SGMII - 460EX */
  723. bis->bi_phymode[0] = BI_PHYMODE_SGMII;
  724. bis->bi_phymode[1] = BI_PHYMODE_SGMII;
  725. bis->bi_phymode[2] = BI_PHYMODE_NONE;
  726. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  727. break;
  728. case 12:
  729. /* 3 SGMII - 460GT */
  730. bis->bi_phymode[0] = BI_PHYMODE_SGMII;
  731. bis->bi_phymode[1] = BI_PHYMODE_SGMII;
  732. bis->bi_phymode[2] = BI_PHYMODE_SGMII;
  733. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  734. break;
  735. default:
  736. break;
  737. }
  738. /* Set EMAC for MDIO */
  739. mfsdr(SDR0_ETH_CFG, eth_cfg);
  740. eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
  741. mtsdr(SDR0_ETH_CFG, eth_cfg);
  742. out_be32((void *)RGMII_FER, rmiifer);
  743. #if defined(CONFIG_460GT)
  744. out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1);
  745. #endif
  746. /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
  747. mfsdr(SDR0_ETH_CFG, eth_cfg);
  748. eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
  749. mtsdr(SDR0_ETH_CFG, eth_cfg);
  750. return 0;
  751. }
  752. #endif /* CONFIG_460EX || CONFIG_460GT */
  753. static inline void *malloc_aligned(u32 size, u32 align)
  754. {
  755. return (void *)(((u32)malloc(size + align) + align - 1) &
  756. ~(align - 1));
  757. }
  758. static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
  759. {
  760. int i;
  761. unsigned long reg = 0;
  762. unsigned long msr;
  763. unsigned long speed;
  764. unsigned long duplex;
  765. unsigned long failsafe;
  766. unsigned mode_reg;
  767. unsigned short devnum;
  768. unsigned short reg_short;
  769. #if defined(CONFIG_440GX) || \
  770. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  771. defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  772. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  773. defined(CONFIG_405EX)
  774. u32 opbfreq;
  775. sys_info_t sysinfo;
  776. #if defined(CONFIG_440GX) || \
  777. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  778. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  779. defined(CONFIG_405EX)
  780. __maybe_unused int ethgroup = -1;
  781. #endif
  782. #endif
  783. u32 bd_cached;
  784. u32 bd_uncached = 0;
  785. #ifdef CONFIG_4xx_DCACHE
  786. static u32 last_used_ea = 0;
  787. #endif
  788. #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  789. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  790. defined(CONFIG_405EX)
  791. int rgmii_channel;
  792. #endif
  793. EMAC_4XX_HW_PST hw_p = dev->priv;
  794. /* before doing anything, figure out if we have a MAC address */
  795. /* if not, bail */
  796. if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
  797. printf("ERROR: ethaddr not set!\n");
  798. return -1;
  799. }
  800. #if defined(CONFIG_440GX) || \
  801. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  802. defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  803. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  804. defined(CONFIG_405EX)
  805. /* Need to get the OPB frequency so we can access the PHY */
  806. get_sys_info (&sysinfo);
  807. #endif
  808. msr = mfmsr ();
  809. mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
  810. devnum = hw_p->devnum;
  811. #ifdef INFO_4XX_ENET
  812. /* AS.HARNOIS
  813. * We should have :
  814. * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
  815. * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
  816. * is possible that new packets (without relationship with
  817. * current transfer) have got the time to arrived before
  818. * netloop calls eth_halt
  819. */
  820. printf ("About preceeding transfer (eth%d):\n"
  821. "- Sent packet number %d\n"
  822. "- Received packet number %d\n"
  823. "- Handled packet number %d\n",
  824. hw_p->devnum,
  825. hw_p->stats.pkts_tx,
  826. hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
  827. hw_p->stats.pkts_tx = 0;
  828. hw_p->stats.pkts_rx = 0;
  829. hw_p->stats.pkts_handled = 0;
  830. hw_p->print_speed = 1; /* print speed message again next time */
  831. #endif
  832. hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
  833. hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
  834. hw_p->rx_slot = 0; /* MAL Receive Slot */
  835. hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
  836. hw_p->rx_u_index = 0; /* Receive User Queue Index */
  837. hw_p->tx_slot = 0; /* MAL Transmit Slot */
  838. hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
  839. hw_p->tx_u_index = 0; /* Transmit User Queue Index */
  840. #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
  841. /* set RMII mode */
  842. /* NOTE: 440GX spec states that mode is mutually exclusive */
  843. /* NOTE: Therefore, disable all other EMACS, since we handle */
  844. /* NOTE: only one emac at a time */
  845. reg = 0;
  846. out_be32((void *)ZMII0_FER, 0);
  847. udelay (100);
  848. #if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
  849. out_be32((void *)ZMII0_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
  850. #elif defined(CONFIG_440GX) || \
  851. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  852. defined(CONFIG_460EX) || defined(CONFIG_460GT)
  853. ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
  854. #endif
  855. out_be32((void *)ZMII0_SSR, ZMII0_SSR_SP << ZMII0_SSR_V(devnum));
  856. #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
  857. #if defined(CONFIG_405EX)
  858. ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
  859. #endif
  860. sync();
  861. /* provide clocks for EMAC internal loopback */
  862. emac_loopback_enable(hw_p);
  863. /* EMAC RESET */
  864. out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST);
  865. /* remove clocks for EMAC internal loopback */
  866. emac_loopback_disable(hw_p);
  867. failsafe = 1000;
  868. while ((in_be32((void *)EMAC0_MR0 + hw_p->hw_addr) & (EMAC_MR0_SRST)) && failsafe) {
  869. udelay (1000);
  870. failsafe--;
  871. }
  872. if (failsafe <= 0)
  873. printf("\nProblem resetting EMAC!\n");
  874. #if defined(CONFIG_440GX) || \
  875. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  876. defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  877. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  878. defined(CONFIG_405EX)
  879. /* Whack the M1 register */
  880. mode_reg = 0x0;
  881. mode_reg &= ~0x00000038;
  882. opbfreq = sysinfo.freqOPB / 1000000;
  883. if (opbfreq <= 50);
  884. else if (opbfreq <= 66)
  885. mode_reg |= EMAC_MR1_OBCI_66;
  886. else if (opbfreq <= 83)
  887. mode_reg |= EMAC_MR1_OBCI_83;
  888. else if (opbfreq <= 100)
  889. mode_reg |= EMAC_MR1_OBCI_100;
  890. else
  891. mode_reg |= EMAC_MR1_OBCI_GT100;
  892. out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
  893. #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
  894. #if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \
  895. defined(CONFIG_GPCS_PHY2_ADDR) || defined(CONFIG_GPCS_PHY3_ADDR)
  896. if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
  897. /*
  898. * In SGMII mode, GPCS access is needed for
  899. * communication with the internal SGMII SerDes.
  900. */
  901. switch (devnum) {
  902. #if defined(CONFIG_GPCS_PHY_ADDR)
  903. case 0:
  904. reg = CONFIG_GPCS_PHY_ADDR;
  905. break;
  906. #endif
  907. #if defined(CONFIG_GPCS_PHY1_ADDR)
  908. case 1:
  909. reg = CONFIG_GPCS_PHY1_ADDR;
  910. break;
  911. #endif
  912. #if defined(CONFIG_GPCS_PHY2_ADDR)
  913. case 2:
  914. reg = CONFIG_GPCS_PHY2_ADDR;
  915. break;
  916. #endif
  917. #if defined(CONFIG_GPCS_PHY3_ADDR)
  918. case 3:
  919. reg = CONFIG_GPCS_PHY3_ADDR;
  920. break;
  921. #endif
  922. }
  923. mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr);
  924. mode_reg |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_IPPA_SET(reg);
  925. out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
  926. /* Configure GPCS interface to recommended setting for SGMII */
  927. miiphy_reset(dev->name, reg);
  928. miiphy_write(dev->name, reg, 0x04, 0x8120); /* AsymPause, FDX */
  929. miiphy_write(dev->name, reg, 0x07, 0x2801); /* msg_pg, toggle */
  930. miiphy_write(dev->name, reg, 0x00, 0x0140); /* 1Gbps, FDX */
  931. }
  932. #endif /* defined(CONFIG_GPCS_PHY_ADDR) */
  933. /* wait for PHY to complete auto negotiation */
  934. reg_short = 0;
  935. switch (devnum) {
  936. case 0:
  937. reg = CONFIG_PHY_ADDR;
  938. break;
  939. #if defined (CONFIG_PHY1_ADDR)
  940. case 1:
  941. reg = CONFIG_PHY1_ADDR;
  942. break;
  943. #endif
  944. #if defined (CONFIG_PHY2_ADDR)
  945. case 2:
  946. reg = CONFIG_PHY2_ADDR;
  947. break;
  948. #endif
  949. #if defined (CONFIG_PHY3_ADDR)
  950. case 3:
  951. reg = CONFIG_PHY3_ADDR;
  952. break;
  953. #endif
  954. default:
  955. reg = CONFIG_PHY_ADDR;
  956. break;
  957. }
  958. bis->bi_phynum[devnum] = reg;
  959. if (reg == CONFIG_FIXED_PHY)
  960. goto get_speed;
  961. #if defined(CONFIG_PHY_RESET)
  962. /*
  963. * Reset the phy, only if its the first time through
  964. * otherwise, just check the speeds & feeds
  965. */
  966. if (hw_p->first_init == 0) {
  967. #if defined(CONFIG_M88E1111_PHY)
  968. miiphy_write (dev->name, reg, 0x14, 0x0ce3);
  969. miiphy_write (dev->name, reg, 0x18, 0x4101);
  970. miiphy_write (dev->name, reg, 0x09, 0x0e00);
  971. miiphy_write (dev->name, reg, 0x04, 0x01e1);
  972. #if defined(CONFIG_M88E1111_DISABLE_FIBER)
  973. miiphy_read(dev->name, reg, 0x1b, &reg_short);
  974. reg_short |= 0x8000;
  975. miiphy_write(dev->name, reg, 0x1b, reg_short);
  976. #endif
  977. #endif
  978. #if defined(CONFIG_M88E1112_PHY)
  979. if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
  980. /*
  981. * Marvell 88E1112 PHY needs to have the SGMII MAC
  982. * interace (page 2) properly configured to
  983. * communicate with the 460EX/GT GPCS interface.
  984. */
  985. /* Set access to Page 2 */
  986. miiphy_write(dev->name, reg, 0x16, 0x0002);
  987. miiphy_write(dev->name, reg, 0x00, 0x0040); /* 1Gbps */
  988. miiphy_read(dev->name, reg, 0x1a, &reg_short);
  989. reg_short |= 0x8000; /* bypass Auto-Negotiation */
  990. miiphy_write(dev->name, reg, 0x1a, reg_short);
  991. miiphy_reset(dev->name, reg); /* reset MAC interface */
  992. /* Reset access to Page 0 */
  993. miiphy_write(dev->name, reg, 0x16, 0x0000);
  994. }
  995. #endif /* defined(CONFIG_M88E1112_PHY) */
  996. miiphy_reset (dev->name, reg);
  997. #if defined(CONFIG_440GX) || \
  998. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  999. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  1000. defined(CONFIG_405EX)
  1001. #if defined(CONFIG_CIS8201_PHY)
  1002. /*
  1003. * Cicada 8201 PHY needs to have an extended register whacked
  1004. * for RGMII mode.
  1005. */
  1006. if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
  1007. #if defined(CONFIG_CIS8201_SHORT_ETCH)
  1008. miiphy_write (dev->name, reg, 23, 0x1300);
  1009. #else
  1010. miiphy_write (dev->name, reg, 23, 0x1000);
  1011. #endif
  1012. /*
  1013. * Vitesse VSC8201/Cicada CIS8201 errata:
  1014. * Interoperability problem with Intel 82547EI phys
  1015. * This work around (provided by Vitesse) changes
  1016. * the default timer convergence from 8ms to 12ms
  1017. */
  1018. miiphy_write (dev->name, reg, 0x1f, 0x2a30);
  1019. miiphy_write (dev->name, reg, 0x08, 0x0200);
  1020. miiphy_write (dev->name, reg, 0x1f, 0x52b5);
  1021. miiphy_write (dev->name, reg, 0x02, 0x0004);
  1022. miiphy_write (dev->name, reg, 0x01, 0x0671);
  1023. miiphy_write (dev->name, reg, 0x00, 0x8fae);
  1024. miiphy_write (dev->name, reg, 0x1f, 0x2a30);
  1025. miiphy_write (dev->name, reg, 0x08, 0x0000);
  1026. miiphy_write (dev->name, reg, 0x1f, 0x0000);
  1027. /* end Vitesse/Cicada errata */
  1028. }
  1029. #endif /* defined(CONFIG_CIS8201_PHY) */
  1030. #if defined(CONFIG_ET1011C_PHY)
  1031. /*
  1032. * Agere ET1011c PHY needs to have an extended register whacked
  1033. * for RGMII mode.
  1034. */
  1035. if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
  1036. miiphy_read (dev->name, reg, 0x16, &reg_short);
  1037. reg_short &= ~(0x7);
  1038. reg_short |= 0x6; /* RGMII DLL Delay*/
  1039. miiphy_write (dev->name, reg, 0x16, reg_short);
  1040. miiphy_read (dev->name, reg, 0x17, &reg_short);
  1041. reg_short &= ~(0x40);
  1042. miiphy_write (dev->name, reg, 0x17, reg_short);
  1043. miiphy_write(dev->name, reg, 0x1c, 0x74f0);
  1044. }
  1045. #endif /* defined(CONFIG_ET1011C_PHY) */
  1046. #endif /* defined(CONFIG_440GX) ... */
  1047. /* Start/Restart autonegotiation */
  1048. phy_setup_aneg (dev->name, reg);
  1049. udelay (1000);
  1050. }
  1051. #endif /* defined(CONFIG_PHY_RESET) */
  1052. miiphy_read (dev->name, reg, MII_BMSR, &reg_short);
  1053. /*
  1054. * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
  1055. */
  1056. if ((reg_short & BMSR_ANEGCAPABLE)
  1057. && !(reg_short & BMSR_ANEGCOMPLETE)) {
  1058. puts ("Waiting for PHY auto negotiation to complete");
  1059. i = 0;
  1060. while (!(reg_short & BMSR_ANEGCOMPLETE)) {
  1061. /*
  1062. * Timeout reached ?
  1063. */
  1064. if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
  1065. puts (" TIMEOUT !\n");
  1066. break;
  1067. }
  1068. if ((i++ % 1000) == 0) {
  1069. putc ('.');
  1070. }
  1071. udelay (1000); /* 1 ms */
  1072. miiphy_read (dev->name, reg, MII_BMSR, &reg_short);
  1073. }
  1074. puts (" done\n");
  1075. udelay (500000); /* another 500 ms (results in faster booting) */
  1076. }
  1077. get_speed:
  1078. if (reg == CONFIG_FIXED_PHY) {
  1079. for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
  1080. if (devnum == fixed_phy_port[i].devnum) {
  1081. speed = fixed_phy_port[i].speed;
  1082. duplex = fixed_phy_port[i].duplex;
  1083. break;
  1084. }
  1085. }
  1086. if (i == ARRAY_SIZE(fixed_phy_port)) {
  1087. printf("ERROR: PHY (%s) not configured correctly!\n",
  1088. dev->name);
  1089. return -1;
  1090. }
  1091. } else {
  1092. speed = miiphy_speed(dev->name, reg);
  1093. duplex = miiphy_duplex(dev->name, reg);
  1094. }
  1095. if (hw_p->print_speed) {
  1096. hw_p->print_speed = 0;
  1097. printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
  1098. (int) speed, (duplex == HALF) ? "HALF" : "FULL",
  1099. hw_p->devnum);
  1100. }
  1101. #if defined(CONFIG_440) && \
  1102. !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
  1103. !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
  1104. !defined(CONFIG_460EX) && !defined(CONFIG_460GT)
  1105. #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
  1106. mfsdr(SDR0_MFR, reg);
  1107. if (speed == 100) {
  1108. reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
  1109. } else {
  1110. reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
  1111. }
  1112. mtsdr(SDR0_MFR, reg);
  1113. #endif
  1114. /* Set ZMII/RGMII speed according to the phy link speed */
  1115. reg = in_be32((void *)ZMII0_SSR);
  1116. if ( (speed == 100) || (speed == 1000) )
  1117. out_be32((void *)ZMII0_SSR, reg | (ZMII0_SSR_SP << ZMII0_SSR_V (devnum)));
  1118. else
  1119. out_be32((void *)ZMII0_SSR, reg & (~(ZMII0_SSR_SP << ZMII0_SSR_V (devnum))));
  1120. if ((devnum == 2) || (devnum == 3)) {
  1121. if (speed == 1000)
  1122. reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
  1123. else if (speed == 100)
  1124. reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
  1125. else if (speed == 10)
  1126. reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
  1127. else {
  1128. printf("Error in RGMII Speed\n");
  1129. return -1;
  1130. }
  1131. out_be32((void *)RGMII_SSR, reg);
  1132. }
  1133. #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
  1134. #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  1135. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  1136. defined(CONFIG_405EX)
  1137. if (devnum >= 2)
  1138. rgmii_channel = devnum - 2;
  1139. else
  1140. rgmii_channel = devnum;
  1141. if (speed == 1000)
  1142. reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel));
  1143. else if (speed == 100)
  1144. reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel));
  1145. else if (speed == 10)
  1146. reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel));
  1147. else {
  1148. printf("Error in RGMII Speed\n");
  1149. return -1;
  1150. }
  1151. out_be32((void *)RGMII_SSR, reg);
  1152. #if defined(CONFIG_460GT)
  1153. if ((devnum == 2) || (devnum == 3))
  1154. out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg);
  1155. #endif
  1156. #endif
  1157. /* set the Mal configuration reg */
  1158. #if defined(CONFIG_440GX) || \
  1159. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  1160. defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  1161. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  1162. defined(CONFIG_405EX)
  1163. mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
  1164. MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
  1165. #else
  1166. mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
  1167. /* Errata 1.12: MAL_1 -- Disable MAL bursting */
  1168. if (get_pvr() == PVR_440GP_RB) {
  1169. mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB);
  1170. }
  1171. #endif
  1172. /*
  1173. * Malloc MAL buffer desciptors, make sure they are
  1174. * aligned on cache line boundary size
  1175. * (401/403/IOP480 = 16, 405 = 32)
  1176. * and doesn't cross cache block boundaries.
  1177. */
  1178. if (hw_p->first_init == 0) {
  1179. debug("*** Allocating descriptor memory ***\n");
  1180. bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096);
  1181. if (!bd_cached) {
  1182. printf("%s: Error allocating MAL descriptor buffers!\n", __func__);
  1183. return -1;
  1184. }
  1185. #ifdef CONFIG_4xx_DCACHE
  1186. flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
  1187. if (!last_used_ea)
  1188. #if defined(CONFIG_SYS_MEM_TOP_HIDE)
  1189. bd_uncached = bis->bi_memsize + CONFIG_SYS_MEM_TOP_HIDE;
  1190. #else
  1191. bd_uncached = bis->bi_memsize;
  1192. #endif
  1193. else
  1194. bd_uncached = last_used_ea + MAL_ALLOC_SIZE;
  1195. last_used_ea = bd_uncached;
  1196. program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
  1197. TLB_WORD2_I_ENABLE);
  1198. #else
  1199. bd_uncached = bd_cached;
  1200. #endif
  1201. hw_p->tx_phys = bd_cached;
  1202. hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
  1203. hw_p->tx = (mal_desc_t *)(bd_uncached);
  1204. hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
  1205. debug("hw_p->tx=%p, hw_p->rx=%p\n", hw_p->tx, hw_p->rx);
  1206. }
  1207. for (i = 0; i < NUM_TX_BUFF; i++) {
  1208. hw_p->tx[i].ctrl = 0;
  1209. hw_p->tx[i].data_len = 0;
  1210. if (hw_p->first_init == 0)
  1211. hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE,
  1212. L1_CACHE_BYTES);
  1213. hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
  1214. if ((NUM_TX_BUFF - 1) == i)
  1215. hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
  1216. hw_p->tx_run[i] = -1;
  1217. debug("TX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->tx[i].data_ptr);
  1218. }
  1219. for (i = 0; i < NUM_RX_BUFF; i++) {
  1220. hw_p->rx[i].ctrl = 0;
  1221. hw_p->rx[i].data_len = 0;
  1222. hw_p->rx[i].data_ptr = (char *)NetRxPackets[i];
  1223. if ((NUM_RX_BUFF - 1) == i)
  1224. hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
  1225. hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
  1226. hw_p->rx_ready[i] = -1;
  1227. debug("RX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->rx[i].data_ptr);
  1228. }
  1229. reg = 0x00000000;
  1230. reg |= dev->enetaddr[0]; /* set high address */
  1231. reg = reg << 8;
  1232. reg |= dev->enetaddr[1];
  1233. out_be32((void *)EMAC0_IAH + hw_p->hw_addr, reg);
  1234. reg = 0x00000000;
  1235. reg |= dev->enetaddr[2]; /* set low address */
  1236. reg = reg << 8;
  1237. reg |= dev->enetaddr[3];
  1238. reg = reg << 8;
  1239. reg |= dev->enetaddr[4];
  1240. reg = reg << 8;
  1241. reg |= dev->enetaddr[5];
  1242. out_be32((void *)EMAC0_IAL + hw_p->hw_addr, reg);
  1243. switch (devnum) {
  1244. case 1:
  1245. /* setup MAL tx & rx channel pointers */
  1246. #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
  1247. mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
  1248. #else
  1249. mtdcr (MAL0_TXCTP1R, hw_p->tx_phys);
  1250. #endif
  1251. #if defined(CONFIG_440)
  1252. mtdcr (MAL0_TXBADDR, 0x0);
  1253. mtdcr (MAL0_RXBADDR, 0x0);
  1254. #endif
  1255. #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  1256. mtdcr (MAL0_RXCTP8R, hw_p->rx_phys);
  1257. /* set RX buffer size */
  1258. mtdcr (MAL0_RCBS8, ENET_MAX_MTU_ALIGNED / 16);
  1259. #else
  1260. mtdcr (MAL0_RXCTP1R, hw_p->rx_phys);
  1261. /* set RX buffer size */
  1262. mtdcr (MAL0_RCBS1, ENET_MAX_MTU_ALIGNED / 16);
  1263. #endif
  1264. break;
  1265. #if defined (CONFIG_440GX)
  1266. case 2:
  1267. /* setup MAL tx & rx channel pointers */
  1268. mtdcr (MAL0_TXBADDR, 0x0);
  1269. mtdcr (MAL0_RXBADDR, 0x0);
  1270. mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
  1271. mtdcr (MAL0_RXCTP2R, hw_p->rx_phys);
  1272. /* set RX buffer size */
  1273. mtdcr (MAL0_RCBS2, ENET_MAX_MTU_ALIGNED / 16);
  1274. break;
  1275. case 3:
  1276. /* setup MAL tx & rx channel pointers */
  1277. mtdcr (MAL0_TXBADDR, 0x0);
  1278. mtdcr (MAL0_TXCTP3R, hw_p->tx_phys);
  1279. mtdcr (MAL0_RXBADDR, 0x0);
  1280. mtdcr (MAL0_RXCTP3R, hw_p->rx_phys);
  1281. /* set RX buffer size */
  1282. mtdcr (MAL0_RCBS3, ENET_MAX_MTU_ALIGNED / 16);
  1283. break;
  1284. #endif /* CONFIG_440GX */
  1285. #if defined (CONFIG_460GT)
  1286. case 2:
  1287. /* setup MAL tx & rx channel pointers */
  1288. mtdcr (MAL0_TXBADDR, 0x0);
  1289. mtdcr (MAL0_RXBADDR, 0x0);
  1290. mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
  1291. mtdcr (MAL0_RXCTP16R, hw_p->rx_phys);
  1292. /* set RX buffer size */
  1293. mtdcr (MAL0_RCBS16, ENET_MAX_MTU_ALIGNED / 16);
  1294. break;
  1295. case 3:
  1296. /* setup MAL tx & rx channel pointers */
  1297. mtdcr (MAL0_TXBADDR, 0x0);
  1298. mtdcr (MAL0_RXBADDR, 0x0);
  1299. mtdcr (MAL0_TXCTP3R, hw_p->tx_phys);
  1300. mtdcr (MAL0_RXCTP24R, hw_p->rx_phys);
  1301. /* set RX buffer size */
  1302. mtdcr (MAL0_RCBS24, ENET_MAX_MTU_ALIGNED / 16);
  1303. break;
  1304. #endif /* CONFIG_460GT */
  1305. case 0:
  1306. default:
  1307. /* setup MAL tx & rx channel pointers */
  1308. #if defined(CONFIG_440)
  1309. mtdcr (MAL0_TXBADDR, 0x0);
  1310. mtdcr (MAL0_RXBADDR, 0x0);
  1311. #endif
  1312. mtdcr (MAL0_TXCTP0R, hw_p->tx_phys);
  1313. mtdcr (MAL0_RXCTP0R, hw_p->rx_phys);
  1314. /* set RX buffer size */
  1315. mtdcr (MAL0_RCBS0, ENET_MAX_MTU_ALIGNED / 16);
  1316. break;
  1317. }
  1318. /* Enable MAL transmit and receive channels */
  1319. #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
  1320. mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
  1321. #else
  1322. mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> hw_p->devnum));
  1323. #endif
  1324. mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> hw_p->devnum));
  1325. /* set transmit enable & receive enable */
  1326. out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_TXE | EMAC_MR0_RXE);
  1327. mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr);
  1328. /* set rx-/tx-fifo size */
  1329. mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE;
  1330. /* set speed */
  1331. if (speed == _1000BASET) {
  1332. #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
  1333. unsigned long pfc1;
  1334. mfsdr (SDR0_PFC1, pfc1);
  1335. pfc1 |= SDR0_PFC1_EM_1000;
  1336. mtsdr (SDR0_PFC1, pfc1);
  1337. #endif
  1338. mode_reg = mode_reg | EMAC_MR1_MF_1000MBPS | EMAC_MR1_IST;
  1339. } else if (speed == _100BASET)
  1340. mode_reg = mode_reg | EMAC_MR1_MF_100MBPS | EMAC_MR1_IST;
  1341. else
  1342. mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
  1343. if (duplex == FULL)
  1344. mode_reg = mode_reg | 0x80000000 | EMAC_MR1_IST;
  1345. out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
  1346. /* Enable broadcast and indvidual address */
  1347. /* TBS: enabling runts as some misbehaved nics will send runts */
  1348. out_be32((void *)EMAC0_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
  1349. /* we probably need to set the tx mode1 reg? maybe at tx time */
  1350. /* set transmit request threshold register */
  1351. out_be32((void *)EMAC0_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
  1352. /* set receive low/high water mark register */
  1353. #if defined(CONFIG_440)
  1354. /* 440s has a 64 byte burst length */
  1355. out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
  1356. #else
  1357. /* 405s have a 16 byte burst length */
  1358. out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
  1359. #endif /* defined(CONFIG_440) */
  1360. out_be32((void *)EMAC0_TMR1 + hw_p->hw_addr, 0xf8640000);
  1361. /* Set fifo limit entry in tx mode 0 */
  1362. out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, 0x00000003);
  1363. /* Frame gap set */
  1364. out_be32((void *)EMAC0_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
  1365. /* Set EMAC IER */
  1366. hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
  1367. if (speed == _100BASET)
  1368. hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
  1369. out_be32((void *)EMAC0_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
  1370. out_be32((void *)EMAC0_IER + hw_p->hw_addr, hw_p->emac_ier);
  1371. if (hw_p->first_init == 0) {
  1372. /*
  1373. * Connect interrupt service routines
  1374. */
  1375. irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
  1376. (interrupt_handler_t *) enetInt, dev);
  1377. }
  1378. mtmsr (msr); /* enable interrupts again */
  1379. hw_p->bis = bis;
  1380. hw_p->first_init = 1;
  1381. return 0;
  1382. }
  1383. static int ppc_4xx_eth_send(struct eth_device *dev, void *ptr, int len)
  1384. {
  1385. struct enet_frame *ef_ptr;
  1386. ulong time_start, time_now;
  1387. unsigned long temp_txm0;
  1388. EMAC_4XX_HW_PST hw_p = dev->priv;
  1389. ef_ptr = (struct enet_frame *) ptr;
  1390. /*-----------------------------------------------------------------------+
  1391. * Copy in our address into the frame.
  1392. *-----------------------------------------------------------------------*/
  1393. (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
  1394. /*-----------------------------------------------------------------------+
  1395. * If frame is too long or too short, modify length.
  1396. *-----------------------------------------------------------------------*/
  1397. /* TBS: where does the fragment go???? */
  1398. if (len > ENET_MAX_MTU)
  1399. len = ENET_MAX_MTU;
  1400. /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
  1401. memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
  1402. flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len);
  1403. /*-----------------------------------------------------------------------+
  1404. * set TX Buffer busy, and send it
  1405. *-----------------------------------------------------------------------*/
  1406. hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
  1407. EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
  1408. ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
  1409. if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
  1410. hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
  1411. hw_p->tx[hw_p->tx_slot].data_len = (short) len;
  1412. hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
  1413. sync();
  1414. out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr,
  1415. in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr) | EMAC_TMR0_GNP0);
  1416. #ifdef INFO_4XX_ENET
  1417. hw_p->stats.pkts_tx++;
  1418. #endif
  1419. /*-----------------------------------------------------------------------+
  1420. * poll unitl the packet is sent and then make sure it is OK
  1421. *-----------------------------------------------------------------------*/
  1422. time_start = get_timer (0);
  1423. while (1) {
  1424. temp_txm0 = in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr);
  1425. /* loop until either TINT turns on or 3 seconds elapse */
  1426. if ((temp_txm0 & EMAC_TMR0_GNP0) != 0) {
  1427. /* transmit is done, so now check for errors
  1428. * If there is an error, an interrupt should
  1429. * happen when we return
  1430. */
  1431. time_now = get_timer (0);
  1432. if ((time_now - time_start) > 3000) {
  1433. return (-1);
  1434. }
  1435. } else {
  1436. return (len);
  1437. }
  1438. }
  1439. }
  1440. int enetInt (struct eth_device *dev)
  1441. {
  1442. int serviced;
  1443. int rc = -1; /* default to not us */
  1444. u32 mal_isr;
  1445. u32 emac_isr = 0;
  1446. u32 mal_eob;
  1447. u32 uic_mal;
  1448. u32 uic_mal_err;
  1449. u32 uic_emac;
  1450. u32 uic_emac_b;
  1451. EMAC_4XX_HW_PST hw_p;
  1452. /*
  1453. * Because the mal is generic, we need to get the current
  1454. * eth device
  1455. */
  1456. dev = eth_get_dev();
  1457. hw_p = dev->priv;
  1458. /* enter loop that stays in interrupt code until nothing to service */
  1459. do {
  1460. serviced = 0;
  1461. uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR);
  1462. uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR);
  1463. uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR);
  1464. uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR);
  1465. if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB))
  1466. && !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE))
  1467. && !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) {
  1468. /* not for us */
  1469. return (rc);
  1470. }
  1471. /* get and clear controller status interrupts */
  1472. /* look at MAL and EMAC error interrupts */
  1473. if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) {
  1474. /* we have a MAL error interrupt */
  1475. mal_isr = mfdcr(MAL0_ESR);
  1476. mal_err(dev, mal_isr, uic_mal_err,
  1477. MAL_UIC_DEF, MAL_UIC_ERR);
  1478. /* clear MAL error interrupt status bits */
  1479. mtdcr(UIC_BASE_MAL_ERR + UIC_SR,
  1480. UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE);
  1481. return -1;
  1482. }
  1483. /* look for EMAC errors */
  1484. if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) {
  1485. emac_isr = in_be32((void *)EMAC0_ISR + hw_p->hw_addr);
  1486. emac_err(dev, emac_isr);
  1487. /* clear EMAC error interrupt status bits */
  1488. mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx);
  1489. mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB);
  1490. return -1;
  1491. }
  1492. /* handle MAX TX EOB interrupt from a tx */
  1493. if (uic_mal & UIC_MAL_TXEOB) {
  1494. /* clear MAL interrupt status bits */
  1495. mal_eob = mfdcr(MAL0_TXEOBISR);
  1496. mtdcr(MAL0_TXEOBISR, mal_eob);
  1497. mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB);
  1498. /* indicate that we serviced an interrupt */
  1499. serviced = 1;
  1500. rc = 0;
  1501. }
  1502. /* handle MAL RX EOB interrupt from a receive */
  1503. /* check for EOB on valid channels */
  1504. if (uic_mal & UIC_MAL_RXEOB) {
  1505. mal_eob = mfdcr(MAL0_RXEOBISR);
  1506. if (mal_eob &
  1507. (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) {
  1508. /* push packet to upper layer */
  1509. enet_rcv(dev, emac_isr);
  1510. /* clear MAL interrupt status bits */
  1511. mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB);
  1512. /* indicate that we serviced an interrupt */
  1513. serviced = 1;
  1514. rc = 0;
  1515. }
  1516. }
  1517. #if defined(CONFIG_405EZ)
  1518. /*
  1519. * On 405EZ the RX-/TX-interrupts are coalesced into
  1520. * one IRQ bit in the UIC. We need to acknowledge the
  1521. * RX-/TX-interrupts in the SDR0_ICINTSTAT reg as well.
  1522. */
  1523. mtsdr(SDR0_ICINTSTAT,
  1524. SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
  1525. #endif /* defined(CONFIG_405EZ) */
  1526. } while (serviced);
  1527. return (rc);
  1528. }
  1529. /*-----------------------------------------------------------------------------+
  1530. * MAL Error Routine
  1531. *-----------------------------------------------------------------------------*/
  1532. static void mal_err (struct eth_device *dev, unsigned long isr,
  1533. unsigned long uic, unsigned long maldef,
  1534. unsigned long mal_errr)
  1535. {
  1536. EMAC_4XX_HW_PST hw_p = dev->priv;
  1537. mtdcr (MAL0_ESR, isr); /* clear interrupt */
  1538. /* clear DE interrupt */
  1539. mtdcr (MAL0_TXDEIR, 0xC0000000);
  1540. mtdcr (MAL0_RXDEIR, 0x80000000);
  1541. #ifdef INFO_4XX_ENET
  1542. printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
  1543. #endif
  1544. eth_init (hw_p->bis); /* start again... */
  1545. }
  1546. /*-----------------------------------------------------------------------------+
  1547. * EMAC Error Routine
  1548. *-----------------------------------------------------------------------------*/
  1549. static void emac_err (struct eth_device *dev, unsigned long isr)
  1550. {
  1551. EMAC_4XX_HW_PST hw_p = dev->priv;
  1552. printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
  1553. out_be32((void *)EMAC0_ISR + hw_p->hw_addr, isr);
  1554. }
  1555. /*-----------------------------------------------------------------------------+
  1556. * enet_rcv() handles the ethernet receive data
  1557. *-----------------------------------------------------------------------------*/
  1558. static void enet_rcv (struct eth_device *dev, unsigned long malisr)
  1559. {
  1560. unsigned long data_len;
  1561. unsigned long rx_eob_isr;
  1562. EMAC_4XX_HW_PST hw_p = dev->priv;
  1563. int handled = 0;
  1564. int i;
  1565. int loop_count = 0;
  1566. rx_eob_isr = mfdcr (MAL0_RXEOBISR);
  1567. if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) {
  1568. /* clear EOB */
  1569. mtdcr (MAL0_RXEOBISR, rx_eob_isr);
  1570. /* EMAC RX done */
  1571. while (1) { /* do all */
  1572. i = hw_p->rx_slot;
  1573. if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
  1574. || (loop_count >= NUM_RX_BUFF))
  1575. break;
  1576. loop_count++;
  1577. handled++;
  1578. data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff; /* Get len */
  1579. if (data_len) {
  1580. if (data_len > ENET_MAX_MTU) /* Check len */
  1581. data_len = 0;
  1582. else {
  1583. if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
  1584. data_len = 0;
  1585. hw_p->stats.rx_err_log[hw_p->
  1586. rx_err_index]
  1587. = hw_p->rx[i].ctrl;
  1588. hw_p->rx_err_index++;
  1589. if (hw_p->rx_err_index ==
  1590. MAX_ERR_LOG)
  1591. hw_p->rx_err_index =
  1592. 0;
  1593. } /* emac_erros */
  1594. } /* data_len < max mtu */
  1595. } /* if data_len */
  1596. if (!data_len) { /* no data */
  1597. hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
  1598. hw_p->stats.data_len_err++; /* Error at Rx */
  1599. }
  1600. /* !data_len */
  1601. /* AS.HARNOIS */
  1602. /* Check if user has already eaten buffer */
  1603. /* if not => ERROR */
  1604. else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
  1605. if (hw_p->is_receiving)
  1606. printf ("ERROR : Receive buffers are full!\n");
  1607. break;
  1608. } else {
  1609. hw_p->stats.rx_frames++;
  1610. hw_p->stats.rx += data_len;
  1611. #ifdef INFO_4XX_ENET
  1612. hw_p->stats.pkts_rx++;
  1613. #endif
  1614. /* AS.HARNOIS
  1615. * use ring buffer
  1616. */
  1617. hw_p->rx_ready[hw_p->rx_i_index] = i;
  1618. hw_p->rx_i_index++;
  1619. if (NUM_RX_BUFF == hw_p->rx_i_index)
  1620. hw_p->rx_i_index = 0;
  1621. hw_p->rx_slot++;
  1622. if (NUM_RX_BUFF == hw_p->rx_slot)
  1623. hw_p->rx_slot = 0;
  1624. /* AS.HARNOIS
  1625. * free receive buffer only when
  1626. * buffer has been handled (eth_rx)
  1627. rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
  1628. */
  1629. } /* if data_len */
  1630. } /* while */
  1631. } /* if EMACK_RXCHL */
  1632. }
  1633. static int ppc_4xx_eth_rx (struct eth_device *dev)
  1634. {
  1635. int length;
  1636. int user_index;
  1637. unsigned long msr;
  1638. EMAC_4XX_HW_PST hw_p = dev->priv;
  1639. hw_p->is_receiving = 1; /* tell driver */
  1640. for (;;) {
  1641. /* AS.HARNOIS
  1642. * use ring buffer and
  1643. * get index from rx buffer desciptor queue
  1644. */
  1645. user_index = hw_p->rx_ready[hw_p->rx_u_index];
  1646. if (user_index == -1) {
  1647. length = -1;
  1648. break; /* nothing received - leave for() loop */
  1649. }
  1650. msr = mfmsr ();
  1651. mtmsr (msr & ~(MSR_EE));
  1652. length = hw_p->rx[user_index].data_len & 0x0fff;
  1653. /* Pass the packet up to the protocol layers. */
  1654. /* NetReceive(NetRxPackets[rxIdx], length - 4); */
  1655. /* NetReceive(NetRxPackets[i], length); */
  1656. invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr,
  1657. (u32)hw_p->rx[user_index].data_ptr +
  1658. length - 4);
  1659. NetReceive (NetRxPackets[user_index], length - 4);
  1660. /* Free Recv Buffer */
  1661. hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
  1662. /* Free rx buffer descriptor queue */
  1663. hw_p->rx_ready[hw_p->rx_u_index] = -1;
  1664. hw_p->rx_u_index++;
  1665. if (NUM_RX_BUFF == hw_p->rx_u_index)
  1666. hw_p->rx_u_index = 0;
  1667. #ifdef INFO_4XX_ENET
  1668. hw_p->stats.pkts_handled++;
  1669. #endif
  1670. mtmsr (msr); /* Enable IRQ's */
  1671. }
  1672. hw_p->is_receiving = 0; /* tell driver */
  1673. return length;
  1674. }
  1675. int ppc_4xx_eth_initialize (bd_t * bis)
  1676. {
  1677. static int virgin = 0;
  1678. struct eth_device *dev;
  1679. int eth_num = 0;
  1680. EMAC_4XX_HW_PST hw = NULL;
  1681. u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
  1682. u32 hw_addr[4];
  1683. u32 mal_ier;
  1684. #if defined(CONFIG_440GX)
  1685. unsigned long pfc1;
  1686. mfsdr (SDR0_PFC1, pfc1);
  1687. pfc1 &= ~(0x01e00000);
  1688. pfc1 |= 0x01200000;
  1689. mtsdr (SDR0_PFC1, pfc1);
  1690. #endif
  1691. /* first clear all mac-addresses */
  1692. for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
  1693. memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
  1694. for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
  1695. int ethaddr_idx = eth_num + CONFIG_EMAC_NR_START;
  1696. switch (eth_num) {
  1697. default: /* fall through */
  1698. case 0:
  1699. eth_getenv_enetaddr("ethaddr", ethaddr[ethaddr_idx]);
  1700. hw_addr[eth_num] = 0x0;
  1701. break;
  1702. #ifdef CONFIG_HAS_ETH1
  1703. case 1:
  1704. eth_getenv_enetaddr("eth1addr", ethaddr[ethaddr_idx]);
  1705. hw_addr[eth_num] = 0x100;
  1706. break;
  1707. #endif
  1708. #ifdef CONFIG_HAS_ETH2
  1709. case 2:
  1710. eth_getenv_enetaddr("eth2addr", ethaddr[ethaddr_idx]);
  1711. #if defined(CONFIG_460GT)
  1712. hw_addr[eth_num] = 0x300;
  1713. #else
  1714. hw_addr[eth_num] = 0x400;
  1715. #endif
  1716. break;
  1717. #endif
  1718. #ifdef CONFIG_HAS_ETH3
  1719. case 3:
  1720. eth_getenv_enetaddr("eth3addr", ethaddr[ethaddr_idx]);
  1721. #if defined(CONFIG_460GT)
  1722. hw_addr[eth_num] = 0x400;
  1723. #else
  1724. hw_addr[eth_num] = 0x600;
  1725. #endif
  1726. break;
  1727. #endif
  1728. }
  1729. }
  1730. /* set phy num and mode */
  1731. bis->bi_phynum[0] = CONFIG_PHY_ADDR;
  1732. bis->bi_phymode[0] = 0;
  1733. #if defined(CONFIG_PHY1_ADDR)
  1734. bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
  1735. bis->bi_phymode[1] = 0;
  1736. #endif
  1737. #if defined(CONFIG_440GX)
  1738. bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
  1739. bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
  1740. bis->bi_phymode[2] = 2;
  1741. bis->bi_phymode[3] = 2;
  1742. #endif
  1743. #if defined(CONFIG_440GX) || \
  1744. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  1745. defined(CONFIG_405EX)
  1746. ppc_4xx_eth_setup_bridge(0, bis);
  1747. #endif
  1748. for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
  1749. /*
  1750. * See if we can actually bring up the interface,
  1751. * otherwise, skip it
  1752. */
  1753. if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
  1754. bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
  1755. continue;
  1756. }
  1757. /* Allocate device structure */
  1758. dev = (struct eth_device *) malloc (sizeof (*dev));
  1759. if (dev == NULL) {
  1760. printf ("ppc_4xx_eth_initialize: "
  1761. "Cannot allocate eth_device %d\n", eth_num);
  1762. return (-1);
  1763. }
  1764. memset(dev, 0, sizeof(*dev));
  1765. /* Allocate our private use data */
  1766. hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
  1767. if (hw == NULL) {
  1768. printf ("ppc_4xx_eth_initialize: "
  1769. "Cannot allocate private hw data for eth_device %d",
  1770. eth_num);
  1771. free (dev);
  1772. return (-1);
  1773. }
  1774. memset(hw, 0, sizeof(*hw));
  1775. hw->hw_addr = hw_addr[eth_num];
  1776. memcpy (dev->enetaddr, ethaddr[eth_num], 6);
  1777. hw->devnum = eth_num;
  1778. hw->print_speed = 1;
  1779. sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
  1780. dev->priv = (void *) hw;
  1781. dev->init = ppc_4xx_eth_init;
  1782. dev->halt = ppc_4xx_eth_halt;
  1783. dev->send = ppc_4xx_eth_send;
  1784. dev->recv = ppc_4xx_eth_rx;
  1785. eth_register(dev);
  1786. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  1787. miiphy_register(dev->name,
  1788. emac4xx_miiphy_read, emac4xx_miiphy_write);
  1789. #endif
  1790. if (0 == virgin) {
  1791. /* set the MAL IER ??? names may change with new spec ??? */
  1792. #if defined(CONFIG_440SPE) || \
  1793. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  1794. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  1795. defined(CONFIG_405EX)
  1796. mal_ier =
  1797. MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
  1798. MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
  1799. #else
  1800. mal_ier =
  1801. MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
  1802. MAL_IER_OPBE | MAL_IER_PLBE;
  1803. #endif
  1804. mtdcr (MAL0_ESR, 0xffffffff); /* clear pending interrupts */
  1805. mtdcr (MAL0_TXDEIR, 0xffffffff); /* clear pending interrupts */
  1806. mtdcr (MAL0_RXDEIR, 0xffffffff); /* clear pending interrupts */
  1807. mtdcr (MAL0_IER, mal_ier);
  1808. /* install MAL interrupt handler */
  1809. irq_install_handler (VECNUM_MAL_SERR,
  1810. (interrupt_handler_t *) enetInt,
  1811. dev);
  1812. irq_install_handler (VECNUM_MAL_TXEOB,
  1813. (interrupt_handler_t *) enetInt,
  1814. dev);
  1815. irq_install_handler (VECNUM_MAL_RXEOB,
  1816. (interrupt_handler_t *) enetInt,
  1817. dev);
  1818. irq_install_handler (VECNUM_MAL_TXDE,
  1819. (interrupt_handler_t *) enetInt,
  1820. dev);
  1821. irq_install_handler (VECNUM_MAL_RXDE,
  1822. (interrupt_handler_t *) enetInt,
  1823. dev);
  1824. virgin = 1;
  1825. }
  1826. } /* end for each supported device */
  1827. return 0;
  1828. }