init.S 9.9 KB

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  1. /*
  2. * SPDX-License-Identifier: GPL-2.0 ibm-pibs
  3. */
  4. #include <config.h>
  5. #include <asm/ppc4xx.h>
  6. #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
  7. #include <ppc_asm.tmpl>
  8. #include <ppc_defs.h>
  9. #include <asm/cache.h>
  10. #include <asm/mmu.h>
  11. /**
  12. * ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals
  13. *
  14. * IMPORTANT: For pass1 this code must run from cache since you can not
  15. * reliably change a peripheral banks timing register (pbxap) while running
  16. * code from that bank. For ex., since we are running from ROM on bank 0, we
  17. * can NOT execute the code that modifies bank 0 timings from ROM, so
  18. * we run it from cache.
  19. *
  20. * Bank 0 - Boot-Flash
  21. * Bank 1 - NAND-Flash
  22. * Bank 2 - ISA bus
  23. * Bank 3 - Second Flash
  24. * Bank 4 - USB controller
  25. */
  26. .globl ext_bus_cntlr_init
  27. ext_bus_cntlr_init:
  28. /*
  29. * We need the current boot up configuration to set correct
  30. * timings into internal flash and external flash
  31. */
  32. mfdcr r24,CPC0_PSR /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
  33. 0 0 -> 8 bit external ROM
  34. 0 1 -> 16 bit internal ROM */
  35. addi r4,0,2
  36. srw r24,r24,r4 /* shift right r24 two positions */
  37. andi. r24,r24,0x06000
  38. /*
  39. * All calculations are based on 33MHz EBC clock.
  40. *
  41. * First, create a "very slow" timing (~250ns) with burst mode enabled
  42. * This is need for the external flash access
  43. */
  44. lis r25,0x0800
  45. /* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280 */
  46. ori r25,r25,0x0280
  47. /*
  48. * Second, create a fast timing:
  49. * 90ns first cycle - 3 clock access
  50. * and 90ns burst cycle, plus 1 clock after the last access
  51. * This is used for the internal access
  52. */
  53. lis r26,0x8900
  54. /* 1000 1001 0xxx 0000 0000 0010 100x xxxx */
  55. ori r26,r26,0x0280
  56. /*
  57. * We can't change settings on CS# if we currently use them.
  58. * -> load a few instructions into cache and run this code from cache
  59. */
  60. mflr r4 /* save link register */
  61. bl ..getAddr
  62. ..getAddr:
  63. mflr r3 /* get address of ..getAddr */
  64. mtlr r4 /* restore link register */
  65. addi r4,0,14 /* set ctr to 10; used to prefetch */
  66. mtctr r4 /* 10 cache lines to fit this function
  67. in cache (gives us 8x10=80 instructions) */
  68. ..ebcloop:
  69. icbt r0,r3 /* prefetch cache line for addr in r3 */
  70. addi r3,r3,32 /* move to next cache line */
  71. bdnz ..ebcloop /* continue for 10 cache lines */
  72. /*
  73. * Delay to ensure all accesses to ROM are complete before changing
  74. * bank 0 timings. 200usec should be enough.
  75. * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
  76. */
  77. lis r3,0x0
  78. ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
  79. mtctr r3
  80. ..spinlp:
  81. bdnz ..spinlp /* spin loop */
  82. /*-----------------------------------------------------------------------
  83. * Memory Bank 0 (BOOT-ROM) initialization
  84. * 0xFFEF00000....0xFFFFFFF
  85. * We only have to change the timing. Mapping is ok by boot-strapping
  86. *----------------------------------------------------------------------- */
  87. li r4,PB1AP /* PB0AP=Peripheral Bank 0 Access Parameters */
  88. mtdcr EBC0_CFGADDR,r4
  89. mr r4,r26 /* assume internal fast flash is boot flash */
  90. cmpwi r24,0x2000 /* assumption true? ... */
  91. beq 1f /* ...yes! */
  92. mr r4,r25 /* ...no, use the slow variant */
  93. mr r25,r26 /* use this for the other flash */
  94. 1:
  95. mtdcr EBC0_CFGDATA,r4 /* change timing now */
  96. li r4,PB0CR /* PB0CR=Peripheral Bank 0 Control Register */
  97. mtdcr EBC0_CFGADDR,r4
  98. mfdcr r4,EBC0_CFGDATA
  99. lis r3,0x0001
  100. ori r3,r3,0x8000 /* allow reads and writes */
  101. or r4,r4,r3
  102. mtdcr EBC0_CFGDATA,r4
  103. /*-----------------------------------------------------------------------
  104. * Memory Bank 3 (Second-Flash) initialization
  105. * 0xF0000000...0xF01FFFFF -> 2MB
  106. *----------------------------------------------------------------------- */
  107. li r4,PB3AP /* Peripheral Bank 1 Access Parameter */
  108. mtdcr EBC0_CFGADDR,r4
  109. mtdcr EBC0_CFGDATA,r2 /* change timing */
  110. li r4,PB3CR /* Peripheral Bank 1 Configuration Registers */
  111. mtdcr EBC0_CFGADDR,r4
  112. lis r4,0xF003
  113. ori r4,r4,0x8000
  114. /*
  115. * Consider boot configuration
  116. */
  117. xori r24,r24,0x2000 /* invert current bus width */
  118. or r4,r4,r24
  119. mtdcr EBC0_CFGDATA,r4
  120. /*-----------------------------------------------------------------------
  121. * Memory Bank 1 (NAND-Flash) initialization
  122. * 0x77D00000...0x77DFFFFF -> 1MB
  123. * - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns
  124. * - the setup time is 0ns
  125. * - the hold time is 15ns
  126. * ->
  127. * - TWT = 0
  128. * - CSN = 0
  129. * - OEN = 0
  130. * - WBN = 0
  131. * - WBF = 0
  132. * - TH = 1
  133. * ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold)
  134. *----------------------------------------------------------------------- */
  135. li r4,PB1AP /* Peripheral Bank 1 Access Parameter */
  136. mtdcr EBC0_CFGADDR,r4
  137. lis r4,0x0000
  138. ori r4,r4,0x0200
  139. mtdcr EBC0_CFGDATA,r4
  140. li r4,PB1CR /* Peripheral Bank 1 Configuration Registers */
  141. mtdcr EBC0_CFGADDR,r4
  142. lis r4,0x77D1
  143. ori r4,r4,0x8000
  144. mtdcr EBC0_CFGDATA,r4
  145. /* USB init (without acceleration) */
  146. #ifndef CONFIG_ISP1161_PRESENT
  147. li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */
  148. mtdcr EBC0_CFGADDR,r4
  149. lis r4,0x0180
  150. ori r4,r4,0x5940
  151. mtdcr EBC0_CFGDATA,r4
  152. #endif
  153. /*-----------------------------------------------------------------------
  154. * Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7)
  155. * 0x78000000...0x7BFFFFFF -> 64 MB
  156. * Wir arbeiten bei 33 MHz -> 30ns
  157. *-----------------------------------------------------------------------
  158. A7 (ppc notation) or A24 (standard notation) decides about
  159. the type of access:
  160. A7/A24=0 -> memory cycle
  161. A7/ /A24=1 -> I/O cycle
  162. */
  163. li r4,PB2AP /* PB2AP=Peripheral Bank 2 Access Parameters */
  164. mtdcr EBC0_CFGADDR,r4
  165. /*
  166. We emulate an ISA access
  167. 1. Address active
  168. 2. wait 0 EBC clocks -> CSN=0
  169. 3. set CS#
  170. 4. wait 0 EBC clock -> OEN/WBN=0
  171. 5. set OE#/WE#
  172. 6. wait 4 clocks (ca. 90ns) and for Ready signal
  173. 7. hold for 4 clocks -> TH=4
  174. */
  175. #if 1
  176. /* faster access to isa-bus */
  177. lis r4,0x0180
  178. ori r4,r4,0x5940
  179. #else
  180. lis r4,0x0100
  181. ori r4,r4,0x0340
  182. #endif
  183. mtdcr EBC0_CFGDATA,r4
  184. #ifdef IDE_USES_ISA_EMULATION
  185. li r25,PB5AP /* PB5AP=Peripheral Bank 5 Access Parameters */
  186. mtdcr EBC0_CFGADDR,r25
  187. mtdcr EBC0_CFGDATA,r4
  188. #endif
  189. li r25,PB6AP /* PB6AP=Peripheral Bank 6 Access Parameters */
  190. mtdcr EBC0_CFGADDR,r25
  191. mtdcr EBC0_CFGDATA,r4
  192. li r25,PB7AP /* PB7AP=Peripheral Bank 7 Access Parameters */
  193. mtdcr EBC0_CFGADDR,r25
  194. mtdcr EBC0_CFGDATA,r4
  195. li r25,PB2CR /* PB2CR=Peripheral Bank 2 Configuration Register */
  196. mtdcr EBC0_CFGADDR,r25
  197. lis r4,0x780B
  198. ori r4,r4,0xA000
  199. mtdcr EBC0_CFGDATA,r4
  200. /*
  201. * the other areas are only 1MiB in size
  202. */
  203. lis r4,0x7401
  204. ori r4,r4,0xA000
  205. li r25,PB6CR /* PB6CR=Peripheral Bank 6 Configuration Register */
  206. mtdcr EBC0_CFGADDR,r25
  207. lis r4,0x7401
  208. ori r4,r4,0xA000
  209. mtdcr EBC0_CFGDATA,r4
  210. li r25,PB7CR /* PB7CR=Peripheral Bank 7 Configuration Register */
  211. mtdcr EBC0_CFGADDR,r25
  212. lis r4,0x7411
  213. ori r4,r4,0xA000
  214. mtdcr EBC0_CFGDATA,r4
  215. #ifndef CONFIG_ISP1161_PRESENT
  216. li r25,PB4CR /* PB4CR=Peripheral Bank 4 Configuration Register */
  217. mtdcr EBC0_CFGADDR,r25
  218. lis r4,0x7421
  219. ori r4,r4,0xA000
  220. mtdcr EBC0_CFGDATA,r4
  221. #endif
  222. #ifdef IDE_USES_ISA_EMULATION
  223. li r25,PB5CR /* PB5CR=Peripheral Bank 5 Configuration Register */
  224. mtdcr EBC0_CFGADDR,r25
  225. lis r4,0x0000
  226. ori r4,r4,0x0000
  227. mtdcr EBC0_CFGDATA,r4
  228. #endif
  229. /*-----------------------------------------------------------------------
  230. * Memory bank 4: USB controller Philips ISP6111
  231. * 0x77C00000 ... 0x77CFFFFF
  232. *
  233. * The chip is connected to:
  234. * - CPU CS#4
  235. * - CPU IRQ#2
  236. * - CPU DMA 3
  237. *
  238. * Timing:
  239. * - command to first data: 300ns. Software must ensure this timing!
  240. * - Write pulse: 26ns
  241. * - Read pulse: 33ns
  242. * - read cycle time: 150ns
  243. * - write cycle time: 140ns
  244. *
  245. * Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns
  246. *
  247. * |- 300ns --|
  248. * |---- 420ns ---|---- 420ns ---| cycle
  249. * CS ############:###____#######:###____#######
  250. * OE ############:####___#######:####___#######
  251. * WE ############:####__########:####__########
  252. *
  253. * ----> 2 clocks RD/WR pulses: 60ns
  254. * ----> CSN: 3 clock, 90ns
  255. * ----> OEN: 1 clocks (read cycle)
  256. * ----> WBN: 1 clocks (write cycle)
  257. * ----> WBE: 2 clocks
  258. * ----> TH: 7 clock, 210ns
  259. * ----> TWT: 7 clocks
  260. *----------------------------------------------------------------------- */
  261. #ifdef CONFIG_ISP1161_PRESENT
  262. li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */
  263. mtdcr EBC0_CFGADDR,r4
  264. lis r4,0x030D
  265. ori r4,r4,0x5E80
  266. mtdcr EBC0_CFGDATA,r4
  267. li r4,PB4CR /* PB2CR=Peripheral Bank 4 Configuration Register */
  268. mtdcr EBC0_CFGADDR,r4
  269. lis r4,0x77C1
  270. ori r4,r4,0xA000
  271. mtdcr EBC0_CFGDATA,r4
  272. #endif
  273. #ifndef IDE_USES_ISA_EMULATION
  274. /*-----------------------------------------------------------------------
  275. * Memory Bank 5 used for IDE access
  276. *
  277. * Timings for IDE Interface
  278. *
  279. * SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time
  280. * 70 165 30 PIO-Mode 0, [ns]
  281. * 3 6 1 [Cycles] ----> AP=0x040C0200
  282. * 50 125 20 PIO-Mode 1, [ns]
  283. * 2 5 1 [Cycles] ----> AP=0x03080200
  284. * 30 100 15 PIO-Mode 2, [ns]
  285. * 1 4 1 [Cycles] ----> AP=0x02040200
  286. * 30 80 10 PIO-Mode 3, [ns]
  287. * 1 3 1 [Cycles] ----> AP=0x01840200
  288. * 25 70 10 PIO-Mode 4, [ns]
  289. * 1 3 1 [Cycles] ----> AP=0x01840200
  290. *
  291. *----------------------------------------------------------------------- */
  292. li r4,PB5AP
  293. mtdcr EBC0_CFGADDR,r4
  294. lis r4,0x040C
  295. ori r4,r4,0x0200
  296. mtdcr EBC0_CFGDATA,r4
  297. li r4,PB5CR /* PB2CR=Peripheral Bank 2 Configuration Register */
  298. mtdcr EBC0_CFGADDR,r4
  299. lis r4,0x7A01
  300. ori r4,r4,0xA000
  301. mtdcr EBC0_CFGDATA,r4
  302. #endif
  303. /*
  304. * External Peripheral Control Register
  305. */
  306. li r4,EBC0_CFG
  307. mtdcr EBC0_CFGADDR,r4
  308. lis r4,0xB84E
  309. ori r4,r4,0xF000
  310. mtdcr EBC0_CFGDATA,r4
  311. /*
  312. * drive POST code
  313. */
  314. lis r4,0x7900
  315. ori r4,r4,0x0080
  316. li r3,0x0001
  317. stb r3,0(r4) /* 01 -> external bus controller is initialized */
  318. nop /* pass2 DCR errata #8 */
  319. blr