init.S 2.8 KB

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  1. /*
  2. * SPDX-License-Identifier: GPL-2.0 ibm-pibs
  3. */
  4. /*------------------------------------------------------------------------- */
  5. /* Function: ext_bus_cntlr_init */
  6. /* Description: Initializes the External Bus Controller for the external */
  7. /* peripherals. IMPORTANT: For pass1 this code must run from */
  8. /* cache since you can not reliably change a peripheral banks */
  9. /* timing register (pbxap) while running code from that bank. */
  10. /* For ex., since we are running from ROM on bank 0, we can NOT */
  11. /* execute the code that modifies bank 0 timings from ROM, so */
  12. /* we run it from cache. */
  13. /* */
  14. /* */
  15. /* The layout for the PEI JSE board: */
  16. /* Bank 0 - Flash and SRAM */
  17. /* Bank 1 - SystemACE */
  18. /* Bank 2 - not used */
  19. /* Bank 3 - not used */
  20. /* Bank 4 - not used */
  21. /* Bank 5 - not used */
  22. /* Bank 6 - not used */
  23. /* Bank 7 - not used */
  24. /*------------------------------------------------------------------------- */
  25. #include <asm/ppc4xx.h>
  26. #include <ppc_asm.tmpl>
  27. #include <ppc_defs.h>
  28. #include <asm/cache.h>
  29. #include <asm/mmu.h>
  30. .globl ext_bus_cntlr_init
  31. ext_bus_cntlr_init:
  32. mflr r4 /* save link register */
  33. bl ..getAddr
  34. ..getAddr:
  35. mflr r3 /* get address of ..getAddr */
  36. mtlr r4 /* restore link register */
  37. addi r4,0,14 /* set ctr to 10; used to prefetch */
  38. mtctr r4 /* 10 cache lines to fit this function */
  39. /* in cache (gives us 8x10=80 instrctns) */
  40. ..ebcloop:
  41. icbt r0,r3 /* prefetch cache line for addr in r3 */
  42. addi r3,r3,32 /* move to next cache line */
  43. bdnz ..ebcloop /* continue for 10 cache lines */
  44. /*----------------------------------------------------------------- */
  45. /* Delay to ensure all accesses to ROM are complete before changing */
  46. /* bank 0 timings. 200usec should be enough. */
  47. /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
  48. /*----------------------------------------------------------------- */
  49. addis r3,0,0x0
  50. ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
  51. mtctr r3
  52. ..spinlp:
  53. bdnz ..spinlp /* spin loop */
  54. /*----------------------------------------------------------------- */
  55. /* Memory Bank 0 (Flash) initialization */
  56. /*----------------------------------------------------------------- */
  57. addi r4,0,PB1AP
  58. mtdcr EBC0_CFGADDR,r4
  59. addis r4,0,0x9B01
  60. ori r4,r4,0x5480
  61. mtdcr EBC0_CFGDATA,r4
  62. addi r4,0,PB0CR
  63. mtdcr EBC0_CFGADDR,r4
  64. addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
  65. ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
  66. mtdcr EBC0_CFGDATA,r4
  67. blr