writeibm.S 3.8 KB

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  1. /*
  2. * SPDX-License-Identifier: GPL-2.0 ibm-pibs
  3. */
  4. /*----------------------------------------------------------------------------- */
  5. /* Function: ext_bus_cntlr_init */
  6. /* Description: Initializes the External Bus Controller for the external */
  7. /* peripherals. IMPORTANT: For pass1 this code must run from */
  8. /* cache since you can not reliably change a peripheral banks */
  9. /* timing register (pbxap) while running code from that bank. */
  10. /* For ex., since we are running from ROM on bank 0, we can NOT */
  11. /* execute the code that modifies bank 0 timings from ROM, so */
  12. /* we run it from cache. */
  13. /* Bank 0 - Flash and SRAM */
  14. /* Bank 1 - NVRAM/RTC */
  15. /* Bank 2 - Keyboard/Mouse controller */
  16. /* Bank 3 - IR controller */
  17. /* Bank 4 - not used */
  18. /* Bank 5 - not used */
  19. /* Bank 6 - not used */
  20. /* Bank 7 - FPGA registers */
  21. /*----------------------------------------------------------------------------- */
  22. #include <asm/ppc4xx.h>
  23. #include <ppc_asm.tmpl>
  24. #include <ppc_defs.h>
  25. #include <asm/cache.h>
  26. #include <asm/mmu.h>
  27. .globl write_without_sync
  28. write_without_sync:
  29. /*
  30. * Write one values to host via pci busmastering
  31. * ptr = 0xc0000000 -> 0x01000000 (PCI)
  32. * *ptr = 0x01234567;
  33. */
  34. addi r31,0,0
  35. lis r31,0xc000
  36. start1:
  37. lis r0,0x0123
  38. ori r0,r0,0x4567
  39. stw r0,0(r31)
  40. /*
  41. * Read one value back
  42. * ptr = (volatile unsigned long *)addr;
  43. * val = *ptr;
  44. */
  45. lwz r0,0(r31)
  46. /*
  47. * One pci config write
  48. * ibmPciConfigWrite(0x2e, 2, 0x1234);
  49. */
  50. /* subsystem id */
  51. li r4,0x002C
  52. oris r4,r4,0x8000
  53. lis r3,0xEEC0
  54. stwbrx r4,0,r3
  55. li r5,0x1234
  56. ori r3,r3,0x4
  57. stwbrx r5,0,r3
  58. b start1
  59. blr /* never reached !!!! */
  60. .globl write_with_sync
  61. write_with_sync:
  62. /*
  63. * Write one values to host via pci busmastering
  64. * ptr = 0xc0000000 -> 0x01000000 (PCI)
  65. * *ptr = 0x01234567;
  66. */
  67. addi r31,0,0
  68. lis r31,0xc000
  69. start2:
  70. lis r0,0x0123
  71. ori r0,r0,0x4567
  72. stw r0,0(r31)
  73. /*
  74. * Read one value back
  75. * ptr = (volatile unsigned long *)addr;
  76. * val = *ptr;
  77. */
  78. lwz r0,0(r31)
  79. /*
  80. * One pci config write
  81. * ibmPciConfigWrite(0x2e, 2, 0x1234);
  82. */
  83. /* subsystem id */
  84. li r4,0x002C
  85. oris r4,r4,0x8000
  86. lis r3,0xEEC0
  87. stwbrx r4,0,r3
  88. sync
  89. li r5,0x1234
  90. ori r3,r3,0x4
  91. stwbrx r5,0,r3
  92. sync
  93. b start2
  94. blr /* never reached !!!! */
  95. .globl write_with_less_sync
  96. write_with_less_sync:
  97. /*
  98. * Write one values to host via pci busmastering
  99. * ptr = 0xc0000000 -> 0x01000000 (PCI)
  100. * *ptr = 0x01234567;
  101. */
  102. addi r31,0,0
  103. lis r31,0xc000
  104. start2b:
  105. lis r0,0x0123
  106. ori r0,r0,0x4567
  107. stw r0,0(r31)
  108. /*
  109. * Read one value back
  110. * ptr = (volatile unsigned long *)addr;
  111. * val = *ptr;
  112. */
  113. lwz r0,0(r31)
  114. /*
  115. * One pci config write
  116. * ibmPciConfigWrite(0x2e, 2, 0x1234);
  117. */
  118. /* subsystem id */
  119. li r4,0x002C
  120. oris r4,r4,0x8000
  121. lis r3,0xEEC0
  122. stwbrx r4,0,r3
  123. sync
  124. li r5,0x1234
  125. ori r3,r3,0x4
  126. stwbrx r5,0,r3
  127. /* sync */
  128. b start2b
  129. blr /* never reached !!!! */
  130. .globl write_with_more_sync
  131. write_with_more_sync:
  132. /*
  133. * Write one values to host via pci busmastering
  134. * ptr = 0xc0000000 -> 0x01000000 (PCI)
  135. * *ptr = 0x01234567;
  136. */
  137. addi r31,0,0
  138. lis r31,0xc000
  139. start3:
  140. lis r0,0x0123
  141. ori r0,r0,0x4567
  142. stw r0,0(r31)
  143. sync
  144. /*
  145. * Read one value back
  146. * ptr = (volatile unsigned long *)addr;
  147. * val = *ptr;
  148. */
  149. lwz r0,0(r31)
  150. sync
  151. /*
  152. * One pci config write
  153. * ibmPciConfigWrite(0x2e, 2, 0x1234);
  154. */
  155. /* subsystem id (PCIC0_SBSYSVID)*/
  156. li r4,0x002C
  157. oris r4,r4,0x8000
  158. lis r3,0xEEC0
  159. stwbrx r4,0,r3
  160. sync
  161. li r5,0x1234
  162. ori r3,r3,0x4
  163. stwbrx r5,0,r3
  164. sync
  165. b start3
  166. blr /* never reached !!!! */