init.S 6.1 KB

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  1. /*
  2. * SPDX-License-Identifier: GPL-2.0 ibm-pibs
  3. */
  4. #include <config.h>
  5. #include <asm/ppc4xx.h>
  6. #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
  7. #include <ppc_asm.tmpl>
  8. #include <ppc_defs.h>
  9. #include <asm/cache.h>
  10. #include <asm/mmu.h>
  11. #define LI32(reg,val) \
  12. addis reg,0,val@h;\
  13. ori reg,reg,val@l
  14. #define WDCR_EBC(reg,val) \
  15. addi r4,0,reg;\
  16. mtdcr EBC0_CFGADDR,r4;\
  17. addis r4,0,val@h;\
  18. ori r4,r4,val@l;\
  19. mtdcr EBC0_CFGDATA,r4
  20. #define WDCR_SDRAM(reg,val) \
  21. addi r4,0,reg;\
  22. mtdcr SDRAM0_CFGADDR,r4;\
  23. addis r4,0,val@h;\
  24. ori r4,r4,val@l;\
  25. mtdcr SDRAM0_CFGDATA,r4
  26. /******************************************************************************
  27. * Function: ext_bus_cntlr_init
  28. *
  29. * Description: Configures EBC Controller and a few basic chip selects.
  30. *
  31. * CS0 is setup to get the Boot Flash out of the addresss range
  32. * so that we may setup a stack. CS7 is setup so that we can
  33. * access and reset the hardware watchdog.
  34. *
  35. * IMPORTANT: For pass1 this code must run from
  36. * cache since you can not reliably change a peripheral banks
  37. * timing register (pbxap) while running code from that bank.
  38. * For ex., since we are running from ROM on bank 0, we can NOT
  39. * execute the code that modifies bank 0 timings from ROM, so
  40. * we run it from cache.
  41. *
  42. * Notes: Does NOT use the stack.
  43. *****************************************************************************/
  44. .section ".text"
  45. .align 2
  46. .globl ext_bus_cntlr_init
  47. .type ext_bus_cntlr_init, @function
  48. ext_bus_cntlr_init:
  49. mflr r0
  50. /********************************************************************
  51. * Prefetch entire ext_bus_cntrl_init function into the icache.
  52. * This is necessary because we are going to change the same CS we
  53. * are executing from. Otherwise a CPU lockup may occur.
  54. *******************************************************************/
  55. bl ..getAddr
  56. ..getAddr:
  57. mflr r3 /* get address of ..getAddr */
  58. /* Calculate number of cache lines for this function */
  59. addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
  60. mtctr r4
  61. ..ebcloop:
  62. icbt r0, r3 /* prefetch cache line for addr in r3*/
  63. addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
  64. bdnz ..ebcloop /* continue for $CTR cache lines */
  65. /********************************************************************
  66. * Delay to ensure all accesses to ROM are complete before changing
  67. * bank 0 timings. 200usec should be enough.
  68. * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
  69. *******************************************************************/
  70. addis r3, 0, 0x0
  71. ori r3, r3, 0xA000 /* wait 200us from reset */
  72. mtctr r3
  73. ..spinlp:
  74. bdnz ..spinlp /* spin loop */
  75. /********************************************************************
  76. * SETUP CPC0_CR0
  77. *******************************************************************/
  78. LI32(r4, 0x00c01030)
  79. mtdcr CPC0_CR0, r4
  80. /********************************************************************
  81. * Setup CPC0_CR1: Change PCIINT signal to PerWE
  82. *******************************************************************/
  83. mfdcr r4, CPC0_CR1
  84. ori r4, r4, 0x4000
  85. mtdcr CPC0_CR1, r4
  86. /********************************************************************
  87. * Setup External Bus Controller (EBC).
  88. *******************************************************************/
  89. WDCR_EBC(EBC0_CFG, 0xd84c0000)
  90. /********************************************************************
  91. * Memory Bank 0 (Intel 28F640J3 Flash) initialization
  92. *******************************************************************/
  93. /*WDCR_EBC(PB1AP, 0x03055200)*/
  94. /*WDCR_EBC(PB1AP, 0x04055200)*/
  95. WDCR_EBC(PB1AP, 0x08055200)
  96. WDCR_EBC(PB0CR, 0xff87a000)
  97. /********************************************************************
  98. * Memory Bank 3 (Xilinx XC95144 CPLD) initialization
  99. *******************************************************************/
  100. /*WDCR_EBC(PB3AP, 0x07869200)*/
  101. WDCR_EBC(PB3AP, 0x04055200)
  102. WDCR_EBC(PB3CR, 0xf081c000)
  103. /********************************************************************
  104. * Memory Bank 1,2,4-7 (Unused) initialization
  105. *******************************************************************/
  106. WDCR_EBC(PB1AP, 0)
  107. WDCR_EBC(PB1CR, 0)
  108. WDCR_EBC(PB2AP, 0)
  109. WDCR_EBC(PB2CR, 0)
  110. WDCR_EBC(PB4AP, 0)
  111. WDCR_EBC(PB4CR, 0)
  112. WDCR_EBC(PB5AP, 0)
  113. WDCR_EBC(PB5CR, 0)
  114. WDCR_EBC(PB6AP, 0)
  115. WDCR_EBC(PB6CR, 0)
  116. WDCR_EBC(PB7AP, 0)
  117. WDCR_EBC(PB7CR, 0)
  118. /* We are all done */
  119. mtlr r0 /* Restore link register */
  120. blr /* Return to calling function */
  121. .Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
  122. /* end ext_bus_cntlr_init() */
  123. /******************************************************************************
  124. * Function: sdram_init
  125. *
  126. * Description: Configures SDRAM memory banks.
  127. *
  128. * Notes: Does NOT use the stack.
  129. *****************************************************************************/
  130. .section ".text"
  131. .align 2
  132. .globl sdram_init
  133. .type sdram_init, @function
  134. sdram_init:
  135. /*
  136. * Disable memory controller to allow
  137. * values to be changed.
  138. */
  139. WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
  140. /*
  141. * Configure Memory Banks
  142. */
  143. WDCR_SDRAM(SDRAM0_B0CR, 0x00062001)
  144. WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
  145. WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
  146. WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
  147. /*
  148. * Set up SDTR1 (SDRAM Timing Register)
  149. */
  150. WDCR_SDRAM(SDRAM0_TR, 0x00854009)
  151. /*
  152. * Set RTR (Refresh Timing Register)
  153. */
  154. WDCR_SDRAM(SDRAM0_RTR, 0x10000000)
  155. /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */
  156. /********************************************************************
  157. * Delay to ensure 200usec have elapsed since reset. Assume worst
  158. * case that the core is running 200Mhz:
  159. * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
  160. *******************************************************************/
  161. addis r3, 0, 0x0000
  162. ori r3, r3, 0xA000 /* Wait >200us from reset */
  163. mtctr r3
  164. ..spinlp2:
  165. bdnz ..spinlp2 /* spin loop */
  166. /********************************************************************
  167. * Set memory controller options reg, MCOPT1.
  168. *******************************************************************/
  169. WDCR_SDRAM(SDRAM0_CFG,0x80800000)
  170. ..sdri_done:
  171. blr /* Return to calling function */
  172. .Lfe1: .size sdram_init,.Lfe1-sdram_init
  173. /* end sdram_init() */