init.S 4.4 KB

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  1. /*
  2. * SPDX-License-Identifier: GPL-2.0 ibm-pibs
  3. */
  4. /*----------------------------------------------------------------------------- */
  5. /* Function: ext_bus_cntlr_init */
  6. /* Description: Initializes the External Bus Controller for the external */
  7. /* peripherals. IMPORTANT: For pass1 this code must run from */
  8. /* cache since you can not reliably change a peripheral banks */
  9. /* timing register (pbxap) while running code from that bank. */
  10. /* For ex., since we are running from ROM on bank 0, we can NOT */
  11. /* execute the code that modifies bank 0 timings from ROM, so */
  12. /* we run it from cache. */
  13. /* Bank 0 - Flash and SRAM */
  14. /* Bank 1 - NVRAM/RTC */
  15. /* Bank 2 - Keyboard/Mouse controller */
  16. /* Bank 3 - IR controller */
  17. /* Bank 4 - not used */
  18. /* Bank 5 - not used */
  19. /* Bank 6 - not used */
  20. /* Bank 7 - FPGA registers */
  21. /*-----------------------------------------------------------------------------#include <config.h> */
  22. #include <asm/ppc4xx.h>
  23. #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
  24. #include <ppc_asm.tmpl>
  25. #include <ppc_defs.h>
  26. #include <asm/cache.h>
  27. #include <asm/mmu.h>
  28. /* CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty */
  29. /* except for #1 which we use for DMA'ing to IOCA-like things, so the */
  30. /* control registers to set that up are determined by what we've */
  31. /* empirically discovered work there. */
  32. .globl ext_bus_cntlr_init
  33. ext_bus_cntlr_init:
  34. mflr r4 /* save link register */
  35. bl ..getAddr
  36. ..getAddr:
  37. mflr r3 /* get address of ..getAddr */
  38. mtlr r4 /* restore link register */
  39. addi r4,0,14 /* set ctr to 10; used to prefetch */
  40. mtctr r4 /* 10 cache lines to fit this function */
  41. /* in cache (gives us 8x10=80 instrctns) */
  42. ..ebcloop:
  43. icbt r0,r3 /* prefetch cache line for addr in r3 */
  44. addi r3,r3,32 /* move to next cache line */
  45. bdnz ..ebcloop /* continue for 10 cache lines */
  46. /*------------------------------------------------------------------- */
  47. /* Delay to ensure all accesses to ROM are complete before changing */
  48. /* bank 0 timings. 200usec should be enough. */
  49. /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
  50. /*------------------------------------------------------------------- */
  51. addis r3,0,0x0
  52. ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
  53. mtctr r3
  54. ..spinlp:
  55. bdnz ..spinlp /* spin loop */
  56. /*---------------------------------------------------------------------- */
  57. /* Peripheral Bank 0 (Flash) initialization */
  58. /*---------------------------------------------------------------------- */
  59. /* 0x7F8FFE80 slowest boot */
  60. addi r4,0,PB1AP
  61. mtdcr EBC0_CFGADDR,r4
  62. addis r4,0,0x9B01
  63. ori r4,r4,0x5480
  64. mtdcr EBC0_CFGDATA,r4
  65. addi r4,0,PB0CR
  66. mtdcr EBC0_CFGADDR,r4
  67. addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */
  68. ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
  69. mtdcr EBC0_CFGDATA,r4
  70. blr
  71. /*---------------------------------------------------------------------- */
  72. /* Peripheral Bank 1 (NVRAM/RTC) initialization */
  73. /* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */
  74. /* and we do DMA on it. The ConfigurationRegister part is threfore */
  75. /* almost arbitrary, except that our linux driver needs to know the */
  76. /* address, but it can query, it.. */
  77. /* */
  78. /* The AccessParameter is CRITICAL, */
  79. /* thouch, since it needs to agree with the electrical timings on the */
  80. /* IOCA parallel interface. That value is: 0x0185,4380 */
  81. /* BurstModeEnable BME=0 */
  82. /* TransferWait TWT=3 */
  83. /* ChipSelectOnTiming CSN=1 */
  84. /* OutputEnableOnTimimg OEN=1 */
  85. /* WriteByteEnableOnTiming WBN=1 */
  86. /* WriteByteEnableOffTiming WBF=0 */
  87. /* TransferHold TH=1 */
  88. /* ReadyEnable RE=1 */
  89. /* SampleOnReady SOR=1 */
  90. /* ByteEnableMode BEM=0 */
  91. /* ParityEnable PEN=0 */
  92. /* all reserved bits=0 */
  93. /*---------------------------------------------------------------------- */
  94. /*---------------------------------------------------------------------- */
  95. addi r4,0,PB1AP
  96. mtdcr EBC0_CFGADDR,r4
  97. addis r4,0,0x0185 /* hiword */
  98. ori r4,r4,0x4380 /* loword */
  99. mtdcr EBC0_CFGDATA,r4
  100. addi r4,0,PB1CR
  101. mtdcr EBC0_CFGADDR,r4
  102. addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */
  103. ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
  104. mtdcr EBC0_CFGDATA,r4
  105. blr