ppc4xx.h 8.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305
  1. /*
  2. * SPDX-License-Identifier: GPL-2.0 ibm-pibs
  3. */
  4. #ifndef __PPC4XX_H__
  5. #define __PPC4XX_H__
  6. /*
  7. * Include SoC specific headers
  8. */
  9. #if defined(CONFIG_405CR)
  10. #include <asm/ppc405cr.h>
  11. #endif
  12. #if defined(CONFIG_405EP)
  13. #include <asm/ppc405ep.h>
  14. #endif
  15. #if defined(CONFIG_405EX)
  16. #include <asm/ppc405ex.h>
  17. #endif
  18. #if defined(CONFIG_405EZ)
  19. #include <asm/ppc405ez.h>
  20. #endif
  21. #if defined(CONFIG_405GP)
  22. #include <asm/ppc405gp.h>
  23. #endif
  24. #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
  25. #include <asm/ppc440ep_gr.h>
  26. #endif
  27. #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  28. #include <asm/ppc440epx_grx.h>
  29. #endif
  30. #if defined(CONFIG_440GP)
  31. #include <asm/ppc440gp.h>
  32. #endif
  33. #if defined(CONFIG_440GX)
  34. #include <asm/ppc440gx.h>
  35. #endif
  36. #if defined(CONFIG_440SP)
  37. #include <asm/ppc440sp.h>
  38. #endif
  39. #if defined(CONFIG_440SPE)
  40. #include <asm/ppc440spe.h>
  41. #endif
  42. #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  43. #include <asm/ppc460ex_gt.h>
  44. #endif
  45. #if defined(CONFIG_460SX)
  46. #include <asm/ppc460sx.h>
  47. #endif
  48. #if defined(CONFIG_APM821XX)
  49. #include <asm/apm821xx.h>
  50. #endif
  51. /*
  52. * Common registers for all SoC's
  53. */
  54. /* DCR registers */
  55. #define PLB3A0_ACR 0x0077
  56. #define PLB4A0_ACR 0x0081
  57. #define PLB4A1_ACR 0x0089
  58. /* CPR register declarations */
  59. #define PLB4Ax_ACR_PPM_MASK 0xf0000000
  60. #define PLB4Ax_ACR_PPM_FIXED 0x00000000
  61. #define PLB4Ax_ACR_PPM_FAIR 0xd0000000
  62. #define PLB4Ax_ACR_HBU_MASK 0x08000000
  63. #define PLB4Ax_ACR_HBU_DISABLED 0x00000000
  64. #define PLB4Ax_ACR_HBU_ENABLED 0x08000000
  65. #define PLB4Ax_ACR_RDP_MASK 0x06000000
  66. #define PLB4Ax_ACR_RDP_DISABLED 0x00000000
  67. #define PLB4Ax_ACR_RDP_2DEEP 0x02000000
  68. #define PLB4Ax_ACR_RDP_3DEEP 0x04000000
  69. #define PLB4Ax_ACR_RDP_4DEEP 0x06000000
  70. #define PLB4Ax_ACR_WRP_MASK 0x01000000
  71. #define PLB4Ax_ACR_WRP_DISABLED 0x00000000
  72. #define PLB4Ax_ACR_WRP_2DEEP 0x01000000
  73. /*
  74. * External Bus Controller
  75. */
  76. /* Values for EBC0_CFGADDR register - indirect addressing of these regs */
  77. #define PB0CR 0x00 /* periph bank 0 config reg */
  78. #define PB1CR 0x01 /* periph bank 1 config reg */
  79. #define PB2CR 0x02 /* periph bank 2 config reg */
  80. #define PB3CR 0x03 /* periph bank 3 config reg */
  81. #define PB4CR 0x04 /* periph bank 4 config reg */
  82. #define PB5CR 0x05 /* periph bank 5 config reg */
  83. #define PB6CR 0x06 /* periph bank 6 config reg */
  84. #define PB7CR 0x07 /* periph bank 7 config reg */
  85. #define PB0AP 0x10 /* periph bank 0 access parameters */
  86. #define PB1AP 0x11 /* periph bank 1 access parameters */
  87. #define PB2AP 0x12 /* periph bank 2 access parameters */
  88. #define PB3AP 0x13 /* periph bank 3 access parameters */
  89. #define PB4AP 0x14 /* periph bank 4 access parameters */
  90. #define PB5AP 0x15 /* periph bank 5 access parameters */
  91. #define PB6AP 0x16 /* periph bank 6 access parameters */
  92. #define PB7AP 0x17 /* periph bank 7 access parameters */
  93. #define PBEAR 0x20 /* periph bus error addr reg */
  94. #define PBESR0 0x21 /* periph bus error status reg 0 */
  95. #define PBESR1 0x22 /* periph bus error status reg 1 */
  96. #define EBC0_CFG 0x23 /* external bus configuration reg */
  97. /*
  98. * GPIO macro register defines
  99. */
  100. /* todo: merge with gpio.h header */
  101. #define GPIO_BASE GPIO0_BASE
  102. #define GPIO0_OR (GPIO0_BASE + 0x0)
  103. #define GPIO0_TCR (GPIO0_BASE + 0x4)
  104. #define GPIO0_OSRL (GPIO0_BASE + 0x8)
  105. #define GPIO0_OSRH (GPIO0_BASE + 0xC)
  106. #define GPIO0_TSRL (GPIO0_BASE + 0x10)
  107. #define GPIO0_TSRH (GPIO0_BASE + 0x14)
  108. #define GPIO0_ODR (GPIO0_BASE + 0x18)
  109. #define GPIO0_IR (GPIO0_BASE + 0x1C)
  110. #define GPIO0_RR1 (GPIO0_BASE + 0x20)
  111. #define GPIO0_RR2 (GPIO0_BASE + 0x24)
  112. #define GPIO0_RR3 (GPIO0_BASE + 0x28)
  113. #define GPIO0_ISR1L (GPIO0_BASE + 0x30)
  114. #define GPIO0_ISR1H (GPIO0_BASE + 0x34)
  115. #define GPIO0_ISR2L (GPIO0_BASE + 0x38)
  116. #define GPIO0_ISR2H (GPIO0_BASE + 0x3C)
  117. #define GPIO0_ISR3L (GPIO0_BASE + 0x40)
  118. #define GPIO0_ISR3H (GPIO0_BASE + 0x44)
  119. #define GPIO1_OR (GPIO1_BASE + 0x0)
  120. #define GPIO1_TCR (GPIO1_BASE + 0x4)
  121. #define GPIO1_OSRL (GPIO1_BASE + 0x8)
  122. #define GPIO1_OSRH (GPIO1_BASE + 0xC)
  123. #define GPIO1_TSRL (GPIO1_BASE + 0x10)
  124. #define GPIO1_TSRH (GPIO1_BASE + 0x14)
  125. #define GPIO1_ODR (GPIO1_BASE + 0x18)
  126. #define GPIO1_IR (GPIO1_BASE + 0x1C)
  127. #define GPIO1_RR1 (GPIO1_BASE + 0x20)
  128. #define GPIO1_RR2 (GPIO1_BASE + 0x24)
  129. #define GPIO1_RR3 (GPIO1_BASE + 0x28)
  130. #define GPIO1_ISR1L (GPIO1_BASE + 0x30)
  131. #define GPIO1_ISR1H (GPIO1_BASE + 0x34)
  132. #define GPIO1_ISR2L (GPIO1_BASE + 0x38)
  133. #define GPIO1_ISR2H (GPIO1_BASE + 0x3C)
  134. #define GPIO1_ISR3L (GPIO1_BASE + 0x40)
  135. #define GPIO1_ISR3H (GPIO1_BASE + 0x44)
  136. /* General Purpose Timer (GPT) Register Offsets */
  137. #define GPT0_TBC 0x00000000
  138. #define GPT0_IM 0x00000018
  139. #define GPT0_ISS 0x0000001C
  140. #define GPT0_ISC 0x00000020
  141. #define GPT0_IE 0x00000024
  142. #define GPT0_COMP0 0x00000080
  143. #define GPT0_COMP1 0x00000084
  144. #define GPT0_COMP2 0x00000088
  145. #define GPT0_COMP3 0x0000008C
  146. #define GPT0_COMP4 0x00000090
  147. #define GPT0_COMP5 0x00000094
  148. #define GPT0_COMP6 0x00000098
  149. #define GPT0_MASK0 0x000000C0
  150. #define GPT0_MASK1 0x000000C4
  151. #define GPT0_MASK2 0x000000C8
  152. #define GPT0_MASK3 0x000000CC
  153. #define GPT0_MASK4 0x000000D0
  154. #define GPT0_MASK5 0x000000D4
  155. #define GPT0_MASK6 0x000000D8
  156. #define GPT0_DCT0 0x00000110
  157. #define GPT0_DCIS 0x0000011C
  158. #if defined(CONFIG_440)
  159. #include <asm/ppc440.h>
  160. #else
  161. #include <asm/ppc405.h>
  162. #endif
  163. #include <asm/ppc4xx-sdram.h>
  164. #include <asm/ppc4xx-ebc.h>
  165. #if !defined(CONFIG_XILINX_440)
  166. #include <asm/ppc4xx-uic.h>
  167. #endif
  168. /*
  169. * Macro for generating register field mnemonics
  170. */
  171. #define PPC_REG_BITS 32
  172. #define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
  173. /*
  174. * Elide casts when assembling register mnemonics
  175. */
  176. #ifndef __ASSEMBLY__
  177. #define static_cast(type, val) (type)(val)
  178. #else
  179. #define static_cast(type, val) (val)
  180. #endif
  181. /*
  182. * Common stuff for 4xx (405 and 440)
  183. */
  184. #define EXC_OFF_SYS_RESET 0x0100 /* System reset */
  185. #define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
  186. #define RESET_VECTOR 0xfffffffc
  187. #define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for
  188. cache line aligned data. */
  189. #define CPR0_DCR_BASE 0x0C
  190. #define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0)
  191. #define CPR0_CFGDATA (CPR0_DCR_BASE + 0x1)
  192. #define SDR_DCR_BASE 0x0E
  193. #define SDR0_CFGADDR (SDR_DCR_BASE + 0x0)
  194. #define SDR0_CFGDATA (SDR_DCR_BASE + 0x1)
  195. #define SDRAM_DCR_BASE 0x10
  196. #define SDRAM0_CFGADDR (SDRAM_DCR_BASE + 0x0)
  197. #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1)
  198. #define EBC_DCR_BASE 0x12
  199. #define EBC0_CFGADDR (EBC_DCR_BASE + 0x0)
  200. #define EBC0_CFGDATA (EBC_DCR_BASE + 0x1)
  201. /*
  202. * Macros for indirect DCR access
  203. */
  204. #define mtcpr(reg, d) \
  205. do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0)
  206. #define mfcpr(reg, d) \
  207. do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0)
  208. #define mtebc(reg, d) \
  209. do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0)
  210. #define mfebc(reg, d) \
  211. do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0)
  212. #define mtsdram(reg, d) \
  213. do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
  214. #define mfsdram(reg, d) \
  215. do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
  216. #define mtsdr(reg, d) \
  217. do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0)
  218. #define mfsdr(reg, d) \
  219. do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0)
  220. #ifndef __ASSEMBLY__
  221. typedef struct
  222. {
  223. unsigned long freqDDR;
  224. unsigned long freqEBC;
  225. unsigned long freqOPB;
  226. unsigned long freqPCI;
  227. unsigned long freqPLB;
  228. unsigned long freqTmrClk;
  229. unsigned long freqUART;
  230. unsigned long freqProcessor;
  231. unsigned long freqVCOHz;
  232. unsigned long freqVCOMhz; /* in MHz */
  233. unsigned long pciClkSync; /* PCI clock is synchronous */
  234. unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
  235. unsigned long pllExtBusDiv;
  236. unsigned long pllFbkDiv;
  237. unsigned long pllFwdDiv;
  238. unsigned long pllFwdDivA;
  239. unsigned long pllFwdDivB;
  240. unsigned long pllOpbDiv;
  241. unsigned long pllPciDiv;
  242. unsigned long pllPlbDiv;
  243. } PPC4xx_SYS_INFO;
  244. static inline u32 get_mcsr(void)
  245. {
  246. u32 val;
  247. asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
  248. return val;
  249. }
  250. static inline void set_mcsr(u32 val)
  251. {
  252. asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
  253. }
  254. int ppc4xx_pci_sync_clock_config(u32 async);
  255. #endif /* __ASSEMBLY__ */
  256. /* for multi-cpu support */
  257. #define NA_OR_UNKNOWN_CPU -1
  258. #endif /* __PPC4XX_H__ */