ppc4xx-mal.h 5.9 KB

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  1. /* include/mal.h, openbios_walnut, walnut_bios 8/6/99 08:48:40 */
  2. /*
  3. * SPDX-License-Identifier: GPL-2.0 ibm-pibs
  4. */
  5. /*----------------------------------------------------------------------------+
  6. |
  7. | File Name: mal.h
  8. |
  9. | Function: Header file for the MAL (MADMAL) macro on the 405GP.
  10. |
  11. | Author: Mark Wisner
  12. |
  13. | Change Activity-
  14. |
  15. | Date Description of Change BY
  16. | --------- --------------------- ---
  17. | 29-Apr-99 Created MKW
  18. |
  19. +----------------------------------------------------------------------------*/
  20. /*----------------------------------------------------------------------------+
  21. | 17-Nov-03 Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
  22. | Added register bit definitions to support multiple channels
  23. +----------------------------------------------------------------------------*/
  24. #ifndef _mal_h_
  25. #define _mal_h_
  26. #if !defined(MAL_DCR_BASE)
  27. #define MAL_DCR_BASE 0x180
  28. #endif
  29. #define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */
  30. #define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Error Status (Read/Clear) */
  31. #define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */
  32. #define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */
  33. #define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */
  34. #define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status*/
  35. #define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int */
  36. #define MAL0_TXBADDR (MAL_DCR_BASE + 0x09) /* TX descriptor base addr*/
  37. #define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */
  38. #define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */
  39. #define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status*/
  40. #define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int */
  41. #define MAL0_RXBADDR (MAL_DCR_BASE + 0x15) /* RX descriptor base addr */
  42. #define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table pointer */
  43. #define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table pointer */
  44. #define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table pointer */
  45. #define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table pointer */
  46. #define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table pointer */
  47. #define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table pointer */
  48. #define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */
  49. #define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */
  50. #if defined(CONFIG_440GX) || \
  51. defined(CONFIG_460EX) || defined(CONFIG_460GT)
  52. #define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table pointer */
  53. #define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table pointer */
  54. #define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table pointer */
  55. #define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table pointer*/
  56. #define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table pointer*/
  57. #define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */
  58. #define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */
  59. #define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */
  60. #define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */
  61. #define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */
  62. #endif /* CONFIG_440GX */
  63. /* MADMAL transmit and receive status/control bits */
  64. /* for COMMAC bits, refer to the COMMAC header file */
  65. #define MAL_TX_CTRL_READY 0x8000
  66. #define MAL_TX_CTRL_WRAP 0x4000
  67. #define MAL_TX_CTRL_CM 0x2000
  68. #define MAL_TX_CTRL_LAST 0x1000
  69. #define MAL_TX_CTRL_INTR 0x0400
  70. #define MAL_RX_CTRL_EMPTY 0x8000
  71. #define MAL_RX_CTRL_WRAP 0x4000
  72. #define MAL_RX_CTRL_CM 0x2000
  73. #define MAL_RX_CTRL_LAST 0x1000
  74. #define MAL_RX_CTRL_FIRST 0x0800
  75. #define MAL_RX_CTRL_INTR 0x0400
  76. /* Configuration Reg */
  77. #define MAL_CR_MMSR 0x80000000
  78. #define MAL_CR_PLBP_1 0x00400000 /* lowsest is 00 */
  79. #define MAL_CR_PLBP_2 0x00800000
  80. #define MAL_CR_PLBP_3 0x00C00000 /* highest */
  81. #define MAL_CR_GA 0x00200000
  82. #define MAL_CR_OA 0x00100000
  83. #define MAL_CR_PLBLE 0x00080000
  84. #define MAL_CR_PLBLT_1 0x00040000
  85. #define MAL_CR_PLBLT_2 0x00020000
  86. #define MAL_CR_PLBLT_3 0x00010000
  87. #define MAL_CR_PLBLT_4 0x00008000
  88. #define MAL_CR_PLBLT_DEFAULT 0x00078000 /* ????? */
  89. #define MAL_CR_PLBB 0x00004000
  90. #define MAL_CR_OPBBL 0x00000080
  91. #define MAL_CR_EOPIE 0x00000004
  92. #define MAL_CR_LEA 0x00000002
  93. #define MAL_CR_MSD 0x00000001
  94. /* Error Status Reg */
  95. #define MAL_ESR_EVB 0x80000000
  96. #define MAL_ESR_CID 0x40000000
  97. #define MAL_ESR_DE 0x00100000
  98. #define MAL_ESR_ONE 0x00080000
  99. #define MAL_ESR_OTE 0x00040000
  100. #define MAL_ESR_OSE 0x00020000
  101. #define MAL_ESR_PEIN 0x00010000
  102. /* same bit position as the IER */
  103. /* VV VV */
  104. #define MAL_ESR_DEI 0x00000010
  105. #define MAL_ESR_ONEI 0x00000008
  106. #define MAL_ESR_OTEI 0x00000004
  107. #define MAL_ESR_OSEI 0x00000002
  108. #define MAL_ESR_PBEI 0x00000001
  109. /* ^^ ^^ */
  110. /* Mal IER */
  111. #if defined(CONFIG_440SPE) || \
  112. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  113. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  114. defined(CONFIG_405EX)
  115. #define MAL_IER_PT 0x00000080
  116. #define MAL_IER_PRE 0x00000040
  117. #define MAL_IER_PWE 0x00000020
  118. #define MAL_IER_DE 0x00000010
  119. #define MAL_IER_OTE 0x00000004
  120. #define MAL_IER_OE 0x00000002
  121. #define MAL_IER_PE 0x00000001
  122. #else
  123. #define MAL_IER_DE 0x00000010
  124. #define MAL_IER_NE 0x00000008
  125. #define MAL_IER_TE 0x00000004
  126. #define MAL_IER_OPBE 0x00000002
  127. #define MAL_IER_PLBE 0x00000001
  128. #endif
  129. /* MAL Channel Active Set and Reset Registers */
  130. #define MAL_TXRX_CASR (0x80000000)
  131. #define MAL_TXRX_CASR_V(__x) (__x) /* Channel 0 shifts 0, channel 1 shifts 1, etc */
  132. /* MAL Buffer Descriptor structure */
  133. typedef struct {
  134. short ctrl; /* MAL / Commac status control bits */
  135. short data_len; /* Max length is 4K-1 (12 bits) */
  136. char *data_ptr; /* pointer to actual data buffer */
  137. } mal_desc_t;
  138. #endif