ppc4xx-emac.h 18 KB

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  1. /*
  2. * SPDX-License-Identifier: GPL-2.0 ibm-pibs
  3. */
  4. /*----------------------------------------------------------------------------+
  5. |
  6. | File Name: enetemac.h
  7. |
  8. | Function: Header file for the EMAC3 macro on the 405GP.
  9. |
  10. | Author: Mark Wisner
  11. |
  12. | Change Activity-
  13. |
  14. | Date Description of Change BY
  15. | --------- --------------------- ---
  16. | 29-Apr-99 Created MKW
  17. |
  18. +----------------------------------------------------------------------------*/
  19. /*----------------------------------------------------------------------------+
  20. | 19-Nov-03 Travis Sawyer, Sandburst Corporation, tsawyer@sandburst.com
  21. | ported to handle 440GP and 440GX multiple EMACs
  22. +----------------------------------------------------------------------------*/
  23. #ifndef _PPC4XX_ENET_H_
  24. #define _PPC4XX_ENET_H_
  25. #include <net.h>
  26. #include "asm/ppc4xx-mal.h"
  27. /*-----------------------------------------------------------------------------+
  28. | General enternet defines. 802 frames are not supported.
  29. +-----------------------------------------------------------------------------*/
  30. #define ENET_ADDR_LENGTH 6
  31. #define ENET_ARPTYPE 0x806
  32. #define ARP_REQUEST 1
  33. #define ARP_REPLY 2
  34. #define ENET_IPTYPE 0x800
  35. #define ARP_CACHE_SIZE 5
  36. #define NUM_TX_BUFF 1
  37. #define NUM_RX_BUFF PKTBUFSRX
  38. struct enet_frame {
  39. unsigned char dest_addr[ENET_ADDR_LENGTH];
  40. unsigned char source_addr[ENET_ADDR_LENGTH];
  41. unsigned short type;
  42. unsigned char enet_data[1];
  43. };
  44. struct arp_entry {
  45. unsigned long inet_address;
  46. unsigned char mac_address[ENET_ADDR_LENGTH];
  47. unsigned long valid;
  48. unsigned long sec;
  49. unsigned long nsec;
  50. };
  51. /* Statistic Areas */
  52. #define MAX_ERR_LOG 10
  53. typedef struct emac_stats_st{ /* Statistic Block */
  54. int data_len_err;
  55. int rx_frames;
  56. int rx;
  57. int rx_prot_err;
  58. int int_err;
  59. int pkts_tx;
  60. int pkts_rx;
  61. int pkts_handled;
  62. short tx_err_log[MAX_ERR_LOG];
  63. short rx_err_log[MAX_ERR_LOG];
  64. } EMAC_STATS_ST, *EMAC_STATS_PST;
  65. /* Structure containing variables used by the shared code (4xx_enet.c) */
  66. typedef struct emac_4xx_hw_st {
  67. uint32_t hw_addr; /* EMAC offset */
  68. uint32_t tah_addr; /* TAH offset */
  69. uint32_t phy_id;
  70. uint32_t phy_addr;
  71. uint32_t original_fc;
  72. uint32_t txcw;
  73. uint32_t autoneg_failed;
  74. uint32_t emac_ier;
  75. volatile mal_desc_t *tx;
  76. volatile mal_desc_t *rx;
  77. u32 tx_phys;
  78. u32 rx_phys;
  79. bd_t *bis; /* for eth_init upon mal error */
  80. mal_desc_t *alloc_tx_buf;
  81. mal_desc_t *alloc_rx_buf;
  82. char *txbuf_ptr;
  83. uint16_t devnum;
  84. int get_link_status;
  85. int tbi_compatibility_en;
  86. int tbi_compatibility_on;
  87. int fc_send_xon;
  88. int report_tx_early;
  89. int first_init;
  90. int tx_err_index;
  91. int rx_err_index;
  92. int rx_slot; /* MAL Receive Slot */
  93. int rx_i_index; /* Receive Interrupt Queue Index */
  94. int rx_u_index; /* Receive User Queue Index */
  95. int tx_slot; /* MAL Transmit Slot */
  96. int tx_i_index; /* Transmit Interrupt Queue Index */
  97. int tx_u_index; /* Transmit User Queue Index */
  98. int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */
  99. int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */
  100. int is_receiving; /* sync with eth interrupt */
  101. int print_speed; /* print speed message upon start */
  102. EMAC_STATS_ST stats;
  103. } EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST;
  104. #if defined(CONFIG_440GX) || defined(CONFIG_460GT)
  105. #define EMAC_NUM_DEV 4
  106. #elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
  107. !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
  108. #define EMAC_NUM_DEV 2
  109. #else
  110. #define EMAC_NUM_DEV 1
  111. #endif
  112. #ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
  113. #define EMAC_STACR_OC_MASK (0x00008000)
  114. #else
  115. #define EMAC_STACR_OC_MASK (0x00000000)
  116. #endif
  117. /*
  118. * XMII bridge configurations for those systems (e.g. 405EX(r)) that do
  119. * not have a pin function control (PFC) register to otherwise determine
  120. * the bridge configuration.
  121. */
  122. #define EMAC_PHY_MODE_NONE 0
  123. #define EMAC_PHY_MODE_NONE_RGMII 1
  124. #define EMAC_PHY_MODE_RGMII_NONE 2
  125. #define EMAC_PHY_MODE_RGMII_RGMII 3
  126. #define EMAC_PHY_MODE_NONE_GMII 4
  127. #define EMAC_PHY_MODE_GMII_NONE 5
  128. #define EMAC_PHY_MODE_NONE_MII 6
  129. #define EMAC_PHY_MODE_MII_NONE 7
  130. /* ZMII Bridge Register addresses */
  131. #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
  132. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  133. defined(CONFIG_460EX) || defined(CONFIG_460GT)
  134. #define ZMII0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0D00)
  135. #else
  136. #define ZMII0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0780)
  137. #endif
  138. #define ZMII0_FER (ZMII0_BASE)
  139. #define ZMII0_SSR (ZMII0_BASE + 4)
  140. #define ZMII0_SMIISR (ZMII0_BASE + 8)
  141. /* ZMII FER Register Bit Definitions */
  142. #define ZMII_FER_DIS (0x0)
  143. #define ZMII_FER_MDI (0x8)
  144. #define ZMII_FER_SMII (0x4)
  145. #define ZMII_FER_RMII (0x2)
  146. #define ZMII_FER_MII (0x1)
  147. #define ZMII_FER_RSVD11 (0x00200000)
  148. #define ZMII_FER_RSVD10 (0x00100000)
  149. #define ZMII_FER_RSVD14_31 (0x0003FFFF)
  150. #define ZMII_FER_V(__x) (((3 - __x) * 4) + 16)
  151. /* ZMII Speed Selection Register Bit Definitions */
  152. #define ZMII0_SSR_SCI (0x4)
  153. #define ZMII0_SSR_FSS (0x2)
  154. #define ZMII0_SSR_SP (0x1)
  155. #define ZMII0_SSR_RSVD16_31 (0x0000FFFF)
  156. #define ZMII0_SSR_V(__x) (((3 - __x) * 4) + 16)
  157. /* ZMII SMII Status Register Bit Definitions */
  158. #define ZMII0_SMIISR_E1 (0x80)
  159. #define ZMII0_SMIISR_EC (0x40)
  160. #define ZMII0_SMIISR_EN (0x20)
  161. #define ZMII0_SMIISR_EJ (0x10)
  162. #define ZMII0_SMIISR_EL (0x08)
  163. #define ZMII0_SMIISR_ED (0x04)
  164. #define ZMII0_SMIISR_ES (0x02)
  165. #define ZMII0_SMIISR_EF (0x01)
  166. #define ZMII0_SMIISR_V(__x) ((3 - __x) * 8)
  167. /* RGMII Register Addresses */
  168. #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  169. #define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x1000)
  170. #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
  171. #define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x1500)
  172. #elif defined(CONFIG_405EX)
  173. #define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0xB00)
  174. #else
  175. #define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0790)
  176. #endif
  177. #define RGMII_FER (RGMII_BASE + 0x00)
  178. #define RGMII_SSR (RGMII_BASE + 0x04)
  179. #if defined(CONFIG_460GT)
  180. #define RGMII1_BASE_OFFSET 0x100
  181. #endif
  182. /* RGMII Function Enable (FER) Register Bit Definitions */
  183. #define RGMII_FER_DIS (0x00)
  184. #define RGMII_FER_RTBI (0x04)
  185. #define RGMII_FER_RGMII (0x05)
  186. #define RGMII_FER_TBI (0x06)
  187. #define RGMII_FER_GMII (0x07)
  188. #define RGMII_FER_MII (RGMII_FER_GMII)
  189. #define RGMII_FER_V(__x) ((__x - 2) * 4)
  190. #define RGMII_FER_MDIO(__x) (1 << (19 - (__x)))
  191. /* RGMII Speed Selection Register Bit Definitions */
  192. #define RGMII_SSR_SP_10MBPS (0x00)
  193. #define RGMII_SSR_SP_100MBPS (0x02)
  194. #define RGMII_SSR_SP_1000MBPS (0x04)
  195. #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  196. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  197. defined(CONFIG_405EX)
  198. #define RGMII_SSR_V(__x) ((__x) * 8)
  199. #else
  200. #define RGMII_SSR_V(__x) ((__x -2) * 8)
  201. #endif
  202. /*---------------------------------------------------------------------------+
  203. | TCP/IP Acceleration Hardware (TAH) 440GX Only
  204. +---------------------------------------------------------------------------*/
  205. #if defined(CONFIG_440GX)
  206. #define TAH_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0B50)
  207. #define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/
  208. #define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */
  209. #define TAH_SSR0 (TAH_BASE + 0x14) /* Segment Size Reg 0 (R/W) */
  210. #define TAH_SSR1 (TAH_BASE + 0x18) /* Segment Size Reg 1 (R/W) */
  211. #define TAH_SSR2 (TAH_BASE + 0x1C) /* Segment Size Reg 2 (R/W) */
  212. #define TAH_SSR3 (TAH_BASE + 0x20) /* Segment Size Reg 3 (R/W) */
  213. #define TAH_SSR4 (TAH_BASE + 0x24) /* Segment Size Reg 4 (R/W) */
  214. #define TAH_SSR5 (TAH_BASE + 0x28) /* Segment Size Reg 5 (R/W) */
  215. #define TAH_TSR (TAH_BASE + 0x2C) /* Transmit Status Register (RO) */
  216. /* TAH Revision */
  217. #define TAH_REV_RN_M (0x000FFF00) /* Revision Number */
  218. #define TAH_REV_BN_M (0x000000FF) /* Branch Revision Number */
  219. #define TAH_REV_RN_V (8)
  220. #define TAH_REV_BN_V (0)
  221. /* TAH Mode Register */
  222. #define TAH_MR_CVR (0x80000000) /* Checksum verification on RX */
  223. #define TAH_MR_SR (0x40000000) /* Software reset */
  224. #define TAH_MR_ST (0x3F000000) /* Send Threshold */
  225. #define TAH_MR_TFS (0x00E00000) /* Transmit FIFO size */
  226. #define TAH_MR_DTFP (0x00100000) /* Disable TX FIFO parity */
  227. #define TAH_MR_DIG (0x00080000) /* Disable interrupt generation */
  228. #define TAH_MR_RSVD (0x0007FFFF) /* Reserved */
  229. #define TAH_MR_ST_V (20)
  230. #define TAH_MR_TFS_V (17)
  231. #define TAH_MR_TFS_2K (0x1) /* Transmit FIFO size 2Kbyte */
  232. #define TAH_MR_TFS_4K (0x2) /* Transmit FIFO size 4Kbyte */
  233. #define TAH_MR_TFS_6K (0x3) /* Transmit FIFO size 6Kbyte */
  234. #define TAH_MR_TFS_8K (0x4) /* Transmit FIFO size 8Kbyte */
  235. #define TAH_MR_TFS_10K (0x5) /* Transmit FIFO size 10Kbyte (max)*/
  236. /* TAH Segment Size Registers 0:5 */
  237. #define TAH_SSR_RSVD0 (0xC0000000) /* Reserved */
  238. #define TAH_SSR_SS (0x3FFE0000) /* Segment size in multiples of 2 */
  239. #define TAH_SSR_RSVD1 (0x0001FFFF) /* Reserved */
  240. /* TAH Transmit Status Register */
  241. #define TAH_TSR_TFTS (0x80000000) /* Transmit FIFO too small */
  242. #define TAH_TSR_UH (0x40000000) /* Unrecognized header */
  243. #define TAH_TSR_NIPF (0x20000000) /* Not IPv4 */
  244. #define TAH_TSR_IPOP (0x10000000) /* IP option present */
  245. #define TAH_TSR_NISF (0x08000000) /* No IEEE SNAP format */
  246. #define TAH_TSR_ILTS (0x04000000) /* IP length too short */
  247. #define TAH_TSR_IPFP (0x02000000) /* IP fragment present */
  248. #define TAH_TSR_UP (0x01000000) /* Unsupported protocol */
  249. #define TAH_TSR_TFP (0x00800000) /* TCP flags present */
  250. #define TAH_TSR_SUDP (0x00400000) /* Segmentation for UDP */
  251. #define TAH_TSR_DLM (0x00200000) /* Data length mismatch */
  252. #define TAH_TSR_SIEEE (0x00100000) /* Segmentation for IEEE */
  253. #define TAH_TSR_TFPE (0x00080000) /* Transmit FIFO parity error */
  254. #define TAH_TSR_SSTS (0x00040000) /* Segment size too small */
  255. #define TAH_TSR_RSVD (0x0003FFFF) /* Reserved */
  256. #endif /* CONFIG_440GX */
  257. /* Ethernet MAC Regsiter Addresses */
  258. #if defined(CONFIG_440)
  259. #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
  260. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  261. defined(CONFIG_460EX) || defined(CONFIG_460GT)
  262. #define EMAC0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0E00)
  263. #else
  264. #define EMAC0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
  265. #endif
  266. #else
  267. #if defined(CONFIG_405EZ) || defined(CONFIG_405EX)
  268. #define EMAC0_BASE 0xEF600900
  269. #else
  270. #define EMAC0_BASE 0xEF600800
  271. #endif
  272. #endif
  273. #if defined(CONFIG_440EPX)
  274. #define EMAC1_BASE 0xEF600F00
  275. #define EMAC1_MR1 (EMAC1_BASE + 0x04)
  276. #endif
  277. #define EMAC0_MR0 (EMAC0_BASE)
  278. #define EMAC0_MR1 (EMAC0_BASE + 0x04)
  279. #define EMAC0_TMR0 (EMAC0_BASE + 0x08)
  280. #define EMAC0_TMR1 (EMAC0_BASE + 0x0c)
  281. #define EMAC0_RXM (EMAC0_BASE + 0x10)
  282. #define EMAC0_ISR (EMAC0_BASE + 0x14)
  283. #define EMAC0_IER (EMAC0_BASE + 0x18)
  284. #define EMAC0_IAH (EMAC0_BASE + 0x1c)
  285. #define EMAC0_IAL (EMAC0_BASE + 0x20)
  286. #define EMAC0_PTR (EMAC0_BASE + 0x2c)
  287. #define EMAC0_PAUSE_TIME_REG EMAC0_PTR
  288. #define EMAC0_IPGVR (EMAC0_BASE + 0x58)
  289. #define EMAC0_I_FRAME_GAP_REG EMAC0_IPGVR
  290. #define EMAC0_STACR (EMAC0_BASE + 0x5c)
  291. #define EMAC0_TRTR (EMAC0_BASE + 0x60)
  292. #define EMAC0_RWMR (EMAC0_BASE + 0x64)
  293. #define EMAC0_RX_HI_LO_WMARK EMAC0_RWMR
  294. /* bit definitions */
  295. /* MODE REG 0 */
  296. #define EMAC_MR0_RXI (0x80000000)
  297. #define EMAC_MR0_TXI (0x40000000)
  298. #define EMAC_MR0_SRST (0x20000000)
  299. #define EMAC_MR0_TXE (0x10000000)
  300. #define EMAC_MR0_RXE (0x08000000)
  301. #define EMAC_MR0_WKE (0x04000000)
  302. /* on 440GX EMAC_MR1 has a different layout! */
  303. #if defined(CONFIG_440GX) || \
  304. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  305. defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  306. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  307. defined(CONFIG_405EX)
  308. /* MODE Reg 1 */
  309. #define EMAC_MR1_FDE (0x80000000)
  310. #define EMAC_MR1_ILE (0x40000000)
  311. #define EMAC_MR1_VLE (0x20000000)
  312. #define EMAC_MR1_EIFC (0x10000000)
  313. #define EMAC_MR1_APP (0x08000000)
  314. #define EMAC_MR1_RSVD (0x06000000)
  315. #define EMAC_MR1_IST (0x01000000)
  316. #define EMAC_MR1_MF_1000GPCS (0x00C00000)
  317. #define EMAC_MR1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */
  318. #define EMAC_MR1_MF_100MBPS (0x00400000)
  319. #define EMAC_MR1_RFS_MASK (0x00380000)
  320. #define EMAC_MR1_RFS_16K (0x00280000)
  321. #define EMAC_MR1_RFS_8K (0x00200000)
  322. #define EMAC_MR1_RFS_4K (0x00180000)
  323. #define EMAC_MR1_RFS_2K (0x00100000)
  324. #define EMAC_MR1_RFS_1K (0x00080000)
  325. #define EMAC_MR1_TX_FIFO_MASK (0x00070000)
  326. #define EMAC_MR1_TX_FIFO_16K (0x00050000)
  327. #define EMAC_MR1_TX_FIFO_8K (0x00040000)
  328. #define EMAC_MR1_TX_FIFO_4K (0x00030000)
  329. #define EMAC_MR1_TX_FIFO_2K (0x00020000)
  330. #define EMAC_MR1_TX_FIFO_1K (0x00010000)
  331. #define EMAC_MR1_TR_MULTI (0x00008000) /* 0'x for single packet */
  332. #define EMAC_MR1_MWSW (0x00007000)
  333. #define EMAC_MR1_JUMBO_ENABLE (0x00000800)
  334. #define EMAC_MR1_IPPA (0x000007c0)
  335. #define EMAC_MR1_IPPA_SET(id) (((id) & 0x1f) << 6)
  336. #define EMAC_MR1_IPPA_GET(id) (((id) >> 6) & 0x1f)
  337. #define EMAC_MR1_OBCI_GT100 (0x00000020)
  338. #define EMAC_MR1_OBCI_100 (0x00000018)
  339. #define EMAC_MR1_OBCI_83 (0x00000010)
  340. #define EMAC_MR1_OBCI_66 (0x00000008)
  341. #define EMAC_MR1_RSVD1 (0x00000007)
  342. #else /* defined(CONFIG_440GX) */
  343. /* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
  344. #define EMAC_MR1_FDE 0x80000000
  345. #define EMAC_MR1_ILE 0x40000000
  346. #define EMAC_MR1_VLE 0x20000000
  347. #define EMAC_MR1_EIFC 0x10000000
  348. #define EMAC_MR1_APP 0x08000000
  349. #define EMAC_MR1_AEMI 0x02000000
  350. #define EMAC_MR1_IST 0x01000000
  351. #define EMAC_MR1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
  352. #define EMAC_MR1_MF_100MBPS 0x00400000
  353. #define EMAC_MR1_RFS_MASK 0x00300000
  354. #define EMAC_MR1_RFS_4K 0x00300000
  355. #define EMAC_MR1_RFS_2K 0x00200000
  356. #define EMAC_MR1_RFS_1K 0x00100000
  357. #define EMAC_MR1_RFS_512 0x00000000
  358. #define EMAC_MR1_TX_FIFO_MASK 0x000c0000
  359. #define EMAC_MR1_TX_FIFO_2K 0x00080000
  360. #define EMAC_MR1_TX_FIFO_1K 0x00040000
  361. #define EMAC_MR1_TX_FIFO_512 0x00000000
  362. #define EMAC_MR1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
  363. #define EMAC_MR1_TR0_MULTI 0x00008000
  364. #define EMAC_MR1_TR1_DEPEND 0x00004000
  365. #define EMAC_MR1_TR1_MULTI 0x00002000
  366. #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
  367. #define EMAC_MR1_JUMBO_ENABLE 0x00001000
  368. #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
  369. #endif /* defined(CONFIG_440GX) */
  370. #define EMAC_MR1_FIFO_MASK (EMAC_MR1_RFS_MASK | EMAC_MR1_TX_FIFO_MASK)
  371. #if defined(CONFIG_405EZ)
  372. /* 405EZ only supports 512 bytes fifos */
  373. #define EMAC_MR1_FIFO_SIZE (EMAC_MR1_RFS_512 | EMAC_MR1_TX_FIFO_512)
  374. #else
  375. /* Set receive fifo to 4k and tx fifo to 2k */
  376. #define EMAC_MR1_FIFO_SIZE (EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K)
  377. #endif
  378. /* Transmit Mode Register 0 */
  379. #define EMAC_TMR0_GNP0 (0x80000000)
  380. #define EMAC_TMR0_GNP1 (0x40000000)
  381. #define EMAC_TMR0_GNPD (0x20000000)
  382. #define EMAC_TMR0_FC (0x10000000)
  383. /* Receive Mode Register */
  384. #define EMAC_RMR_SP (0x80000000)
  385. #define EMAC_RMR_SFCS (0x40000000)
  386. #define EMAC_RMR_ARRP (0x20000000)
  387. #define EMAC_RMR_ARP (0x10000000)
  388. #define EMAC_RMR_AROP (0x08000000)
  389. #define EMAC_RMR_ARPI (0x04000000)
  390. #define EMAC_RMR_PPP (0x02000000)
  391. #define EMAC_RMR_PME (0x01000000)
  392. #define EMAC_RMR_PMME (0x00800000)
  393. #define EMAC_RMR_IAE (0x00400000)
  394. #define EMAC_RMR_MIAE (0x00200000)
  395. #define EMAC_RMR_BAE (0x00100000)
  396. #define EMAC_RMR_MAE (0x00080000)
  397. /* Interrupt Status & enable Regs */
  398. #define EMAC_ISR_OVR (0x02000000)
  399. #define EMAC_ISR_PP (0x01000000)
  400. #define EMAC_ISR_BP (0x00800000)
  401. #define EMAC_ISR_RP (0x00400000)
  402. #define EMAC_ISR_SE (0x00200000)
  403. #define EMAC_ISR_SYE (0x00100000)
  404. #define EMAC_ISR_BFCS (0x00080000)
  405. #define EMAC_ISR_PTLE (0x00040000)
  406. #define EMAC_ISR_ORE (0x00020000)
  407. #define EMAC_ISR_IRE (0x00010000)
  408. #define EMAC_ISR_DBDM (0x00000200)
  409. #define EMAC_ISR_DB0 (0x00000100)
  410. #define EMAC_ISR_SE0 (0x00000080)
  411. #define EMAC_ISR_TE0 (0x00000040)
  412. #define EMAC_ISR_DB1 (0x00000020)
  413. #define EMAC_ISR_SE1 (0x00000010)
  414. #define EMAC_ISR_TE1 (0x00000008)
  415. #define EMAC_ISR_MOS (0x00000002)
  416. #define EMAC_ISR_MOF (0x00000001)
  417. /* STA CONTROL REG */
  418. #define EMAC_STACR_OC (0x00008000)
  419. #define EMAC_STACR_PHYE (0x00004000)
  420. #ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
  421. #define EMAC_STACR_INDIRECT_MODE (0x00002000)
  422. #define EMAC_STACR_WRITE (0x00000800) /* $BUC */
  423. #define EMAC_STACR_READ (0x00001000) /* $BUC */
  424. #define EMAC_STACR_OP_MASK (0x00001800)
  425. #define EMAC_STACR_MDIO_ADDR (0x00000000)
  426. #define EMAC_STACR_MDIO_WRITE (0x00000800)
  427. #define EMAC_STACR_MDIO_READ (0x00001800)
  428. #define EMAC_STACR_MDIO_READ_INC (0x00001000)
  429. #else
  430. #define EMAC_STACR_WRITE (0x00002000)
  431. #define EMAC_STACR_READ (0x00001000)
  432. #endif
  433. #define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */
  434. #define EMAC_STACR_CLK_66MHZ (0x00000400)
  435. #define EMAC_STACR_CLK_100MHZ (0x00000C00)
  436. /* Transmit Request Threshold Register */
  437. #define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */
  438. #define EMAC_TRTR_192 (0x10000000)
  439. #define EMAC_TRTR_128 (0x01000000)
  440. /* the follwing defines are for the MadMAL status and control registers. */
  441. /* For bits 0..5 look at the mal.h file */
  442. #define EMAC_TX_CTRL_GFCS (0x0200)
  443. #define EMAC_TX_CTRL_GP (0x0100)
  444. #define EMAC_TX_CTRL_ISA (0x0080)
  445. #define EMAC_TX_CTRL_RSA (0x0040)
  446. #define EMAC_TX_CTRL_IVT (0x0020)
  447. #define EMAC_TX_CTRL_RVT (0x0010)
  448. #define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP)
  449. #define EMAC_TX_ST_BFCS (0x0200)
  450. #define EMAC_TX_ST_BPP (0x0100)
  451. #define EMAC_TX_ST_LCS (0x0080)
  452. #define EMAC_TX_ST_ED (0x0040)
  453. #define EMAC_TX_ST_EC (0x0020)
  454. #define EMAC_TX_ST_LC (0x0010)
  455. #define EMAC_TX_ST_MC (0x0008)
  456. #define EMAC_TX_ST_SC (0x0004)
  457. #define EMAC_TX_ST_UR (0x0002)
  458. #define EMAC_TX_ST_SQE (0x0001)
  459. #define EMAC_TX_ST_DEFAULT (0x03F3)
  460. /* madmal receive status / Control bits */
  461. #define EMAC_RX_ST_OE (0x0200)
  462. #define EMAC_RX_ST_PP (0x0100)
  463. #define EMAC_RX_ST_BP (0x0080)
  464. #define EMAC_RX_ST_RP (0x0040)
  465. #define EMAC_RX_ST_SE (0x0020)
  466. #define EMAC_RX_ST_AE (0x0010)
  467. #define EMAC_RX_ST_BFCS (0x0008)
  468. #define EMAC_RX_ST_PTL (0x0004)
  469. #define EMAC_RX_ST_ORE (0x0002)
  470. #define EMAC_RX_ST_IRE (0x0001)
  471. /* all the errors we care about */
  472. #define EMAC_RX_ERRORS (0x03FF)
  473. #endif /* _PPC4XX_ENET_H_ */