ppc440.h 5.2 KB

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  1. /*
  2. * (C) Copyright 2006
  3. * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
  4. * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
  5. * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
  6. * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
  7. * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
  8. *
  9. * (C) Copyright 2010
  10. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  11. *
  12. * SPDX-License-Identifier: GPL-2.0 ibm-pibs
  13. */
  14. #ifndef __PPC440_H__
  15. #define __PPC440_H__
  16. #define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */
  17. /*
  18. * DCRs & Related
  19. */
  20. /* Memory mapped registers */
  21. #define PCIL0_CFGADR (CONFIG_SYS_PCI_BASE + 0x0ec00000)
  22. #define PCIL0_CFGDATA (CONFIG_SYS_PCI_BASE + 0x0ec00004)
  23. #define PCIL0_CFGBASE (CONFIG_SYS_PCI_BASE + 0x0ec80000)
  24. #define PCIL0_IOBASE (CONFIG_SYS_PCI_BASE + 0x08000000)
  25. /* DCR registers */
  26. /* CPR register declarations */
  27. #define CPR0_PLLC 0x0040
  28. #define CPR0_PLLD 0x0060
  29. #define CPR0_PRIMAD0 0x0080
  30. #define CPR0_PRIMBD0 0x00a0
  31. #define CPR0_OPBD0 0x00c0
  32. #define CPR0_PERD 0x00e0
  33. #define CPR0_MALD 0x0100
  34. #define CPR0_SPCID 0x0120
  35. #define CPR0_ICFG 0x0140
  36. /* SDR register definations */
  37. #define SDR0_SDSTP0 0x0020
  38. #define SDR0_SDSTP1 0x0021
  39. #define SDR0_PINSTP 0x0040
  40. #define SDR0_SDCS0 0x0060
  41. #define SDR0_ECID0 0x0080
  42. #define SDR0_ECID1 0x0081
  43. #define SDR0_ECID2 0x0082
  44. #define SDR0_ECID3 0x0083
  45. #define SDR0_DDR0 0x00e1
  46. #define SDR0_EBC 0x0100
  47. #define SDR0_UART0 0x0120
  48. #define SDR0_UART1 0x0121
  49. #define SDR0_UART2 0x0122
  50. #define SDR0_UART3 0x0123
  51. #define SDR0_CP440 0x0180
  52. #define SDR0_XCR 0x01c0
  53. #define SDR0_XCR0 0x01c0
  54. #define SDR0_XPLLC 0x01c1
  55. #define SDR0_XPLLD 0x01c2
  56. #define SDR0_SRST 0x0200
  57. #define SDR0_SRST0 SDR0_SRST
  58. #define SDR0_SRST1 0x0201
  59. #define SDR0_AMP0 0x0240
  60. #define SDR0_AMP1 0x0241
  61. #define SDR0_USB0 0x0320
  62. #define SDR0_CUST0 0x4000
  63. #define SDR0_CUST1 0x4002
  64. #define SDR0_CUST2 0x4004
  65. #define SDR0_CUST3 0x4006
  66. #define SDR0_PFC0 0x4100
  67. #define SDR0_PFC1 0x4101
  68. #define SDR0_PFC2 0x4102
  69. #define SDR0_PFC4 0x4104
  70. #define SDR0_MFR 0x4300
  71. #define SDR0_DDR0_DDRM_DECODE(n) ((((u32)(n)) >> 29) & 0x03)
  72. #define SDR0_PCI0_PAE_MASK (0x80000000 >> 0)
  73. #define SDR0_XCR0_PAE_MASK (0x80000000 >> 0)
  74. #define SDR0_PFC0_GEIE_MASK 0x00003e00
  75. #define SDR0_PFC0_GEIE_TRE 0x00003e00
  76. #define SDR0_PFC0_GEIE_NOTRE 0x00000000
  77. #define SDR0_PFC0_TRE_MASK (0x80000000 >> 23)
  78. #define SDR0_PFC0_TRE_DISABLE 0x00000000
  79. #define SDR0_PFC0_TRE_ENABLE (0x80000000 >> 23)
  80. /*
  81. * Core Configuration/MMU configuration for 440
  82. */
  83. #define CCR0_DAPUIB 0x00100000
  84. #define CCR0_DTB 0x00008000
  85. #define SDR0_SDCS_SDD (0x80000000 >> 31)
  86. /* todo: move this code from macro offsets to struct */
  87. #define PCIL0_VENDID (PCIL0_CFGBASE + PCI_VENDOR_ID )
  88. #define PCIL0_DEVID (PCIL0_CFGBASE + PCI_DEVICE_ID )
  89. #define PCIL0_CMD (PCIL0_CFGBASE + PCI_COMMAND )
  90. #define PCIL0_STATUS (PCIL0_CFGBASE + PCI_STATUS )
  91. #define PCIL0_REVID (PCIL0_CFGBASE + PCI_REVISION_ID )
  92. #define PCIL0_CLS (PCIL0_CFGBASE + PCI_CLASS_CODE)
  93. #define PCIL0_CACHELS (PCIL0_CFGBASE + PCI_CACHE_LINE_SIZE )
  94. #define PCIL0_LATTIM (PCIL0_CFGBASE + PCI_LATENCY_TIMER )
  95. #define PCIL0_HDTYPE (PCIL0_CFGBASE + PCI_HEADER_TYPE )
  96. #define PCIL0_BIST (PCIL0_CFGBASE + PCI_BIST )
  97. #define PCIL0_BAR0 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_0 )
  98. #define PCIL0_BAR1 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_1 )
  99. #define PCIL0_BAR2 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_2 )
  100. #define PCIL0_BAR3 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_3 )
  101. #define PCIL0_BAR4 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_4 )
  102. #define PCIL0_BAR5 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_5 )
  103. #define PCIL0_CISPTR (PCIL0_CFGBASE + PCI_CARDBUS_CIS )
  104. #define PCIL0_SBSYSVID (PCIL0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
  105. #define PCIL0_SBSYSID (PCIL0_CFGBASE + PCI_SUBSYSTEM_ID )
  106. #define PCIL0_EROMBA (PCIL0_CFGBASE + PCI_ROM_ADDRESS )
  107. #define PCIL0_CAP (PCIL0_CFGBASE + PCI_CAPABILITY_LIST )
  108. #define PCIL0_RES0 (PCIL0_CFGBASE + 0x0035 )
  109. #define PCIL0_RES1 (PCIL0_CFGBASE + 0x0036 )
  110. #define PCIL0_RES2 (PCIL0_CFGBASE + 0x0038 )
  111. #define PCIL0_INTLN (PCIL0_CFGBASE + PCI_INTERRUPT_LINE )
  112. #define PCIL0_INTPN (PCIL0_CFGBASE + PCI_INTERRUPT_PIN )
  113. #define PCIL0_MINGNT (PCIL0_CFGBASE + PCI_MIN_GNT )
  114. #define PCIL0_MAXLTNCY (PCIL0_CFGBASE + PCI_MAX_LAT )
  115. #define PCIL0_POM0LAL (PCIL0_CFGBASE + 0x0068)
  116. #define PCIL0_POM0LAH (PCIL0_CFGBASE + 0x006c)
  117. #define PCIL0_POM0SA (PCIL0_CFGBASE + 0x0070)
  118. #define PCIL0_POM0PCIAL (PCIL0_CFGBASE + 0x0074)
  119. #define PCIL0_POM0PCIAH (PCIL0_CFGBASE + 0x0078)
  120. #define PCIL0_POM1LAL (PCIL0_CFGBASE + 0x007c)
  121. #define PCIL0_POM1LAH (PCIL0_CFGBASE + 0x0080)
  122. #define PCIL0_POM1SA (PCIL0_CFGBASE + 0x0084)
  123. #define PCIL0_POM1PCIAL (PCIL0_CFGBASE + 0x0088)
  124. #define PCIL0_POM1PCIAH (PCIL0_CFGBASE + 0x008c)
  125. #define PCIL0_POM2SA (PCIL0_CFGBASE + 0x0090)
  126. #define PCIL0_PIM0SA (PCIL0_CFGBASE + 0x0098)
  127. #define PCIL0_PIM0LAL (PCIL0_CFGBASE + 0x009c)
  128. #define PCIL0_PIM0LAH (PCIL0_CFGBASE + 0x00a0)
  129. #define PCIL0_PIM1SA (PCIL0_CFGBASE + 0x00a4)
  130. #define PCIL0_PIM1LAL (PCIL0_CFGBASE + 0x00a8)
  131. #define PCIL0_PIM1LAH (PCIL0_CFGBASE + 0x00ac)
  132. #define PCIL0_PIM2SA (PCIL0_CFGBASE + 0x00b0)
  133. #define PCIL0_PIM2LAL (PCIL0_CFGBASE + 0x00b4)
  134. #define PCIL0_PIM2LAH (PCIL0_CFGBASE + 0x00b8)
  135. #define PCIL0_STS (PCIL0_CFGBASE + 0x00e0)
  136. #endif /* __PPC440_H__ */