ppc405.h 2.3 KB

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  1. /*
  2. * SPDX-License-Identifier: GPL-2.0 ibm-pibs
  3. */
  4. #ifndef __PPC405_H__
  5. #define __PPC405_H__
  6. /* Define bits and masks for real-mode storage attribute control registers */
  7. #define PPC_128MB_SACR_BIT(addr) ((addr) >> 27)
  8. #define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
  9. #define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */
  10. /* DCR registers */
  11. #define PLB0_ACR 0x0087
  12. /* SDR registers */
  13. #define SDR0_PINSTP 0x0040
  14. /* CPR registers */
  15. #define CPR0_CLKUPD 0x0020
  16. #define CPR0_PLLC 0x0040
  17. #define CPR0_PLLD 0x0060
  18. #define CPR0_CPUD 0x0080
  19. #define CPR0_PLBD 0x00a0
  20. #define CPR0_OPBD0 0x00c0
  21. #define CPR0_PERD 0x00e0
  22. /*
  23. * DMA
  24. */
  25. #define DMA_DCR_BASE 0x0100
  26. #define DMACR0 (DMA_DCR_BASE + 0x00) /* DMA channel control reg 0 */
  27. #define DMACT0 (DMA_DCR_BASE + 0x01) /* DMA count reg 0 */
  28. #define DMADA0 (DMA_DCR_BASE + 0x02) /* DMA destination address reg 0 */
  29. #define DMASA0 (DMA_DCR_BASE + 0x03) /* DMA source address reg 0 */
  30. #define DMASB0 (DMA_DCR_BASE + 0x04) /* DMA sg descriptor addr 0 */
  31. #define DMACR1 (DMA_DCR_BASE + 0x08) /* DMA channel control reg 1 */
  32. #define DMACT1 (DMA_DCR_BASE + 0x09) /* DMA count reg 1 */
  33. #define DMADA1 (DMA_DCR_BASE + 0x0a) /* DMA destination address reg 1 */
  34. #define DMASA1 (DMA_DCR_BASE + 0x0b) /* DMA source address reg 1 */
  35. #define DMASB1 (DMA_DCR_BASE + 0x0c) /* DMA sg descriptor addr 1 */
  36. #define DMACR2 (DMA_DCR_BASE + 0x10) /* DMA channel control reg 2 */
  37. #define DMACT2 (DMA_DCR_BASE + 0x11) /* DMA count reg 2 */
  38. #define DMADA2 (DMA_DCR_BASE + 0x12) /* DMA destination address reg 2 */
  39. #define DMASA2 (DMA_DCR_BASE + 0x13) /* DMA source address reg 2 */
  40. #define DMASB2 (DMA_DCR_BASE + 0x14) /* DMA sg descriptor addr 2 */
  41. #define DMACR3 (DMA_DCR_BASE + 0x18) /* DMA channel control reg 3 */
  42. #define DMACT3 (DMA_DCR_BASE + 0x19) /* DMA count reg 3 */
  43. #define DMADA3 (DMA_DCR_BASE + 0x1a) /* DMA destination address reg 3 */
  44. #define DMASA3 (DMA_DCR_BASE + 0x1b) /* DMA source address reg 3 */
  45. #define DMASB3 (DMA_DCR_BASE + 0x1c) /* DMA sg descriptor addr 3 */
  46. #define DMASR (DMA_DCR_BASE + 0x20) /* DMA status reg */
  47. #define DMASGC (DMA_DCR_BASE + 0x23) /* DMA scatter/gather command reg*/
  48. #define DMAADR (DMA_DCR_BASE + 0x24) /* DMA address decode reg */
  49. #endif /* __PPC405_H__ */