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  1. /*
  2. * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
  3. * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  4. * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
  5. * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
  6. * Copyright (c) 2008 Nuovation System Designs, LLC
  7. * Grant Erickson <gerickson@nuovations.com>
  8. *
  9. * SPDX-License-Identifier: GPL-2.0 ibm-pibs
  10. */
  11. /*
  12. * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards
  13. *
  14. * The following description only applies to the NOR flash style booting.
  15. * NAND booting is different. For more details about NAND booting on 4xx
  16. * take a look at doc/README.nand-boot-ppc440.
  17. *
  18. * The CPU starts at address 0xfffffffc (last word in the address space).
  19. * The U-Boot image therefore has to be located in the "upper" area of the
  20. * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for
  21. * the boot chip-select (CS0) is quite big and covers this area. On the
  22. * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will
  23. * reconfigure this CS0 (and other chip-selects as well when configured
  24. * this way) in the boot process to the "correct" values matching the
  25. * board layout.
  26. */
  27. #include <asm-offsets.h>
  28. #include <config.h>
  29. #include <asm/ppc4xx.h>
  30. #include <version.h>
  31. #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
  32. #include <ppc_asm.tmpl>
  33. #include <ppc_defs.h>
  34. #include <asm/cache.h>
  35. #include <asm/mmu.h>
  36. #include <asm/ppc4xx-isram.h>
  37. #ifdef CONFIG_SYS_INIT_DCACHE_CS
  38. # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
  39. # define PBxAP PB1AP
  40. # define PBxCR PB0CR
  41. # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
  42. # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
  43. # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
  44. # endif
  45. # endif
  46. # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
  47. # define PBxAP PB1AP
  48. # define PBxCR PB1CR
  49. # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
  50. # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
  51. # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
  52. # endif
  53. # endif
  54. # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
  55. # define PBxAP PB2AP
  56. # define PBxCR PB2CR
  57. # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
  58. # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
  59. # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
  60. # endif
  61. # endif
  62. # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
  63. # define PBxAP PB3AP
  64. # define PBxCR PB3CR
  65. # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
  66. # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
  67. # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
  68. # endif
  69. # endif
  70. # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
  71. # define PBxAP PB4AP
  72. # define PBxCR PB4CR
  73. # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
  74. # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
  75. # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
  76. # endif
  77. # endif
  78. # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
  79. # define PBxAP PB5AP
  80. # define PBxCR PB5CR
  81. # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
  82. # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
  83. # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
  84. # endif
  85. # endif
  86. # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
  87. # define PBxAP PB6AP
  88. # define PBxCR PB6CR
  89. # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
  90. # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
  91. # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
  92. # endif
  93. # endif
  94. # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
  95. # define PBxAP PB7AP
  96. # define PBxCR PB7CR
  97. # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
  98. # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
  99. # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
  100. # endif
  101. # endif
  102. # ifndef PBxAP_VAL
  103. # define PBxAP_VAL 0
  104. # endif
  105. # ifndef PBxCR_VAL
  106. # define PBxCR_VAL 0
  107. # endif
  108. /*
  109. * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
  110. * used as temporary stack pointer for the primordial stack
  111. */
  112. # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
  113. # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
  114. EBC_BXAP_TWT_ENCODE(7) | \
  115. EBC_BXAP_BCE_DISABLE | \
  116. EBC_BXAP_BCT_2TRANS | \
  117. EBC_BXAP_CSN_ENCODE(0) | \
  118. EBC_BXAP_OEN_ENCODE(0) | \
  119. EBC_BXAP_WBN_ENCODE(0) | \
  120. EBC_BXAP_WBF_ENCODE(0) | \
  121. EBC_BXAP_TH_ENCODE(2) | \
  122. EBC_BXAP_RE_DISABLED | \
  123. EBC_BXAP_SOR_NONDELAYED | \
  124. EBC_BXAP_BEM_WRITEONLY | \
  125. EBC_BXAP_PEN_DISABLED)
  126. # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
  127. # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
  128. # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
  129. EBC_BXCR_BS_64MB | \
  130. EBC_BXCR_BU_RW | \
  131. EBC_BXCR_BW_16BIT)
  132. # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
  133. # ifndef CONFIG_SYS_INIT_RAM_PATTERN
  134. # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
  135. # endif
  136. #endif /* CONFIG_SYS_INIT_DCACHE_CS */
  137. #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10)))
  138. #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE!
  139. #endif
  140. /*
  141. * Unless otherwise overriden, enable two 128MB cachable instruction regions
  142. * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
  143. * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
  144. */
  145. #if !defined(CONFIG_SYS_FLASH_BASE)
  146. /* If not already defined, set it to the "last" 128MByte region */
  147. # define CONFIG_SYS_FLASH_BASE 0xf8000000
  148. #endif
  149. #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
  150. # define CONFIG_SYS_ICACHE_SACR_VALUE \
  151. (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
  152. PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
  153. PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
  154. #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
  155. #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
  156. # define CONFIG_SYS_DCACHE_SACR_VALUE \
  157. (0x00000000)
  158. #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
  159. #if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH)
  160. #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0 /* use TLB 0 as default */
  161. #endif
  162. #define function_prolog(func_name) .text; \
  163. .align 2; \
  164. .globl func_name; \
  165. func_name:
  166. #define function_epilog(func_name) .type func_name,@function; \
  167. .size func_name,.-func_name
  168. /* We don't want the MMU yet.
  169. */
  170. #undef MSR_KERNEL
  171. #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
  172. .extern ext_bus_cntlr_init
  173. #ifdef CONFIG_NAND_U_BOOT
  174. .extern reconfig_tlb0
  175. #endif
  176. /*
  177. * Set up GOT: Global Offset Table
  178. *
  179. * Use r12 to access the GOT
  180. */
  181. #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
  182. START_GOT
  183. GOT_ENTRY(_GOT2_TABLE_)
  184. GOT_ENTRY(_FIXUP_TABLE_)
  185. GOT_ENTRY(_start)
  186. GOT_ENTRY(_start_of_vectors)
  187. GOT_ENTRY(_end_of_vectors)
  188. GOT_ENTRY(transfer_to_handler)
  189. GOT_ENTRY(__init_end)
  190. GOT_ENTRY(__bss_end)
  191. GOT_ENTRY(__bss_start)
  192. END_GOT
  193. #endif /* CONFIG_NAND_SPL */
  194. #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
  195. !defined(CONFIG_SPL_BUILD)
  196. /*
  197. * NAND U-Boot image is started from offset 0
  198. */
  199. .text
  200. #if defined(CONFIG_440)
  201. bl reconfig_tlb0
  202. #endif
  203. GET_GOT
  204. bl cpu_init_f /* run low-level CPU init code (from Flash) */
  205. bl board_init_f
  206. /* NOTREACHED - board_init_f() does not return */
  207. #endif
  208. #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
  209. /*
  210. * 4xx RAM-booting U-Boot image is started from offset 0
  211. */
  212. .text
  213. bl _start_440
  214. #endif
  215. #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
  216. /*
  217. * This is the entry of the real U-Boot from a board port
  218. * that supports SPL booting on the PPC4xx. We only need
  219. * to call board_init_f() here. Everything else has already
  220. * been done in the SPL u-boot version.
  221. */
  222. GET_GOT /* initialize GOT access */
  223. bl board_init_f /* run 1st part of board init code (in Flash)*/
  224. /* NOTREACHED - board_init_f() does not return */
  225. #endif
  226. /*
  227. * 440 Startup -- on reset only the top 4k of the effective
  228. * address space is mapped in by an entry in the instruction
  229. * and data shadow TLB. The .bootpg section is located in the
  230. * top 4k & does only what's necessary to map in the the rest
  231. * of the boot rom. Once the boot rom is mapped in we can
  232. * proceed with normal startup.
  233. *
  234. * NOTE: CS0 only covers the top 2MB of the effective address
  235. * space after reset.
  236. */
  237. #if defined(CONFIG_440)
  238. #if !defined(CONFIG_NAND_SPL)
  239. .section .bootpg,"ax"
  240. #endif
  241. .globl _start_440
  242. /**************************************************************************/
  243. _start_440:
  244. /*--------------------------------------------------------------------+
  245. | 440EPX BUP Change - Hardware team request
  246. +--------------------------------------------------------------------*/
  247. #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  248. sync
  249. nop
  250. nop
  251. #endif
  252. /*----------------------------------------------------------------+
  253. | Core bug fix. Clear the esr
  254. +-----------------------------------------------------------------*/
  255. li r0,0
  256. mtspr SPRN_ESR,r0
  257. /*----------------------------------------------------------------*/
  258. /* Clear and set up some registers. */
  259. /*----------------------------------------------------------------*/
  260. iccci r0,r0 /* NOTE: operands not used for 440 */
  261. dccci r0,r0 /* NOTE: operands not used for 440 */
  262. sync
  263. li r0,0
  264. mtspr SPRN_SRR0,r0
  265. mtspr SPRN_SRR1,r0
  266. mtspr SPRN_CSRR0,r0
  267. mtspr SPRN_CSRR1,r0
  268. /* NOTE: 440GX adds machine check status regs */
  269. #if defined(CONFIG_440) && !defined(CONFIG_440GP)
  270. mtspr SPRN_MCSRR0,r0
  271. mtspr SPRN_MCSRR1,r0
  272. mfspr r1,SPRN_MCSR
  273. mtspr SPRN_MCSR,r1
  274. #endif
  275. /*----------------------------------------------------------------*/
  276. /* CCR0 init */
  277. /*----------------------------------------------------------------*/
  278. /* Disable store gathering & broadcast, guarantee inst/data
  279. * cache block touch, force load/store alignment
  280. * (see errata 1.12: 440_33)
  281. */
  282. lis r1,0x0030 /* store gathering & broadcast disable */
  283. ori r1,r1,0x6000 /* cache touch */
  284. mtspr SPRN_CCR0,r1
  285. /*----------------------------------------------------------------*/
  286. /* Initialize debug */
  287. /*----------------------------------------------------------------*/
  288. mfspr r1,SPRN_DBCR0
  289. andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
  290. bne skip_debug_init /* if set, don't clear debug register */
  291. mfspr r1,SPRN_CCR0
  292. ori r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */
  293. mtspr SPRN_CCR0,r1
  294. mtspr SPRN_DBCR0,r0
  295. mtspr SPRN_DBCR1,r0
  296. mtspr SPRN_DBCR2,r0
  297. mtspr SPRN_IAC1,r0
  298. mtspr SPRN_IAC2,r0
  299. mtspr SPRN_IAC3,r0
  300. mtspr SPRN_DAC1,r0
  301. mtspr SPRN_DAC2,r0
  302. mtspr SPRN_DVC1,r0
  303. mtspr SPRN_DVC2,r0
  304. mfspr r1,SPRN_DBSR
  305. mtspr SPRN_DBSR,r1 /* Clear all valid bits */
  306. skip_debug_init:
  307. #if defined (CONFIG_440SPE)
  308. /*----------------------------------------------------------------+
  309. | Initialize Core Configuration Reg1.
  310. | a. ICDPEI: Record even parity. Normal operation.
  311. | b. ICTPEI: Record even parity. Normal operation.
  312. | c. DCTPEI: Record even parity. Normal operation.
  313. | d. DCDPEI: Record even parity. Normal operation.
  314. | e. DCUPEI: Record even parity. Normal operation.
  315. | f. DCMPEI: Record even parity. Normal operation.
  316. | g. FCOM: Normal operation
  317. | h. MMUPEI: Record even parity. Normal operation.
  318. | i. FFF: Flush only as much data as necessary.
  319. | j. TCS: Timebase increments from CPU clock.
  320. +-----------------------------------------------------------------*/
  321. li r0,0
  322. mtspr SPRN_CCR1, r0
  323. /*----------------------------------------------------------------+
  324. | Reset the timebase.
  325. | The previous write to CCR1 sets the timebase source.
  326. +-----------------------------------------------------------------*/
  327. mtspr SPRN_TBWL, r0
  328. mtspr SPRN_TBWU, r0
  329. #endif
  330. /*----------------------------------------------------------------*/
  331. /* Setup interrupt vectors */
  332. /*----------------------------------------------------------------*/
  333. mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */
  334. li r1,0x0100
  335. mtspr SPRN_IVOR0,r1 /* Critical input */
  336. li r1,0x0200
  337. mtspr SPRN_IVOR1,r1 /* Machine check */
  338. li r1,0x0300
  339. mtspr SPRN_IVOR2,r1 /* Data storage */
  340. li r1,0x0400
  341. mtspr SPRN_IVOR3,r1 /* Instruction storage */
  342. li r1,0x0500
  343. mtspr SPRN_IVOR4,r1 /* External interrupt */
  344. li r1,0x0600
  345. mtspr SPRN_IVOR5,r1 /* Alignment */
  346. li r1,0x0700
  347. mtspr SPRN_IVOR6,r1 /* Program check */
  348. li r1,0x0800
  349. mtspr SPRN_IVOR7,r1 /* Floating point unavailable */
  350. li r1,0x0c00
  351. mtspr SPRN_IVOR8,r1 /* System call */
  352. li r1,0x0a00
  353. mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */
  354. li r1,0x0900
  355. mtspr SPRN_IVOR10,r1 /* Decrementer */
  356. li r1,0x1300
  357. mtspr SPRN_IVOR13,r1 /* Data TLB error */
  358. li r1,0x1400
  359. mtspr SPRN_IVOR14,r1 /* Instr TLB error */
  360. li r1,0x2000
  361. mtspr SPRN_IVOR15,r1 /* Debug */
  362. /*----------------------------------------------------------------*/
  363. /* Configure cache regions */
  364. /*----------------------------------------------------------------*/
  365. mtspr SPRN_INV0,r0
  366. mtspr SPRN_INV1,r0
  367. mtspr SPRN_INV2,r0
  368. mtspr SPRN_INV3,r0
  369. mtspr SPRN_DNV0,r0
  370. mtspr SPRN_DNV1,r0
  371. mtspr SPRN_DNV2,r0
  372. mtspr SPRN_DNV3,r0
  373. mtspr SPRN_ITV0,r0
  374. mtspr SPRN_ITV1,r0
  375. mtspr SPRN_ITV2,r0
  376. mtspr SPRN_ITV3,r0
  377. mtspr SPRN_DTV0,r0
  378. mtspr SPRN_DTV1,r0
  379. mtspr SPRN_DTV2,r0
  380. mtspr SPRN_DTV3,r0
  381. /*----------------------------------------------------------------*/
  382. /* Cache victim limits */
  383. /*----------------------------------------------------------------*/
  384. /* floors 0, ceiling max to use the entire cache -- nothing locked
  385. */
  386. lis r1,0x0001
  387. ori r1,r1,0xf800
  388. mtspr SPRN_IVLIM,r1
  389. mtspr SPRN_DVLIM,r1
  390. /*----------------------------------------------------------------+
  391. |Initialize MMUCR[STID] = 0.
  392. +-----------------------------------------------------------------*/
  393. mfspr r0,SPRN_MMUCR
  394. addis r1,0,0xFFFF
  395. ori r1,r1,0xFF00
  396. and r0,r0,r1
  397. mtspr SPRN_MMUCR,r0
  398. /*----------------------------------------------------------------*/
  399. /* Clear all TLB entries -- TID = 0, TS = 0 */
  400. /*----------------------------------------------------------------*/
  401. addis r0,0,0x0000
  402. #ifdef CONFIG_SYS_RAMBOOT
  403. li r4,0 /* Start with TLB #0 */
  404. #else
  405. li r4,1 /* Start with TLB #1 */
  406. #endif
  407. li r1,64 /* 64 TLB entries */
  408. sub r1,r1,r4 /* calculate last TLB # */
  409. mtctr r1
  410. rsttlb:
  411. #ifdef CONFIG_SYS_RAMBOOT
  412. tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
  413. rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */
  414. beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */
  415. #endif
  416. tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/
  417. tlbwe r0,r4,1
  418. tlbwe r0,r4,2
  419. tlbnxt: addi r4,r4,1 /* Next TLB */
  420. bdnz rsttlb
  421. /*----------------------------------------------------------------*/
  422. /* TLB entry setup -- step thru tlbtab */
  423. /*----------------------------------------------------------------*/
  424. #if defined(CONFIG_440SPE_REVA)
  425. /*----------------------------------------------------------------*/
  426. /* We have different TLB tables for revA and rev B of 440SPe */
  427. /*----------------------------------------------------------------*/
  428. mfspr r1, PVR
  429. lis r0,0x5342
  430. ori r0,r0,0x1891
  431. cmpw r7,r1,r0
  432. bne r7,..revA
  433. bl tlbtabB
  434. b ..goon
  435. ..revA:
  436. bl tlbtabA
  437. ..goon:
  438. #else
  439. bl tlbtab /* Get tlbtab pointer */
  440. #endif
  441. mr r5,r0
  442. li r1,0x003f /* 64 TLB entries max */
  443. mtctr r1
  444. li r4,0 /* TLB # */
  445. addi r5,r5,-4
  446. 1:
  447. #ifdef CONFIG_SYS_RAMBOOT
  448. tlbre r3,r4,0 /* Read contents from TLB word #0 */
  449. rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */
  450. bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */
  451. #endif
  452. lwzu r0,4(r5)
  453. cmpwi r0,0
  454. beq 2f /* 0 marks end */
  455. lwzu r1,4(r5)
  456. lwzu r2,4(r5)
  457. tlbwe r0,r4,0 /* TLB Word 0 */
  458. tlbwe r1,r4,1 /* TLB Word 1 */
  459. tlbwe r2,r4,2 /* TLB Word 2 */
  460. tlbnx2: addi r4,r4,1 /* Next TLB */
  461. bdnz 1b
  462. /*----------------------------------------------------------------*/
  463. /* Continue from 'normal' start */
  464. /*----------------------------------------------------------------*/
  465. 2:
  466. bl 3f
  467. b _start
  468. 3: li r0,0
  469. mtspr SPRN_SRR1,r0 /* Keep things disabled for now */
  470. mflr r1
  471. mtspr SPRN_SRR0,r1
  472. rfi
  473. #endif /* CONFIG_440 */
  474. /*
  475. * r3 - 1st arg to board_init(): IMMP pointer
  476. * r4 - 2nd arg to board_init(): boot flag
  477. */
  478. #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
  479. .text
  480. .long 0x27051956 /* U-Boot Magic Number */
  481. .globl version_string
  482. version_string:
  483. .ascii U_BOOT_VERSION_STRING, "\0"
  484. . = EXC_OFF_SYS_RESET
  485. .globl _start_of_vectors
  486. _start_of_vectors:
  487. /* Critical input. */
  488. CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
  489. #ifdef CONFIG_440
  490. /* Machine check */
  491. MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  492. #else
  493. CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  494. #endif /* CONFIG_440 */
  495. /* Data Storage exception. */
  496. STD_EXCEPTION(0x300, DataStorage, UnknownException)
  497. /* Instruction Storage exception. */
  498. STD_EXCEPTION(0x400, InstStorage, UnknownException)
  499. /* External Interrupt exception. */
  500. STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
  501. /* Alignment exception. */
  502. . = 0x600
  503. Alignment:
  504. EXCEPTION_PROLOG(SRR0, SRR1)
  505. mfspr r4,DAR
  506. stw r4,_DAR(r21)
  507. mfspr r5,DSISR
  508. stw r5,_DSISR(r21)
  509. addi r3,r1,STACK_FRAME_OVERHEAD
  510. EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
  511. /* Program check exception */
  512. . = 0x700
  513. ProgramCheck:
  514. EXCEPTION_PROLOG(SRR0, SRR1)
  515. addi r3,r1,STACK_FRAME_OVERHEAD
  516. EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
  517. MSR_KERNEL, COPY_EE)
  518. #ifdef CONFIG_440
  519. STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
  520. STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
  521. STD_EXCEPTION(0xa00, APU, UnknownException)
  522. #endif
  523. STD_EXCEPTION(0xc00, SystemCall, UnknownException)
  524. #ifdef CONFIG_440
  525. STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
  526. STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
  527. #else
  528. STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
  529. STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
  530. STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
  531. #endif
  532. CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
  533. .globl _end_of_vectors
  534. _end_of_vectors:
  535. . = _START_OFFSET
  536. #endif
  537. .globl _start
  538. _start:
  539. #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
  540. /*
  541. * This is the entry of the real U-Boot from a board port
  542. * that supports SPL booting on the PPC4xx. We only need
  543. * to call board_init_f() here. Everything else has already
  544. * been done in the SPL u-boot version.
  545. */
  546. GET_GOT /* initialize GOT access */
  547. bl board_init_f /* run 1st part of board init code (in Flash)*/
  548. /* NOTREACHED - board_init_f() does not return */
  549. #endif
  550. /*****************************************************************************/
  551. #if defined(CONFIG_440)
  552. /*----------------------------------------------------------------*/
  553. /* Clear and set up some registers. */
  554. /*----------------------------------------------------------------*/
  555. li r0,0x0000
  556. lis r1,0xffff
  557. mtspr SPRN_DEC,r0 /* prevent dec exceptions */
  558. mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */
  559. mtspr SPRN_TBWU,r0
  560. mtspr SPRN_TSR,r1 /* clear all timer exception status */
  561. mtspr SPRN_TCR,r0 /* disable all */
  562. mtspr SPRN_ESR,r0 /* clear exception syndrome register */
  563. mtxer r0 /* clear integer exception register */
  564. /*----------------------------------------------------------------*/
  565. /* Debug setup -- some (not very good) ice's need an event*/
  566. /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
  567. /* value you need in this case 0x8cff 0000 should do the trick */
  568. /*----------------------------------------------------------------*/
  569. #if defined(CONFIG_SYS_INIT_DBCR)
  570. lis r1,0xffff
  571. ori r1,r1,0xffff
  572. mtspr SPRN_DBSR,r1 /* Clear all status bits */
  573. lis r0,CONFIG_SYS_INIT_DBCR@h
  574. ori r0,r0,CONFIG_SYS_INIT_DBCR@l
  575. mtspr SPRN_DBCR0,r0
  576. isync
  577. #endif
  578. /*----------------------------------------------------------------*/
  579. /* Setup the internal SRAM */
  580. /*----------------------------------------------------------------*/
  581. li r0,0
  582. #ifdef CONFIG_SYS_INIT_RAM_DCACHE
  583. /* Clear Dcache to use as RAM */
  584. addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
  585. ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
  586. addis r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h
  587. ori r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l
  588. rlwinm. r5,r4,0,27,31
  589. rlwinm r5,r4,27,5,31
  590. beq ..d_ran
  591. addi r5,r5,0x0001
  592. ..d_ran:
  593. mtctr r5
  594. ..d_ag:
  595. dcbz r0,r3
  596. addi r3,r3,32
  597. bdnz ..d_ag
  598. /*
  599. * Lock the init-ram/stack in d-cache, so that other regions
  600. * may use d-cache as well
  601. * Note, that this current implementation locks exactly 4k
  602. * of d-cache, so please make sure that you don't define a
  603. * bigger init-ram area. Take a look at the lwmon5 440EPx
  604. * implementation as a reference.
  605. */
  606. msync
  607. isync
  608. /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
  609. lis r1,0x0201
  610. ori r1,r1,0xf808
  611. mtspr SPRN_DVLIM,r1
  612. lis r1,0x0808
  613. ori r1,r1,0x0808
  614. mtspr SPRN_DNV0,r1
  615. mtspr SPRN_DNV1,r1
  616. mtspr SPRN_DNV2,r1
  617. mtspr SPRN_DNV3,r1
  618. mtspr SPRN_DTV0,r1
  619. mtspr SPRN_DTV1,r1
  620. mtspr SPRN_DTV2,r1
  621. mtspr SPRN_DTV3,r1
  622. msync
  623. isync
  624. #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
  625. /* 440EP & 440GR are only 440er PPC's without internal SRAM */
  626. #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
  627. /* not all PPC's have internal SRAM usable as L2-cache */
  628. #if defined(CONFIG_440GX) || \
  629. defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  630. defined(CONFIG_460SX)
  631. mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
  632. #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  633. defined(CONFIG_APM821XX)
  634. lis r1, 0x0000
  635. ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
  636. mtdcr L2_CACHE_CFG,r1
  637. #endif
  638. lis r2,0x7fff
  639. ori r2,r2,0xffff
  640. mfdcr r1,ISRAM0_DPC
  641. and r1,r1,r2 /* Disable parity check */
  642. mtdcr ISRAM0_DPC,r1
  643. mfdcr r1,ISRAM0_PMEG
  644. and r1,r1,r2 /* Disable pwr mgmt */
  645. mtdcr ISRAM0_PMEG,r1
  646. lis r1,0x8000 /* BAS = 8000_0000 */
  647. #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
  648. ori r1,r1,0x0980 /* first 64k */
  649. mtdcr ISRAM0_SB0CR,r1
  650. lis r1,0x8001
  651. ori r1,r1,0x0980 /* second 64k */
  652. mtdcr ISRAM0_SB1CR,r1
  653. lis r1, 0x8002
  654. ori r1,r1, 0x0980 /* third 64k */
  655. mtdcr ISRAM0_SB2CR,r1
  656. lis r1, 0x8003
  657. ori r1,r1, 0x0980 /* fourth 64k */
  658. mtdcr ISRAM0_SB3CR,r1
  659. #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
  660. defined(CONFIG_460GT) || defined(CONFIG_APM821XX)
  661. lis r1,0x0000 /* BAS = X_0000_0000 */
  662. ori r1,r1,0x0984 /* first 64k */
  663. mtdcr ISRAM0_SB0CR,r1
  664. lis r1,0x0001
  665. ori r1,r1,0x0984 /* second 64k */
  666. mtdcr ISRAM0_SB1CR,r1
  667. lis r1, 0x0002
  668. ori r1,r1, 0x0984 /* third 64k */
  669. mtdcr ISRAM0_SB2CR,r1
  670. lis r1, 0x0003
  671. ori r1,r1, 0x0984 /* fourth 64k */
  672. mtdcr ISRAM0_SB3CR,r1
  673. #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  674. defined(CONFIG_APM821XX)
  675. lis r2,0x7fff
  676. ori r2,r2,0xffff
  677. mfdcr r1,ISRAM1_DPC
  678. and r1,r1,r2 /* Disable parity check */
  679. mtdcr ISRAM1_DPC,r1
  680. mfdcr r1,ISRAM1_PMEG
  681. and r1,r1,r2 /* Disable pwr mgmt */
  682. mtdcr ISRAM1_PMEG,r1
  683. lis r1,0x0004 /* BAS = 4_0004_0000 */
  684. ori r1,r1,ISRAM1_SIZE /* ocm size */
  685. mtdcr ISRAM1_SB0CR,r1
  686. #endif
  687. #elif defined(CONFIG_460SX)
  688. lis r1,0x0000 /* BAS = 0000_0000 */
  689. ori r1,r1,0x0B84 /* first 128k */
  690. mtdcr ISRAM0_SB0CR,r1
  691. lis r1,0x0001
  692. ori r1,r1,0x0B84 /* second 128k */
  693. mtdcr ISRAM0_SB1CR,r1
  694. lis r1, 0x0002
  695. ori r1,r1, 0x0B84 /* third 128k */
  696. mtdcr ISRAM0_SB2CR,r1
  697. lis r1, 0x0003
  698. ori r1,r1, 0x0B84 /* fourth 128k */
  699. mtdcr ISRAM0_SB3CR,r1
  700. #elif defined(CONFIG_440GP)
  701. ori r1,r1,0x0380 /* 8k rw */
  702. mtdcr ISRAM0_SB0CR,r1
  703. mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
  704. #endif
  705. #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
  706. /*----------------------------------------------------------------*/
  707. /* Setup the stack in internal SRAM */
  708. /*----------------------------------------------------------------*/
  709. lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
  710. ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
  711. li r0,0
  712. stwu r0,-4(r1)
  713. stwu r0,-4(r1) /* Terminate call chain */
  714. stwu r1,-8(r1) /* Save back chain and move SP */
  715. lis r0,RESET_VECTOR@h /* Address of reset vector */
  716. ori r0,r0, RESET_VECTOR@l
  717. stwu r1,-8(r1) /* Save back chain and move SP */
  718. stw r0,+12(r1) /* Save return addr (underflow vect) */
  719. #ifdef CONFIG_NAND_SPL
  720. bl nand_boot_common /* will not return */
  721. #else
  722. #ifndef CONFIG_SPL_BUILD
  723. GET_GOT
  724. #endif
  725. bl cpu_init_f /* run low-level CPU init code (from Flash) */
  726. bl board_init_f
  727. /* NOTREACHED - board_init_f() does not return */
  728. #endif
  729. #endif /* CONFIG_440 */
  730. /*****************************************************************************/
  731. #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
  732. defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
  733. defined(CONFIG_405EX) || defined(CONFIG_405)
  734. /*----------------------------------------------------------------------- */
  735. /* Clear and set up some registers. */
  736. /*----------------------------------------------------------------------- */
  737. addi r4,r0,0x0000
  738. #if !defined(CONFIG_405EX)
  739. mtspr SPRN_SGR,r4
  740. #else
  741. /*
  742. * On 405EX, completely clearing the SGR leads to PPC hangup
  743. * upon PCIe configuration access. The PCIe memory regions
  744. * need to be guarded!
  745. */
  746. lis r3,0x0000
  747. ori r3,r3,0x7FFC
  748. mtspr SPRN_SGR,r3
  749. #endif
  750. mtspr SPRN_DCWR,r4
  751. mtesr r4 /* clear Exception Syndrome Reg */
  752. mttcr r4 /* clear Timer Control Reg */
  753. mtxer r4 /* clear Fixed-Point Exception Reg */
  754. mtevpr r4 /* clear Exception Vector Prefix Reg */
  755. addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
  756. /* dbsr is cleared by setting bits to 1) */
  757. mtdbsr r4 /* clear/reset the dbsr */
  758. /* Invalidate the i- and d-caches. */
  759. bl invalidate_icache
  760. bl invalidate_dcache
  761. /* Set-up icache cacheability. */
  762. lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
  763. ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
  764. mticcr r4
  765. isync
  766. /* Set-up dcache cacheability. */
  767. lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
  768. ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
  769. mtdccr r4
  770. #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
  771. && !defined (CONFIG_XILINX_405)
  772. /*----------------------------------------------------------------------- */
  773. /* Tune the speed and size for flash CS0 */
  774. /*----------------------------------------------------------------------- */
  775. bl ext_bus_cntlr_init
  776. #endif
  777. #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
  778. /*
  779. * For boards that don't have OCM and can't use the data cache
  780. * for their primordial stack, setup stack here directly after the
  781. * SDRAM is initialized in ext_bus_cntlr_init.
  782. */
  783. lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
  784. ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
  785. li r0, 0 /* Make room for stack frame header and */
  786. stwu r0, -4(r1) /* clear final stack frame so that */
  787. stwu r0, -4(r1) /* stack backtraces terminate cleanly */
  788. /*
  789. * Set up a dummy frame to store reset vector as return address.
  790. * this causes stack underflow to reset board.
  791. */
  792. stwu r1, -8(r1) /* Save back chain and move SP */
  793. lis r0, RESET_VECTOR@h /* Address of reset vector */
  794. ori r0, r0, RESET_VECTOR@l
  795. stwu r1, -8(r1) /* Save back chain and move SP */
  796. stw r0, +12(r1) /* Save return addr (underflow vect) */
  797. #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
  798. #if defined(CONFIG_405EP)
  799. /*----------------------------------------------------------------------- */
  800. /* DMA Status, clear to come up clean */
  801. /*----------------------------------------------------------------------- */
  802. addis r3,r0, 0xFFFF /* Clear all existing DMA status */
  803. ori r3,r3, 0xFFFF
  804. mtdcr DMASR, r3
  805. bl ppc405ep_init /* do ppc405ep specific init */
  806. #endif /* CONFIG_405EP */
  807. #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
  808. #if defined(CONFIG_405EZ)
  809. /********************************************************************
  810. * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
  811. *******************************************************************/
  812. /*
  813. * We can map the OCM on the PLB3, so map it at
  814. * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
  815. */
  816. lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
  817. ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
  818. ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
  819. mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */
  820. ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
  821. mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */
  822. isync
  823. lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
  824. ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
  825. ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
  826. mtdcr OCM0_DSRC1, r3 /* Set Data Side */
  827. mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */
  828. ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
  829. mtdcr OCM0_DSRC2, r3 /* Set Data Side */
  830. mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */
  831. addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
  832. mtdcr OCM0_DISDPC,r3
  833. isync
  834. #else /* CONFIG_405EZ */
  835. /********************************************************************
  836. * Setup OCM - On Chip Memory
  837. *******************************************************************/
  838. /* Setup OCM */
  839. lis r0, 0x7FFF
  840. ori r0, r0, 0xFFFF
  841. mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */
  842. mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */
  843. and r3, r3, r0 /* disable data-side IRAM */
  844. and r4, r4, r0 /* disable data-side IRAM */
  845. mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */
  846. mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */
  847. isync
  848. lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
  849. ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
  850. mtdcr OCM0_DSARC, r3
  851. addis r4, 0, 0xC000 /* OCM data area enabled */
  852. mtdcr OCM0_DSCNTL, r4
  853. isync
  854. #endif /* CONFIG_405EZ */
  855. #endif
  856. /*----------------------------------------------------------------------- */
  857. /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
  858. /*----------------------------------------------------------------------- */
  859. #ifdef CONFIG_SYS_INIT_DCACHE_CS
  860. li r4, PBxAP
  861. mtdcr EBC0_CFGADDR, r4
  862. lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
  863. ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
  864. mtdcr EBC0_CFGDATA, r4
  865. addi r4, 0, PBxCR
  866. mtdcr EBC0_CFGADDR, r4
  867. lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
  868. ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
  869. mtdcr EBC0_CFGDATA, r4
  870. /*
  871. * Enable the data cache for the 128MB storage access control region
  872. * at CONFIG_SYS_INIT_RAM_ADDR.
  873. */
  874. mfdccr r4
  875. oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
  876. ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
  877. mtdccr r4
  878. /*
  879. * Preallocate data cache lines to be used to avoid a subsequent
  880. * cache miss and an ensuing machine check exception when exceptions
  881. * are enabled.
  882. */
  883. li r0, 0
  884. lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
  885. ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
  886. lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
  887. ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
  888. /*
  889. * Convert the size, in bytes, to the number of cache lines/blocks
  890. * to preallocate.
  891. */
  892. clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
  893. srwi r5, r4, L1_CACHE_SHIFT
  894. beq ..load_counter
  895. addi r5, r5, 0x0001
  896. ..load_counter:
  897. mtctr r5
  898. /* Preallocate the computed number of cache blocks. */
  899. ..alloc_dcache_block:
  900. dcba r0, r3
  901. addi r3, r3, L1_CACHE_BYTES
  902. bdnz ..alloc_dcache_block
  903. sync
  904. /*
  905. * Load the initial stack pointer and data area and convert the size,
  906. * in bytes, to the number of words to initialize to a known value.
  907. */
  908. lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
  909. ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
  910. lis r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h
  911. ori r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l
  912. mtctr r4
  913. lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
  914. ori r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l
  915. lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
  916. ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
  917. ..stackloop:
  918. stwu r4, -4(r2)
  919. bdnz ..stackloop
  920. /*
  921. * Make room for stack frame header and clear final stack frame so
  922. * that stack backtraces terminate cleanly.
  923. */
  924. stwu r0, -4(r1)
  925. stwu r0, -4(r1)
  926. /*
  927. * Set up a dummy frame to store reset vector as return address.
  928. * this causes stack underflow to reset board.
  929. */
  930. stwu r1, -8(r1) /* Save back chain and move SP */
  931. addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
  932. ori r0, r0, RESET_VECTOR@l
  933. stwu r1, -8(r1) /* Save back chain and move SP */
  934. stw r0, +12(r1) /* Save return addr (underflow vect) */
  935. #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
  936. (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
  937. /*
  938. * Stack in OCM.
  939. */
  940. /* Set up Stack at top of OCM */
  941. lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
  942. ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
  943. /* Set up a zeroized stack frame so that backtrace works right */
  944. li r0, 0
  945. stwu r0, -4(r1)
  946. stwu r0, -4(r1)
  947. /*
  948. * Set up a dummy frame to store reset vector as return address.
  949. * this causes stack underflow to reset board.
  950. */
  951. stwu r1, -8(r1) /* Save back chain and move SP */
  952. lis r0, RESET_VECTOR@h /* Address of reset vector */
  953. ori r0, r0, RESET_VECTOR@l
  954. stwu r1, -8(r1) /* Save back chain and move SP */
  955. stw r0, +12(r1) /* Save return addr (underflow vect) */
  956. #endif /* CONFIG_SYS_INIT_DCACHE_CS */
  957. #ifdef CONFIG_NAND_SPL
  958. bl nand_boot_common /* will not return */
  959. #else
  960. GET_GOT /* initialize GOT access */
  961. bl cpu_init_f /* run low-level CPU init code (from Flash) */
  962. bl board_init_f /* run first part of init code (from Flash) */
  963. /* NOTREACHED - board_init_f() does not return */
  964. #endif /* CONFIG_NAND_SPL */
  965. #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
  966. /*----------------------------------------------------------------------- */
  967. #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
  968. /*
  969. * This code finishes saving the registers to the exception frame
  970. * and jumps to the appropriate handler for the exception.
  971. * Register r21 is pointer into trap frame, r1 has new stack pointer.
  972. */
  973. .globl transfer_to_handler
  974. transfer_to_handler:
  975. stw r22,_NIP(r21)
  976. lis r22,MSR_POW@h
  977. andc r23,r23,r22
  978. stw r23,_MSR(r21)
  979. SAVE_GPR(7, r21)
  980. SAVE_4GPRS(8, r21)
  981. SAVE_8GPRS(12, r21)
  982. SAVE_8GPRS(24, r21)
  983. mflr r23
  984. andi. r24,r23,0x3f00 /* get vector offset */
  985. stw r24,TRAP(r21)
  986. li r22,0
  987. stw r22,RESULT(r21)
  988. mtspr SPRG2,r22 /* r1 is now kernel sp */
  989. lwz r24,0(r23) /* virtual address of handler */
  990. lwz r23,4(r23) /* where to go when done */
  991. mtspr SRR0,r24
  992. mtspr SRR1,r20
  993. mtlr r23
  994. SYNC
  995. rfi /* jump to handler, enable MMU */
  996. int_return:
  997. mfmsr r28 /* Disable interrupts */
  998. li r4,0
  999. ori r4,r4,MSR_EE
  1000. andc r28,r28,r4
  1001. SYNC /* Some chip revs need this... */
  1002. mtmsr r28
  1003. SYNC
  1004. lwz r2,_CTR(r1)
  1005. lwz r0,_LINK(r1)
  1006. mtctr r2
  1007. mtlr r0
  1008. lwz r2,_XER(r1)
  1009. lwz r0,_CCR(r1)
  1010. mtspr XER,r2
  1011. mtcrf 0xFF,r0
  1012. REST_10GPRS(3, r1)
  1013. REST_10GPRS(13, r1)
  1014. REST_8GPRS(23, r1)
  1015. REST_GPR(31, r1)
  1016. lwz r2,_NIP(r1) /* Restore environment */
  1017. lwz r0,_MSR(r1)
  1018. mtspr SRR0,r2
  1019. mtspr SRR1,r0
  1020. lwz r0,GPR0(r1)
  1021. lwz r2,GPR2(r1)
  1022. lwz r1,GPR1(r1)
  1023. SYNC
  1024. rfi
  1025. crit_return:
  1026. mfmsr r28 /* Disable interrupts */
  1027. li r4,0
  1028. ori r4,r4,MSR_EE
  1029. andc r28,r28,r4
  1030. SYNC /* Some chip revs need this... */
  1031. mtmsr r28
  1032. SYNC
  1033. lwz r2,_CTR(r1)
  1034. lwz r0,_LINK(r1)
  1035. mtctr r2
  1036. mtlr r0
  1037. lwz r2,_XER(r1)
  1038. lwz r0,_CCR(r1)
  1039. mtspr XER,r2
  1040. mtcrf 0xFF,r0
  1041. REST_10GPRS(3, r1)
  1042. REST_10GPRS(13, r1)
  1043. REST_8GPRS(23, r1)
  1044. REST_GPR(31, r1)
  1045. lwz r2,_NIP(r1) /* Restore environment */
  1046. lwz r0,_MSR(r1)
  1047. mtspr SPRN_CSRR0,r2
  1048. mtspr SPRN_CSRR1,r0
  1049. lwz r0,GPR0(r1)
  1050. lwz r2,GPR2(r1)
  1051. lwz r1,GPR1(r1)
  1052. SYNC
  1053. rfci
  1054. #ifdef CONFIG_440
  1055. mck_return:
  1056. mfmsr r28 /* Disable interrupts */
  1057. li r4,0
  1058. ori r4,r4,MSR_EE
  1059. andc r28,r28,r4
  1060. SYNC /* Some chip revs need this... */
  1061. mtmsr r28
  1062. SYNC
  1063. lwz r2,_CTR(r1)
  1064. lwz r0,_LINK(r1)
  1065. mtctr r2
  1066. mtlr r0
  1067. lwz r2,_XER(r1)
  1068. lwz r0,_CCR(r1)
  1069. mtspr XER,r2
  1070. mtcrf 0xFF,r0
  1071. REST_10GPRS(3, r1)
  1072. REST_10GPRS(13, r1)
  1073. REST_8GPRS(23, r1)
  1074. REST_GPR(31, r1)
  1075. lwz r2,_NIP(r1) /* Restore environment */
  1076. lwz r0,_MSR(r1)
  1077. mtspr SPRN_MCSRR0,r2
  1078. mtspr SPRN_MCSRR1,r0
  1079. lwz r0,GPR0(r1)
  1080. lwz r2,GPR2(r1)
  1081. lwz r1,GPR1(r1)
  1082. SYNC
  1083. rfmci
  1084. #endif /* CONFIG_440 */
  1085. .globl get_pvr
  1086. get_pvr:
  1087. mfspr r3, PVR
  1088. blr
  1089. /*------------------------------------------------------------------------------- */
  1090. /* Function: out16 */
  1091. /* Description: Output 16 bits */
  1092. /*------------------------------------------------------------------------------- */
  1093. .globl out16
  1094. out16:
  1095. sth r4,0x0000(r3)
  1096. blr
  1097. /*------------------------------------------------------------------------------- */
  1098. /* Function: out16r */
  1099. /* Description: Byte reverse and output 16 bits */
  1100. /*------------------------------------------------------------------------------- */
  1101. .globl out16r
  1102. out16r:
  1103. sthbrx r4,r0,r3
  1104. blr
  1105. /*------------------------------------------------------------------------------- */
  1106. /* Function: out32r */
  1107. /* Description: Byte reverse and output 32 bits */
  1108. /*------------------------------------------------------------------------------- */
  1109. .globl out32r
  1110. out32r:
  1111. stwbrx r4,r0,r3
  1112. blr
  1113. /*------------------------------------------------------------------------------- */
  1114. /* Function: in16 */
  1115. /* Description: Input 16 bits */
  1116. /*------------------------------------------------------------------------------- */
  1117. .globl in16
  1118. in16:
  1119. lhz r3,0x0000(r3)
  1120. blr
  1121. /*------------------------------------------------------------------------------- */
  1122. /* Function: in16r */
  1123. /* Description: Input 16 bits and byte reverse */
  1124. /*------------------------------------------------------------------------------- */
  1125. .globl in16r
  1126. in16r:
  1127. lhbrx r3,r0,r3
  1128. blr
  1129. /*------------------------------------------------------------------------------- */
  1130. /* Function: in32r */
  1131. /* Description: Input 32 bits and byte reverse */
  1132. /*------------------------------------------------------------------------------- */
  1133. .globl in32r
  1134. in32r:
  1135. lwbrx r3,r0,r3
  1136. blr
  1137. #if !defined(CONFIG_SPL_BUILD)
  1138. /*
  1139. * void relocate_code (addr_sp, gd, addr_moni)
  1140. *
  1141. * This "function" does not return, instead it continues in RAM
  1142. * after relocating the monitor code.
  1143. *
  1144. * r3 = Relocated stack pointer
  1145. * r4 = Relocated global data pointer
  1146. * r5 = Relocated text pointer
  1147. */
  1148. .globl relocate_code
  1149. relocate_code:
  1150. #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
  1151. /*
  1152. * We need to flush the initial global data (gd_t) and bd_info
  1153. * before the dcache will be invalidated.
  1154. */
  1155. /* Save registers */
  1156. mr r9, r3
  1157. mr r10, r4
  1158. mr r11, r5
  1159. /*
  1160. * Flush complete dcache, this is faster than flushing the
  1161. * ranges for global_data and bd_info instead.
  1162. */
  1163. bl flush_dcache
  1164. #if defined(CONFIG_SYS_INIT_DCACHE_CS)
  1165. /*
  1166. * Undo the earlier data cache set-up for the primordial stack and
  1167. * data area. First, invalidate the data cache and then disable data
  1168. * cacheability for that area. Finally, restore the EBC values, if
  1169. * any.
  1170. */
  1171. /* Invalidate the primordial stack and data area in cache */
  1172. lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
  1173. ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
  1174. lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
  1175. ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
  1176. add r4, r4, r3
  1177. bl invalidate_dcache_range
  1178. /* Disable cacheability for the region */
  1179. mfdccr r3
  1180. lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
  1181. ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
  1182. and r3, r3, r4
  1183. mtdccr r3
  1184. /* Restore the EBC parameters */
  1185. li r3, PBxAP
  1186. mtdcr EBC0_CFGADDR, r3
  1187. lis r3, PBxAP_VAL@h
  1188. ori r3, r3, PBxAP_VAL@l
  1189. mtdcr EBC0_CFGDATA, r3
  1190. li r3, PBxCR
  1191. mtdcr EBC0_CFGADDR, r3
  1192. lis r3, PBxCR_VAL@h
  1193. ori r3, r3, PBxCR_VAL@l
  1194. mtdcr EBC0_CFGDATA, r3
  1195. #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
  1196. /* Restore registers */
  1197. mr r3, r9
  1198. mr r4, r10
  1199. mr r5, r11
  1200. #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
  1201. #ifdef CONFIG_SYS_INIT_RAM_DCACHE
  1202. /*
  1203. * Unlock the previously locked d-cache
  1204. */
  1205. msync
  1206. isync
  1207. /* set TFLOOR/NFLOOR to 0 again */
  1208. lis r6,0x0001
  1209. ori r6,r6,0xf800
  1210. mtspr SPRN_DVLIM,r6
  1211. lis r6,0x0000
  1212. ori r6,r6,0x0000
  1213. mtspr SPRN_DNV0,r6
  1214. mtspr SPRN_DNV1,r6
  1215. mtspr SPRN_DNV2,r6
  1216. mtspr SPRN_DNV3,r6
  1217. mtspr SPRN_DTV0,r6
  1218. mtspr SPRN_DTV1,r6
  1219. mtspr SPRN_DTV2,r6
  1220. mtspr SPRN_DTV3,r6
  1221. msync
  1222. isync
  1223. /* Invalidate data cache, now no longer our stack */
  1224. dccci 0,0
  1225. sync
  1226. isync
  1227. #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
  1228. /*
  1229. * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
  1230. * to speed up the boot process. Now this cache needs to be disabled.
  1231. */
  1232. #if defined(CONFIG_440)
  1233. /* Clear all potential pending exceptions */
  1234. mfspr r1,SPRN_MCSR
  1235. mtspr SPRN_MCSR,r1
  1236. addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
  1237. tlbre r0,r1,0x0002 /* Read contents */
  1238. ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
  1239. tlbwe r0,r1,0x0002 /* Save it out */
  1240. sync
  1241. isync
  1242. #endif /* defined(CONFIG_440) */
  1243. mr r1, r3 /* Set new stack pointer */
  1244. mr r9, r4 /* Save copy of Init Data pointer */
  1245. mr r10, r5 /* Save copy of Destination Address */
  1246. GET_GOT
  1247. mr r3, r5 /* Destination Address */
  1248. lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
  1249. ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
  1250. lwz r5, GOT(__init_end)
  1251. sub r5, r5, r4
  1252. li r6, L1_CACHE_BYTES /* Cache Line Size */
  1253. /*
  1254. * Fix GOT pointer:
  1255. *
  1256. * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
  1257. *
  1258. * Offset:
  1259. */
  1260. sub r15, r10, r4
  1261. /* First our own GOT */
  1262. add r12, r12, r15
  1263. /* then the one used by the C code */
  1264. add r30, r30, r15
  1265. /*
  1266. * Now relocate code
  1267. */
  1268. cmplw cr1,r3,r4
  1269. addi r0,r5,3
  1270. srwi. r0,r0,2
  1271. beq cr1,4f /* In place copy is not necessary */
  1272. beq 7f /* Protect against 0 count */
  1273. mtctr r0
  1274. bge cr1,2f
  1275. la r8,-4(r4)
  1276. la r7,-4(r3)
  1277. 1: lwzu r0,4(r8)
  1278. stwu r0,4(r7)
  1279. bdnz 1b
  1280. b 4f
  1281. 2: slwi r0,r0,2
  1282. add r8,r4,r0
  1283. add r7,r3,r0
  1284. 3: lwzu r0,-4(r8)
  1285. stwu r0,-4(r7)
  1286. bdnz 3b
  1287. /*
  1288. * Now flush the cache: note that we must start from a cache aligned
  1289. * address. Otherwise we might miss one cache line.
  1290. */
  1291. 4: cmpwi r6,0
  1292. add r5,r3,r5
  1293. beq 7f /* Always flush prefetch queue in any case */
  1294. subi r0,r6,1
  1295. andc r3,r3,r0
  1296. mr r4,r3
  1297. 5: dcbst 0,r4
  1298. add r4,r4,r6
  1299. cmplw r4,r5
  1300. blt 5b
  1301. sync /* Wait for all dcbst to complete on bus */
  1302. mr r4,r3
  1303. 6: icbi 0,r4
  1304. add r4,r4,r6
  1305. cmplw r4,r5
  1306. blt 6b
  1307. 7: sync /* Wait for all icbi to complete on bus */
  1308. isync
  1309. /*
  1310. * We are done. Do not return, instead branch to second part of board
  1311. * initialization, now running from RAM.
  1312. */
  1313. addi r0, r10, in_ram - _start + _START_OFFSET
  1314. mtlr r0
  1315. blr /* NEVER RETURNS! */
  1316. in_ram:
  1317. /*
  1318. * Relocation Function, r12 point to got2+0x8000
  1319. *
  1320. * Adjust got2 pointers, no need to check for 0, this code
  1321. * already puts a few entries in the table.
  1322. */
  1323. li r0,__got2_entries@sectoff@l
  1324. la r3,GOT(_GOT2_TABLE_)
  1325. lwz r11,GOT(_GOT2_TABLE_)
  1326. mtctr r0
  1327. sub r11,r3,r11
  1328. addi r3,r3,-4
  1329. 1: lwzu r0,4(r3)
  1330. cmpwi r0,0
  1331. beq- 2f
  1332. add r0,r0,r11
  1333. stw r0,0(r3)
  1334. 2: bdnz 1b
  1335. /*
  1336. * Now adjust the fixups and the pointers to the fixups
  1337. * in case we need to move ourselves again.
  1338. */
  1339. li r0,__fixup_entries@sectoff@l
  1340. lwz r3,GOT(_FIXUP_TABLE_)
  1341. cmpwi r0,0
  1342. mtctr r0
  1343. addi r3,r3,-4
  1344. beq 4f
  1345. 3: lwzu r4,4(r3)
  1346. lwzux r0,r4,r11
  1347. cmpwi r0,0
  1348. add r0,r0,r11
  1349. stw r4,0(r3)
  1350. beq- 5f
  1351. stw r0,0(r4)
  1352. 5: bdnz 3b
  1353. 4:
  1354. clear_bss:
  1355. /*
  1356. * Now clear BSS segment
  1357. */
  1358. lwz r3,GOT(__bss_start)
  1359. lwz r4,GOT(__bss_end)
  1360. cmplw 0, r3, r4
  1361. beq 7f
  1362. li r0, 0
  1363. andi. r5, r4, 3
  1364. beq 6f
  1365. sub r4, r4, r5
  1366. mtctr r5
  1367. mr r5, r4
  1368. 5: stb r0, 0(r5)
  1369. addi r5, r5, 1
  1370. bdnz 5b
  1371. 6:
  1372. stw r0, 0(r3)
  1373. addi r3, r3, 4
  1374. cmplw 0, r3, r4
  1375. bne 6b
  1376. 7:
  1377. mr r3, r9 /* Init Data pointer */
  1378. mr r4, r10 /* Destination Address */
  1379. bl board_init_r
  1380. /*
  1381. * Copy exception vector code to low memory
  1382. *
  1383. * r3: dest_addr
  1384. * r7: source address, r8: end address, r9: target address
  1385. */
  1386. .globl trap_init
  1387. trap_init:
  1388. mflr r4 /* save link register */
  1389. GET_GOT
  1390. lwz r7, GOT(_start_of_vectors)
  1391. lwz r8, GOT(_end_of_vectors)
  1392. li r9, 0x100 /* reset vector always at 0x100 */
  1393. cmplw 0, r7, r8
  1394. bgelr /* return if r7>=r8 - just in case */
  1395. 1:
  1396. lwz r0, 0(r7)
  1397. stw r0, 0(r9)
  1398. addi r7, r7, 4
  1399. addi r9, r9, 4
  1400. cmplw 0, r7, r8
  1401. bne 1b
  1402. /*
  1403. * relocate `hdlr' and `int_return' entries
  1404. */
  1405. li r7, .L_MachineCheck - _start + _START_OFFSET
  1406. li r8, Alignment - _start + _START_OFFSET
  1407. 2:
  1408. bl trap_reloc
  1409. addi r7, r7, 0x100 /* next exception vector */
  1410. cmplw 0, r7, r8
  1411. blt 2b
  1412. li r7, .L_Alignment - _start + _START_OFFSET
  1413. bl trap_reloc
  1414. li r7, .L_ProgramCheck - _start + _START_OFFSET
  1415. bl trap_reloc
  1416. #ifdef CONFIG_440
  1417. li r7, .L_FPUnavailable - _start + _START_OFFSET
  1418. bl trap_reloc
  1419. li r7, .L_Decrementer - _start + _START_OFFSET
  1420. bl trap_reloc
  1421. li r7, .L_APU - _start + _START_OFFSET
  1422. bl trap_reloc
  1423. li r7, .L_InstructionTLBError - _start + _START_OFFSET
  1424. bl trap_reloc
  1425. li r7, .L_DataTLBError - _start + _START_OFFSET
  1426. bl trap_reloc
  1427. #else /* CONFIG_440 */
  1428. li r7, .L_PIT - _start + _START_OFFSET
  1429. bl trap_reloc
  1430. li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
  1431. bl trap_reloc
  1432. li r7, .L_DataTLBMiss - _start + _START_OFFSET
  1433. bl trap_reloc
  1434. #endif /* CONFIG_440 */
  1435. li r7, .L_DebugBreakpoint - _start + _START_OFFSET
  1436. bl trap_reloc
  1437. #if !defined(CONFIG_440)
  1438. addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
  1439. oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
  1440. mtmsr r7 /* change MSR */
  1441. #else
  1442. bl __440_msr_set
  1443. b __440_msr_continue
  1444. __440_msr_set:
  1445. addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
  1446. oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
  1447. mtspr SPRN_SRR1,r7
  1448. mflr r7
  1449. mtspr SPRN_SRR0,r7
  1450. rfi
  1451. __440_msr_continue:
  1452. #endif
  1453. mtlr r4 /* restore link register */
  1454. blr
  1455. #endif /* CONFIG_SPL_BUILD */
  1456. #if defined(CONFIG_440)
  1457. /*----------------------------------------------------------------------------+
  1458. | dcbz_area.
  1459. +----------------------------------------------------------------------------*/
  1460. function_prolog(dcbz_area)
  1461. rlwinm. r5,r4,0,27,31
  1462. rlwinm r5,r4,27,5,31
  1463. beq ..d_ra2
  1464. addi r5,r5,0x0001
  1465. ..d_ra2:mtctr r5
  1466. ..d_ag2:dcbz r0,r3
  1467. addi r3,r3,32
  1468. bdnz ..d_ag2
  1469. sync
  1470. blr
  1471. function_epilog(dcbz_area)
  1472. #endif /* CONFIG_440 */
  1473. #endif /* CONFIG_NAND_SPL */
  1474. /*------------------------------------------------------------------------------- */
  1475. /* Function: in8 */
  1476. /* Description: Input 8 bits */
  1477. /*------------------------------------------------------------------------------- */
  1478. .globl in8
  1479. in8:
  1480. lbz r3,0x0000(r3)
  1481. blr
  1482. /*------------------------------------------------------------------------------- */
  1483. /* Function: out8 */
  1484. /* Description: Output 8 bits */
  1485. /*------------------------------------------------------------------------------- */
  1486. .globl out8
  1487. out8:
  1488. stb r4,0x0000(r3)
  1489. blr
  1490. /*------------------------------------------------------------------------------- */
  1491. /* Function: out32 */
  1492. /* Description: Output 32 bits */
  1493. /*------------------------------------------------------------------------------- */
  1494. .globl out32
  1495. out32:
  1496. stw r4,0x0000(r3)
  1497. blr
  1498. /*------------------------------------------------------------------------------- */
  1499. /* Function: in32 */
  1500. /* Description: Input 32 bits */
  1501. /*------------------------------------------------------------------------------- */
  1502. .globl in32
  1503. in32:
  1504. lwz 3,0x0000(3)
  1505. blr
  1506. /**************************************************************************/
  1507. /* PPC405EP specific stuff */
  1508. /**************************************************************************/
  1509. #ifdef CONFIG_405EP
  1510. ppc405ep_init:
  1511. #ifdef CONFIG_BUBINGA
  1512. /*
  1513. * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
  1514. * function) to support FPGA and NVRAM accesses below.
  1515. */
  1516. lis r3,GPIO0_OSRH@h /* config GPIO output select */
  1517. ori r3,r3,GPIO0_OSRH@l
  1518. lis r4,CONFIG_SYS_GPIO0_OSRH@h
  1519. ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
  1520. stw r4,0(r3)
  1521. lis r3,GPIO0_OSRL@h
  1522. ori r3,r3,GPIO0_OSRL@l
  1523. lis r4,CONFIG_SYS_GPIO0_OSRL@h
  1524. ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
  1525. stw r4,0(r3)
  1526. lis r3,GPIO0_ISR1H@h /* config GPIO input select */
  1527. ori r3,r3,GPIO0_ISR1H@l
  1528. lis r4,CONFIG_SYS_GPIO0_ISR1H@h
  1529. ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
  1530. stw r4,0(r3)
  1531. lis r3,GPIO0_ISR1L@h
  1532. ori r3,r3,GPIO0_ISR1L@l
  1533. lis r4,CONFIG_SYS_GPIO0_ISR1L@h
  1534. ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
  1535. stw r4,0(r3)
  1536. lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
  1537. ori r3,r3,GPIO0_TSRH@l
  1538. lis r4,CONFIG_SYS_GPIO0_TSRH@h
  1539. ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
  1540. stw r4,0(r3)
  1541. lis r3,GPIO0_TSRL@h
  1542. ori r3,r3,GPIO0_TSRL@l
  1543. lis r4,CONFIG_SYS_GPIO0_TSRL@h
  1544. ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
  1545. stw r4,0(r3)
  1546. lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
  1547. ori r3,r3,GPIO0_TCR@l
  1548. lis r4,CONFIG_SYS_GPIO0_TCR@h
  1549. ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
  1550. stw r4,0(r3)
  1551. li r3,PB1AP /* program EBC bank 1 for RTC access */
  1552. mtdcr EBC0_CFGADDR,r3
  1553. lis r3,CONFIG_SYS_EBC_PB1AP@h
  1554. ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
  1555. mtdcr EBC0_CFGDATA,r3
  1556. li r3,PB1CR
  1557. mtdcr EBC0_CFGADDR,r3
  1558. lis r3,CONFIG_SYS_EBC_PB1CR@h
  1559. ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
  1560. mtdcr EBC0_CFGDATA,r3
  1561. li r3,PB1AP /* program EBC bank 1 for RTC access */
  1562. mtdcr EBC0_CFGADDR,r3
  1563. lis r3,CONFIG_SYS_EBC_PB1AP@h
  1564. ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
  1565. mtdcr EBC0_CFGDATA,r3
  1566. li r3,PB1CR
  1567. mtdcr EBC0_CFGADDR,r3
  1568. lis r3,CONFIG_SYS_EBC_PB1CR@h
  1569. ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
  1570. mtdcr EBC0_CFGDATA,r3
  1571. li r3,PB4AP /* program EBC bank 4 for FPGA access */
  1572. mtdcr EBC0_CFGADDR,r3
  1573. lis r3,CONFIG_SYS_EBC_PB4AP@h
  1574. ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
  1575. mtdcr EBC0_CFGDATA,r3
  1576. li r3,PB4CR
  1577. mtdcr EBC0_CFGADDR,r3
  1578. lis r3,CONFIG_SYS_EBC_PB4CR@h
  1579. ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
  1580. mtdcr EBC0_CFGDATA,r3
  1581. #endif
  1582. /*
  1583. !-----------------------------------------------------------------------
  1584. ! Check to see if chip is in bypass mode.
  1585. ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
  1586. ! CPU reset Otherwise, skip this step and keep going.
  1587. ! Note: Running BIOS in bypass mode is not supported since PLB speed
  1588. ! will not be fast enough for the SDRAM (min 66MHz)
  1589. !-----------------------------------------------------------------------
  1590. */
  1591. mfdcr r5, CPC0_PLLMR1
  1592. rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
  1593. cmpi cr0,0,r4,0x1
  1594. beq pll_done /* if SSCS =b'1' then PLL has */
  1595. /* already been set */
  1596. /* and CPU has been reset */
  1597. /* so skip to next section */
  1598. #ifdef CONFIG_BUBINGA
  1599. /*
  1600. !-----------------------------------------------------------------------
  1601. ! Read NVRAM to get value to write in PLLMR.
  1602. ! If value has not been correctly saved, write default value
  1603. ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
  1604. ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
  1605. !
  1606. ! WARNING: This code assumes the first three words in the nvram_t
  1607. ! structure in openbios.h. Changing the beginning of
  1608. ! the structure will break this code.
  1609. !
  1610. !-----------------------------------------------------------------------
  1611. */
  1612. addis r3,0,NVRAM_BASE@h
  1613. addi r3,r3,NVRAM_BASE@l
  1614. lwz r4, 0(r3)
  1615. addis r5,0,NVRVFY1@h
  1616. addi r5,r5,NVRVFY1@l
  1617. cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
  1618. bne ..no_pllset
  1619. addi r3,r3,4
  1620. lwz r4, 0(r3)
  1621. addis r5,0,NVRVFY2@h
  1622. addi r5,r5,NVRVFY2@l
  1623. cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
  1624. bne ..no_pllset
  1625. addi r3,r3,8 /* Skip over conf_size */
  1626. lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
  1627. lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
  1628. rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
  1629. cmpi cr0,0,r5,1 /* See if PLL is locked */
  1630. beq pll_write
  1631. ..no_pllset:
  1632. #endif /* CONFIG_BUBINGA */
  1633. #ifdef CONFIG_TAIHU
  1634. mfdcr r4, CPC0_BOOT
  1635. andi. r5, r4, CPC0_BOOT_SEP@l
  1636. bne strap_1 /* serial eeprom present */
  1637. addis r5,0,CPLD_REG0_ADDR@h
  1638. ori r5,r5,CPLD_REG0_ADDR@l
  1639. andi. r5, r5, 0x10
  1640. bne _pci_66mhz
  1641. #endif /* CONFIG_TAIHU */
  1642. #if defined(CONFIG_ZEUS)
  1643. mfdcr r4, CPC0_BOOT
  1644. andi. r5, r4, CPC0_BOOT_SEP@l
  1645. bne strap_1 /* serial eeprom present */
  1646. lis r3,0x0000
  1647. addi r3,r3,0x3030
  1648. lis r4,0x8042
  1649. addi r4,r4,0x223e
  1650. b 1f
  1651. strap_1:
  1652. mfdcr r3, CPC0_PLLMR0
  1653. mfdcr r4, CPC0_PLLMR1
  1654. b 1f
  1655. #endif
  1656. addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
  1657. ori r3,r3,PLLMR0_DEFAULT@l /* */
  1658. addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
  1659. ori r4,r4,PLLMR1_DEFAULT@l /* */
  1660. #ifdef CONFIG_TAIHU
  1661. b 1f
  1662. _pci_66mhz:
  1663. addis r3,0,PLLMR0_DEFAULT_PCI66@h
  1664. ori r3,r3,PLLMR0_DEFAULT_PCI66@l
  1665. addis r4,0,PLLMR1_DEFAULT_PCI66@h
  1666. ori r4,r4,PLLMR1_DEFAULT_PCI66@l
  1667. b 1f
  1668. strap_1:
  1669. mfdcr r3, CPC0_PLLMR0
  1670. mfdcr r4, CPC0_PLLMR1
  1671. #endif /* CONFIG_TAIHU */
  1672. 1:
  1673. b pll_write /* Write the CPC0_PLLMR with new value */
  1674. pll_done:
  1675. /*
  1676. !-----------------------------------------------------------------------
  1677. ! Clear Soft Reset Register
  1678. ! This is needed to enable PCI if not booting from serial EPROM
  1679. !-----------------------------------------------------------------------
  1680. */
  1681. addi r3, 0, 0x0
  1682. mtdcr CPC0_SRR, r3
  1683. addis r3,0,0x0010
  1684. mtctr r3
  1685. pci_wait:
  1686. bdnz pci_wait
  1687. blr /* return to main code */
  1688. /*
  1689. !-----------------------------------------------------------------------------
  1690. ! Function: pll_write
  1691. ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
  1692. ! That is:
  1693. ! 1. Pll is first disabled (de-activated by putting in bypass mode)
  1694. ! 2. PLL is reset
  1695. ! 3. Clock dividers are set while PLL is held in reset and bypassed
  1696. ! 4. PLL Reset is cleared
  1697. ! 5. Wait 100us for PLL to lock
  1698. ! 6. A core reset is performed
  1699. ! Input: r3 = Value to write to CPC0_PLLMR0
  1700. ! Input: r4 = Value to write to CPC0_PLLMR1
  1701. ! Output r3 = none
  1702. !-----------------------------------------------------------------------------
  1703. */
  1704. .globl pll_write
  1705. pll_write:
  1706. mfdcr r5, CPC0_UCR
  1707. andis. r5,r5,0xFFFF
  1708. ori r5,r5,0x0101 /* Stop the UART clocks */
  1709. mtdcr CPC0_UCR,r5 /* Before changing PLL */
  1710. mfdcr r5, CPC0_PLLMR1
  1711. rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
  1712. mtdcr CPC0_PLLMR1,r5
  1713. oris r5,r5,0x4000 /* Set PLL Reset */
  1714. mtdcr CPC0_PLLMR1,r5
  1715. mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
  1716. rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
  1717. oris r5,r5,0x4000 /* Set PLL Reset */
  1718. mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
  1719. rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
  1720. mtdcr CPC0_PLLMR1,r5
  1721. /*
  1722. ! Wait min of 100us for PLL to lock.
  1723. ! See CMOS 27E databook for more info.
  1724. ! At 200MHz, that means waiting 20,000 instructions
  1725. */
  1726. addi r3,0,20000 /* 2000 = 0x4e20 */
  1727. mtctr r3
  1728. pll_wait:
  1729. bdnz pll_wait
  1730. oris r5,r5,0x8000 /* Enable PLL */
  1731. mtdcr CPC0_PLLMR1,r5 /* Engage */
  1732. /*
  1733. * Reset CPU to guarantee timings are OK
  1734. * Not sure if this is needed...
  1735. */
  1736. addis r3,0,0x1000
  1737. mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */
  1738. /* execution will continue from the poweron */
  1739. /* vector of 0xfffffffc */
  1740. #endif /* CONFIG_405EP */
  1741. #if defined(CONFIG_440)
  1742. /*----------------------------------------------------------------------------+
  1743. | mttlb3.
  1744. +----------------------------------------------------------------------------*/
  1745. function_prolog(mttlb3)
  1746. TLBWE(4,3,2)
  1747. blr
  1748. function_epilog(mttlb3)
  1749. /*----------------------------------------------------------------------------+
  1750. | mftlb3.
  1751. +----------------------------------------------------------------------------*/
  1752. function_prolog(mftlb3)
  1753. TLBRE(3,3,2)
  1754. blr
  1755. function_epilog(mftlb3)
  1756. /*----------------------------------------------------------------------------+
  1757. | mttlb2.
  1758. +----------------------------------------------------------------------------*/
  1759. function_prolog(mttlb2)
  1760. TLBWE(4,3,1)
  1761. blr
  1762. function_epilog(mttlb2)
  1763. /*----------------------------------------------------------------------------+
  1764. | mftlb2.
  1765. +----------------------------------------------------------------------------*/
  1766. function_prolog(mftlb2)
  1767. TLBRE(3,3,1)
  1768. blr
  1769. function_epilog(mftlb2)
  1770. /*----------------------------------------------------------------------------+
  1771. | mttlb1.
  1772. +----------------------------------------------------------------------------*/
  1773. function_prolog(mttlb1)
  1774. TLBWE(4,3,0)
  1775. blr
  1776. function_epilog(mttlb1)
  1777. /*----------------------------------------------------------------------------+
  1778. | mftlb1.
  1779. +----------------------------------------------------------------------------*/
  1780. function_prolog(mftlb1)
  1781. TLBRE(3,3,0)
  1782. blr
  1783. function_epilog(mftlb1)
  1784. #endif /* CONFIG_440 */
  1785. #if defined(CONFIG_NAND_SPL)
  1786. /*
  1787. * void nand_boot_relocate(dst, src, bytes)
  1788. *
  1789. * r3 = Destination address to copy code to (in SDRAM)
  1790. * r4 = Source address to copy code from
  1791. * r5 = size to copy in bytes
  1792. */
  1793. nand_boot_relocate:
  1794. mr r6,r3
  1795. mr r7,r4
  1796. mflr r8
  1797. /*
  1798. * Copy SPL from icache into SDRAM
  1799. */
  1800. subi r3,r3,4
  1801. subi r4,r4,4
  1802. srwi r5,r5,2
  1803. mtctr r5
  1804. ..spl_loop:
  1805. lwzu r0,4(r4)
  1806. stwu r0,4(r3)
  1807. bdnz ..spl_loop
  1808. /*
  1809. * Calculate "corrected" link register, so that we "continue"
  1810. * in execution in destination range
  1811. */
  1812. sub r3,r7,r6 /* r3 = src - dst */
  1813. sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
  1814. mtlr r8
  1815. blr
  1816. nand_boot_common:
  1817. /*
  1818. * First initialize SDRAM. It has to be available *before* calling
  1819. * nand_boot().
  1820. */
  1821. lis r3,CONFIG_SYS_SDRAM_BASE@h
  1822. ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
  1823. bl initdram
  1824. /*
  1825. * Now copy the 4k SPL code into SDRAM and continue execution
  1826. * from there.
  1827. */
  1828. lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
  1829. ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
  1830. lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
  1831. ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
  1832. lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
  1833. ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
  1834. bl nand_boot_relocate
  1835. /*
  1836. * We're running from SDRAM now!!!
  1837. *
  1838. * It is necessary for 4xx systems to relocate from running at
  1839. * the original location (0xfffffxxx) to somewhere else (SDRAM
  1840. * preferably). This is because CS0 needs to be reconfigured for
  1841. * NAND access. And we can't reconfigure this CS when currently
  1842. * "running" from it.
  1843. */
  1844. /*
  1845. * Finally call nand_boot() to load main NAND U-Boot image from
  1846. * NAND and jump to it.
  1847. */
  1848. bl nand_boot /* will not return */
  1849. #endif /* CONFIG_NAND_SPL */