4xx_uart.c 7.2 KB

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  1. /*
  2. * (C) Copyright 2000-2006
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * (C) Copyright 2010
  6. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  7. *
  8. * SPDX-License-Identifier: GPL-2.0 ibm-pibs
  9. */
  10. #include <common.h>
  11. #include <commproc.h>
  12. #include <asm/processor.h>
  13. #include <asm/io.h>
  14. #include <watchdog.h>
  15. #include <asm/ppc4xx.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
  18. defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
  19. defined(CONFIG_405EX) || defined(CONFIG_440)
  20. #if defined(CONFIG_440)
  21. #if defined(CONFIG_440GP)
  22. #define CR0_MASK 0x3fff0000
  23. #define CR0_EXTCLK_ENA 0x00600000
  24. #define CR0_UDIV_POS 16
  25. #define UDIV_SUBTRACT 1
  26. #define UART0_SDR CPC0_CR0
  27. #define MFREG(a, d) d = mfdcr(a)
  28. #define MTREG(a, d) mtdcr(a, d)
  29. #else /* #if defined(CONFIG_440GP) */
  30. /* all other 440 PPC's access clock divider via sdr register */
  31. #define CR0_MASK 0xdfffffff
  32. #define CR0_EXTCLK_ENA 0x00800000
  33. #define CR0_UDIV_POS 0
  34. #define UDIV_SUBTRACT 0
  35. #define UART0_SDR SDR0_UART0
  36. #define UART1_SDR SDR0_UART1
  37. #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
  38. defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
  39. defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  40. defined(CONFIG_460EX) || defined(CONFIG_460GT)
  41. #define UART2_SDR SDR0_UART2
  42. #endif
  43. #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
  44. defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
  45. defined(CONFIG_460EX) || defined(CONFIG_460GT)
  46. #define UART3_SDR SDR0_UART3
  47. #endif
  48. #define MFREG(a, d) mfsdr(a, d)
  49. #define MTREG(a, d) mtsdr(a, d)
  50. #endif /* #if defined(CONFIG_440GP) */
  51. #elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
  52. #define UCR0_MASK 0x0000007f
  53. #define UCR1_MASK 0x00007f00
  54. #define UCR0_UDIV_POS 0
  55. #define UCR1_UDIV_POS 8
  56. #define UDIV_MAX 127
  57. #elif defined(CONFIG_405EX)
  58. #define MFREG(a, d) mfsdr(a, d)
  59. #define MTREG(a, d) mtsdr(a, d)
  60. #define CR0_MASK 0x000000ff
  61. #define CR0_EXTCLK_ENA 0x00800000
  62. #define CR0_UDIV_POS 0
  63. #define UDIV_SUBTRACT 0
  64. #define UART0_SDR SDR0_UART0
  65. #define UART1_SDR SDR0_UART1
  66. #else /* CONFIG_405GP || CONFIG_405CR */
  67. #define CR0_MASK 0x00001fff
  68. #define CR0_EXTCLK_ENA 0x000000c0
  69. #define CR0_UDIV_POS 1
  70. #define UDIV_MAX 32
  71. #endif
  72. #if defined(CONFIG_405EP) && defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
  73. #error "External serial clock not supported on AMCC PPC405EP!"
  74. #endif
  75. #if (defined(CONFIG_405EX) || defined(CONFIG_405EZ) || \
  76. defined(CONFIG_440)) && !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
  77. /*
  78. * For some SoC's, the cpu clock is on divider chain A, UART on
  79. * divider chain B ... so cpu clock is irrelevant. Get the
  80. * "optimized" values that are subject to the 1/2 opb clock
  81. * constraint.
  82. */
  83. static u16 serial_bdiv(int baudrate, u32 *udiv)
  84. {
  85. sys_info_t sysinfo;
  86. u32 div; /* total divisor udiv * bdiv */
  87. u32 umin; /* minimum udiv */
  88. u16 diff; /* smallest diff */
  89. u16 idiff; /* current diff */
  90. u16 ibdiv; /* current bdiv */
  91. u32 i;
  92. u32 est; /* current estimate */
  93. u32 max;
  94. #if defined(CONFIG_405EZ)
  95. u32 cpr_pllc;
  96. u32 plloutb;
  97. u32 reg;
  98. #endif
  99. get_sys_info(&sysinfo);
  100. #if defined(CONFIG_405EZ)
  101. /* check the pll feedback source */
  102. mfcpr(CPR0_PLLC, cpr_pllc);
  103. plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
  104. sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) *
  105. sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB);
  106. div = plloutb / (16 * baudrate); /* total divisor */
  107. umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
  108. max = 256; /* highest possible */
  109. #else /* 405EZ */
  110. div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
  111. umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
  112. max = 32; /* highest possible */
  113. #endif /* 405EZ */
  114. *udiv = diff = max;
  115. /*
  116. * i is the test udiv value -- start with the largest
  117. * possible (max) to minimize serial clock and constrain
  118. * search to umin.
  119. */
  120. for (i = max; i > umin; i--) {
  121. ibdiv = div / i;
  122. est = i * ibdiv;
  123. idiff = (est > div) ? (est - div) : (div - est);
  124. if (idiff == 0) {
  125. *udiv = i;
  126. break; /* can't do better */
  127. } else if (idiff < diff) {
  128. *udiv = i; /* best so far */
  129. diff = idiff; /* update lowest diff*/
  130. }
  131. }
  132. #if defined(CONFIG_405EZ)
  133. mfcpr(CPR0_PERD0, reg);
  134. reg &= ~0x0000ffff;
  135. reg |= ((*udiv - 0) << 8) | (*udiv - 0);
  136. mtcpr(CPR0_PERD0, reg);
  137. #endif
  138. return div / *udiv;
  139. }
  140. #endif /* #if (defined(CONFIG_405EP) ... */
  141. /*
  142. * This function returns the UART clock used by the common
  143. * NS16550 driver. Additionally the SoC internal divisors for
  144. * optimal UART baudrate are configured.
  145. */
  146. int get_serial_clock(void)
  147. {
  148. u32 clk;
  149. u32 udiv;
  150. #if !defined(CONFIG_405EZ)
  151. u32 reg;
  152. #endif
  153. #if !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
  154. PPC4xx_SYS_INFO sys_info;
  155. #endif
  156. /*
  157. * Programming of the internal divisors is SoC specific.
  158. * Let's handle this in some #ifdef's for the SoC's.
  159. */
  160. #if defined(CONFIG_405CR) || defined(CONFIG_405GP)
  161. reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
  162. #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
  163. clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
  164. udiv = 1;
  165. reg |= CR0_EXTCLK_ENA;
  166. #else /* CONFIG_SYS_EXT_SERIAL_CLOCK */
  167. clk = gd->cpu_clk;
  168. #ifdef CONFIG_SYS_405_UART_ERRATA_59
  169. udiv = 31; /* Errata 59: stuck at 31 */
  170. #else /* CONFIG_SYS_405_UART_ERRATA_59 */
  171. {
  172. u32 tmp = CONFIG_SYS_BASE_BAUD * 16;
  173. udiv = (clk + tmp / 2) / tmp;
  174. }
  175. if (udiv > UDIV_MAX) /* max. n bits for udiv */
  176. udiv = UDIV_MAX;
  177. #endif /* CONFIG_SYS_405_UART_ERRATA_59 */
  178. #endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */
  179. reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
  180. mtdcr (CPC0_CR0, reg);
  181. #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
  182. clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
  183. #else
  184. clk = CONFIG_SYS_BASE_BAUD * 16;
  185. #endif
  186. #endif /* CONFIG_405CR */
  187. #if defined(CONFIG_405EP)
  188. {
  189. u32 tmp = CONFIG_SYS_BASE_BAUD * 16;
  190. reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
  191. clk = gd->cpu_clk;
  192. udiv = (clk + tmp / 2) / tmp;
  193. if (udiv > UDIV_MAX) /* max. n bits for udiv */
  194. udiv = UDIV_MAX;
  195. }
  196. reg |= udiv << UCR0_UDIV_POS; /* set the UART divisor */
  197. reg |= udiv << UCR1_UDIV_POS; /* set the UART divisor */
  198. mtdcr(CPC0_UCR, reg);
  199. clk = CONFIG_SYS_BASE_BAUD * 16;
  200. #endif /* CONFIG_405EP */
  201. #if defined(CONFIG_405EX) || defined(CONFIG_440)
  202. MFREG(UART0_SDR, reg);
  203. reg &= ~CR0_MASK;
  204. #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
  205. reg |= CR0_EXTCLK_ENA;
  206. udiv = 1;
  207. clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
  208. #else /* CONFIG_SYS_EXT_SERIAL_CLOCK */
  209. clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16;
  210. #endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */
  211. reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
  212. /*
  213. * Configure input clock to baudrate generator for all
  214. * available serial ports here
  215. */
  216. MTREG(UART0_SDR, reg);
  217. #if defined(UART1_SDR)
  218. MTREG(UART1_SDR, reg);
  219. #endif
  220. #if defined(UART2_SDR)
  221. MTREG(UART2_SDR, reg);
  222. #endif
  223. #if defined(UART3_SDR)
  224. MTREG(UART3_SDR, reg);
  225. #endif
  226. #endif /* CONFIG_405EX ... */
  227. #if defined(CONFIG_405EZ)
  228. clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16;
  229. #endif /* CONFIG_405EZ */
  230. /*
  231. * Correct UART frequency in bd-info struct now that
  232. * the UART divisor is available
  233. */
  234. #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
  235. gd->arch.uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
  236. #else
  237. get_sys_info(&sys_info);
  238. gd->arch.uart_clk = sys_info.freqUART / udiv;
  239. #endif
  240. return clk;
  241. }
  242. #endif /* CONFIG_405GP || CONFIG_405CR */