4xx_pci.c 28 KB

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  1. /*
  2. * SPDX-License-Identifier: GPL-2.0 ibm-pibs
  3. *
  4. * File Name: 405gp_pci.c
  5. *
  6. * Function: Initialization code for the 405GP PCI Configuration regs.
  7. *
  8. * Author: Mark Game
  9. *
  10. * Change Activity-
  11. *
  12. * Date Description of Change BY
  13. * --------- --------------------- ---
  14. * 09-Sep-98 Created MCG
  15. * 02-Nov-98 Removed External arbiter selected message JWB
  16. * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB
  17. * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG
  18. * from (0 to n) to (1 to n).
  19. * 17-May-99 Port to Walnut JWB
  20. * 17-Jun-99 Updated for VGA support JWB
  21. * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB
  22. * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG
  23. * target latency timer values are not supported).
  24. * Should be fixed in pass 2.
  25. * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB
  26. * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
  27. * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
  28. * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
  29. * really required after a reset since PMMxMAs are already
  30. * disabled but is a good practice nonetheless. JWB
  31. * 12-Jun-01 stefan.roese@esd-electronics.com
  32. * - PCI host/adapter handling reworked
  33. * 09-Jul-01 stefan.roese@esd-electronics.com
  34. * - PCI host now configures from device 0 (not 1) to max_dev,
  35. * (host configures itself)
  36. * - On CPCI-405 pci base address and size is generated from
  37. * SDRAM and FLASH size (CFG regs not used anymore)
  38. * - Some minor changes for CPCI-405-A (adapter version)
  39. * 14-Sep-01 stefan.roese@esd-electronics.com
  40. * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
  41. * 28-Sep-01 stefan.roese@esd-electronics.com
  42. * - Changed pci master configuration for linux compatibility
  43. * (no need for bios_fixup() anymore)
  44. * 26-Feb-02 stefan.roese@esd-electronics.com
  45. * - Bug fixed in pci configuration (Andrew May)
  46. * - Removed pci class code init for CPCI405 board
  47. * 15-May-02 stefan.roese@esd-electronics.com
  48. * - New vga device handling
  49. * 29-May-02 stefan.roese@esd-electronics.com
  50. * - PCI class code init added (if defined)
  51. *----------------------------------------------------------------------------*/
  52. #include <common.h>
  53. #include <command.h>
  54. #include <asm/4xx_pci.h>
  55. #include <asm/processor.h>
  56. #include <asm/io.h>
  57. #include <pci.h>
  58. #ifdef CONFIG_PCI
  59. DECLARE_GLOBAL_DATA_PTR;
  60. #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
  61. #if defined(CONFIG_PMC405)
  62. ushort pmc405_pci_subsys_deviceid(void);
  63. #endif
  64. /*#define DEBUG*/
  65. /*
  66. * Board-specific pci initialization
  67. * Platform code can reimplement pci_pre_init() if needed
  68. */
  69. int __pci_pre_init(struct pci_controller *hose)
  70. {
  71. #if defined(CONFIG_405EP)
  72. /*
  73. * Enable the internal PCI arbiter by default.
  74. *
  75. * On 405EP CPUs the internal arbiter can be controlled
  76. * by the I2C strapping EEPROM. If you want to do so
  77. * or if you want to disable the arbiter pci_pre_init()
  78. * must be reimplemented without enabling the arbiter.
  79. * The arbiter is enabled in this place because of
  80. * compatibility reasons.
  81. */
  82. mtdcr(CPC0_PCI, mfdcr(CPC0_PCI) | CPC0_PCI_ARBIT_EN);
  83. #endif /* CONFIG_405EP */
  84. return 1;
  85. }
  86. int pci_pre_init(struct pci_controller *hose)
  87. __attribute__((weak, alias("__pci_pre_init")));
  88. int __is_pci_host(struct pci_controller *hose)
  89. {
  90. #if defined(CONFIG_405GP)
  91. if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
  92. return 1;
  93. #elif defined (CONFIG_405EP)
  94. if (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN)
  95. return 1;
  96. #endif
  97. return 0;
  98. }
  99. int is_pci_host(struct pci_controller *hose) __attribute__((weak, alias("__is_pci_host")));
  100. /*-----------------------------------------------------------------------------+
  101. * pci_init. Initializes the 405GP PCI Configuration regs.
  102. *-----------------------------------------------------------------------------*/
  103. void pci_405gp_init(struct pci_controller *hose)
  104. {
  105. int i, reg_num = 0;
  106. bd_t *bd = gd->bd;
  107. unsigned short temp_short;
  108. unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI};
  109. #if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
  110. char *ptmla_str, *ptmms_str;
  111. #endif
  112. unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
  113. unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
  114. #if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
  115. unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
  116. unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
  117. unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
  118. unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
  119. #else
  120. unsigned long pmmla[3] = {0x80000000, 0,0};
  121. unsigned long pmmma[3] = {0xC0000001, 0,0};
  122. unsigned long pmmpcila[3] = {0x80000000, 0,0};
  123. unsigned long pmmpciha[3] = {0x00000000, 0,0};
  124. #endif
  125. #ifdef CONFIG_PCI_PNP
  126. #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
  127. char *s;
  128. #endif
  129. #endif
  130. #if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
  131. ptmla_str = getenv("ptm1la");
  132. ptmms_str = getenv("ptm1ms");
  133. if(NULL != ptmla_str && NULL != ptmms_str ) {
  134. ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
  135. ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
  136. }
  137. ptmla_str = getenv("ptm2la");
  138. ptmms_str = getenv("ptm2ms");
  139. if(NULL != ptmla_str && NULL != ptmms_str ) {
  140. ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
  141. ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
  142. }
  143. #endif
  144. /*
  145. * Register the hose
  146. */
  147. hose->first_busno = 0;
  148. hose->last_busno = 0xff;
  149. /* ISA/PCI I/O space */
  150. pci_set_region(hose->regions + reg_num++,
  151. MIN_PCI_PCI_IOADDR,
  152. MIN_PLB_PCI_IOADDR,
  153. 0x10000,
  154. PCI_REGION_IO);
  155. /* PCI I/O space */
  156. pci_set_region(hose->regions + reg_num++,
  157. 0x00800000,
  158. 0xe8800000,
  159. 0x03800000,
  160. PCI_REGION_IO);
  161. reg_num = 2;
  162. /* Memory spaces */
  163. for (i=0; i<2; i++)
  164. if (ptmms[i] & 1)
  165. {
  166. if (!i) hose->pci_fb = hose->regions + reg_num;
  167. pci_set_region(hose->regions + reg_num++,
  168. ptmpcila[i], ptmla[i],
  169. ~(ptmms[i] & 0xfffff000) + 1,
  170. PCI_REGION_MEM |
  171. PCI_REGION_SYS_MEMORY);
  172. }
  173. /* PCI memory spaces */
  174. for (i=0; i<3; i++)
  175. if (pmmma[i] & 1)
  176. {
  177. pci_set_region(hose->regions + reg_num++,
  178. pmmpcila[i], pmmla[i],
  179. ~(pmmma[i] & 0xfffff000) + 1,
  180. PCI_REGION_MEM);
  181. }
  182. hose->region_count = reg_num;
  183. pci_setup_indirect(hose,
  184. PCICFGADR,
  185. PCICFGDATA);
  186. if (hose->pci_fb)
  187. pciauto_region_init(hose->pci_fb);
  188. /* Let board change/modify hose & do initial checks */
  189. if (pci_pre_init(hose) == 0) {
  190. printf("PCI: Board-specific initialization failed.\n");
  191. printf("PCI: Configuration aborted.\n");
  192. return;
  193. }
  194. pci_register_hose(hose);
  195. /*--------------------------------------------------------------------------+
  196. * 405GP PCI Master configuration.
  197. * Map one 512 MB range of PLB/processor addresses to PCI memory space.
  198. * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
  199. * Use byte reversed out routines to handle endianess.
  200. *--------------------------------------------------------------------------*/
  201. out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
  202. out32r(PMM0LA, pmmla[0]);
  203. out32r(PMM0PCILA, pmmpcila[0]);
  204. out32r(PMM0PCIHA, pmmpciha[0]);
  205. out32r(PMM0MA, pmmma[0]);
  206. /*--------------------------------------------------------------------------+
  207. * PMM1 is not used. Initialize them to zero.
  208. *--------------------------------------------------------------------------*/
  209. out32r(PMM1MA, (pmmma[1]&~0x1));
  210. out32r(PMM1LA, pmmla[1]);
  211. out32r(PMM1PCILA, pmmpcila[1]);
  212. out32r(PMM1PCIHA, pmmpciha[1]);
  213. out32r(PMM1MA, pmmma[1]);
  214. /*--------------------------------------------------------------------------+
  215. * PMM2 is not used. Initialize them to zero.
  216. *--------------------------------------------------------------------------*/
  217. out32r(PMM2MA, (pmmma[2]&~0x1));
  218. out32r(PMM2LA, pmmla[2]);
  219. out32r(PMM2PCILA, pmmpcila[2]);
  220. out32r(PMM2PCIHA, pmmpciha[2]);
  221. out32r(PMM2MA, pmmma[2]);
  222. /*--------------------------------------------------------------------------+
  223. * 405GP PCI Target configuration. (PTM1)
  224. * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
  225. *--------------------------------------------------------------------------*/
  226. out32r(PTM1LA, ptmla[0]); /* insert address */
  227. out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */
  228. pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]);
  229. /*--------------------------------------------------------------------------+
  230. * 405GP PCI Target configuration. (PTM2)
  231. *--------------------------------------------------------------------------*/
  232. out32r(PTM2LA, ptmla[1]); /* insert address */
  233. pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]);
  234. if (ptmms[1] == 0)
  235. {
  236. out32r(PTM2MS, 0x00000001); /* set enable bit */
  237. pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
  238. out32r(PTM2MS, 0x00000000); /* disable */
  239. }
  240. else
  241. {
  242. out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */
  243. }
  244. /*
  245. * Insert Subsystem Vendor and Device ID
  246. */
  247. pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
  248. #ifdef CONFIG_CPCI405
  249. if (is_pci_host(hose))
  250. pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
  251. else
  252. pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2);
  253. #else
  254. pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
  255. #endif
  256. /*
  257. * Insert Class-code
  258. */
  259. #ifdef CONFIG_SYS_PCI_CLASSCODE
  260. pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE);
  261. #endif /* CONFIG_SYS_PCI_CLASSCODE */
  262. /*--------------------------------------------------------------------------+
  263. * If PCI speed = 66MHz, set 66MHz capable bit.
  264. *--------------------------------------------------------------------------*/
  265. if (bd->bi_pci_busfreq >= 66000000) {
  266. pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
  267. pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
  268. }
  269. #if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
  270. #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
  271. if (is_pci_host(hose) ||
  272. (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
  273. #endif
  274. {
  275. /*--------------------------------------------------------------------------+
  276. * Write the 405GP PCI Configuration regs.
  277. * Enable 405GP to be a master on the PCI bus (PMM).
  278. * Enable 405GP to act as a PCI memory target (PTM).
  279. *--------------------------------------------------------------------------*/
  280. pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
  281. pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
  282. PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
  283. }
  284. #endif
  285. #if defined(CONFIG_405EP)
  286. /*
  287. * on ppc405ep vendor/device id is not set
  288. * The user manual says 0x1014 (IBM) / 0x0156 (405GP!)
  289. * are the correct values.
  290. */
  291. pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, PCI_VENDOR_ID_IBM);
  292. pci_write_config_word(PCIDEVID_405GP,
  293. PCI_DEVICE_ID, PCI_DEVICE_ID_IBM_405GP);
  294. #endif
  295. /*
  296. * Set HCE bit (Host Configuration Enabled)
  297. */
  298. pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
  299. pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
  300. #ifdef CONFIG_PCI_PNP
  301. /*--------------------------------------------------------------------------+
  302. * Scan the PCI bus and configure devices found.
  303. *--------------------------------------------------------------------------*/
  304. #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
  305. if (is_pci_host(hose) ||
  306. (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
  307. #endif
  308. {
  309. #ifdef CONFIG_PCI_SCAN_SHOW
  310. printf("PCI: Bus Dev VenId DevId Class Int\n");
  311. #endif
  312. hose->last_busno = pci_hose_scan(hose);
  313. }
  314. #endif /* CONFIG_PCI_PNP */
  315. }
  316. /*
  317. * drivers/pci/pci.c skips every host bridge but the 405GP since it could
  318. * be set as an Adapter.
  319. *
  320. * I (Andrew May) don't know what we should do here, but I don't want
  321. * the auto setup of a PCI device disabling what is done pci_405gp_init
  322. * as has happened before.
  323. */
  324. void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
  325. struct pci_config_table *entry)
  326. {
  327. #ifdef DEBUG
  328. printf("405gp_setup_bridge\n");
  329. #endif
  330. }
  331. /*
  332. *
  333. */
  334. void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
  335. {
  336. unsigned char int_line = 0xff;
  337. /*
  338. * Write pci interrupt line register (cpci405 specific)
  339. */
  340. switch (PCI_DEV(dev) & 0x03)
  341. {
  342. case 0:
  343. int_line = 27 + 2;
  344. break;
  345. case 1:
  346. int_line = 27 + 3;
  347. break;
  348. case 2:
  349. int_line = 27 + 0;
  350. break;
  351. case 3:
  352. int_line = 27 + 1;
  353. break;
  354. }
  355. pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
  356. }
  357. void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
  358. struct pci_config_table *entry)
  359. {
  360. unsigned int cmdstat = 0;
  361. pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
  362. /* always enable io space on vga boards */
  363. pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
  364. cmdstat |= PCI_COMMAND_IO;
  365. pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
  366. }
  367. #if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3))
  368. /*
  369. *As is these functs get called out of flash Not a horrible
  370. *thing, but something to keep in mind. (no statics?)
  371. */
  372. static struct pci_config_table pci_405gp_config_table[] = {
  373. /*if VendID is 0 it terminates the table search (ie Walnut)*/
  374. #ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID
  375. {CONFIG_SYS_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
  376. PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
  377. #endif
  378. {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
  379. PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
  380. {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
  381. PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
  382. { }
  383. };
  384. static struct pci_controller hose = {
  385. fixup_irq: pci_405gp_fixup_irq,
  386. config_table: pci_405gp_config_table,
  387. };
  388. void pci_init_board(void)
  389. {
  390. /*we want the ptrs to RAM not flash (ie don't use init list)*/
  391. hose.fixup_irq = pci_405gp_fixup_irq;
  392. hose.config_table = pci_405gp_config_table;
  393. pci_405gp_init(&hose);
  394. }
  395. #endif
  396. #endif /* CONFIG_405GP */
  397. /*-----------------------------------------------------------------------------+
  398. * CONFIG_440
  399. *-----------------------------------------------------------------------------*/
  400. #if defined(CONFIG_440)
  401. #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
  402. static struct pci_controller ppc440_hose = {0};
  403. #endif
  404. /*
  405. * This routine is called to determine if a pci scan should be
  406. * performed. With various hardware environments (especially cPCI and
  407. * PPMC) it's insufficient to depend on the state of the arbiter enable
  408. * bit in the strap register, or generic host/adapter assumptions.
  409. *
  410. * Rather than hard-code a bad assumption in the general 440 code, the
  411. * 440 pci code requires the board to decide at runtime.
  412. *
  413. * Return 0 for adapter mode, non-zero for host (monarch) mode.
  414. *
  415. * Weak default implementation: "Normal" boards implement the PCI
  416. * host functionality. This can be overridden for PCI adapter boards.
  417. */
  418. int __is_pci_host(struct pci_controller *hose)
  419. {
  420. return 1;
  421. }
  422. int is_pci_host(struct pci_controller *hose)
  423. __attribute__((weak, alias("__is_pci_host")));
  424. #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
  425. defined(CONFIG_440GR) || defined(CONFIG_440GRX)
  426. #if defined(CONFIG_SYS_PCI_TARGET_INIT)
  427. /*
  428. * pci_target_init
  429. *
  430. * The bootstrap configuration provides default settings for the pci
  431. * inbound map (PIM). But the bootstrap config choices are limited and
  432. * may not be sufficient for a given board.
  433. */
  434. void __pci_target_init(struct pci_controller *hose)
  435. {
  436. /*
  437. * Set up Direct MMIO registers
  438. */
  439. /*
  440. * PowerPC440 EP PCI Master configuration.
  441. * Map one 1Gig range of PLB/processor addresses to PCI memory space.
  442. * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
  443. * Use byte reversed out routines to handle endianess.
  444. * Make this region non-prefetchable.
  445. */
  446. /* PMM0 Mask/Attribute - disabled b4 setting */
  447. out_le32((void *)PCIL0_PMM0MA, 0x00000000);
  448. /* PMM0 Local Address */
  449. out_le32((void *)PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
  450. /* PMM0 PCI Low Address */
  451. out_le32((void *)PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
  452. /* PMM0 PCI High Address */
  453. out_le32((void *)PCIL0_PMM0PCIHA, 0x00000000);
  454. /* 512M + No prefetching, and enable region */
  455. out_le32((void *)PCIL0_PMM0MA, 0xE0000001);
  456. /* PMM1 Mask/Attribute - disabled b4 setting */
  457. out_le32((void *)PCIL0_PMM1MA, 0x00000000);
  458. /* PMM1 Local Address */
  459. out_le32((void *)PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
  460. /* PMM1 PCI Low Address */
  461. out_le32((void *)PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
  462. /* PMM1 PCI High Address */
  463. out_le32((void *)PCIL0_PMM1PCIHA, 0x00000000);
  464. /* 512M + No prefetching, and enable region */
  465. out_le32((void *)PCIL0_PMM1MA, 0xE0000001);
  466. out_le32((void *)PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
  467. out_le32((void *)PCIL0_PTM1LA, 0); /* Local Addr. Reg */
  468. out_le32((void *)PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
  469. out_le32((void *)PCIL0_PTM2LA, 0); /* Local Addr. Reg */
  470. /*
  471. * Set up Configuration registers
  472. */
  473. /* Program the board's subsystem id/vendor id */
  474. pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
  475. CONFIG_SYS_PCI_SUBSYS_VENDORID);
  476. pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
  477. /* Configure command register as bus master */
  478. pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
  479. /* 240nS PCI clock */
  480. pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
  481. /* No error reporting */
  482. pci_write_config_word(0, PCI_ERREN, 0);
  483. pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
  484. }
  485. #endif /* CONFIG_SYS_PCI_TARGET_INIT */
  486. /*
  487. * pci_pre_init
  488. *
  489. * This routine is called just prior to registering the hose and gives
  490. * the board the opportunity to check things. Returning a value of zero
  491. * indicates that things are bad & PCI initialization should be aborted.
  492. *
  493. * Different boards may wish to customize the pci controller structure
  494. * (add regions, override default access routines, etc) or perform
  495. * certain pre-initialization actions.
  496. *
  497. */
  498. int __pci_pre_init(struct pci_controller *hose)
  499. {
  500. u32 reg;
  501. /*
  502. * Set priority for all PLB3 devices to 0.
  503. * Set PLB3 arbiter to fair mode.
  504. */
  505. mfsdr(SDR0_AMP1, reg);
  506. mtsdr(SDR0_AMP1, (reg & 0x000000FF) | 0x0000FF00);
  507. reg = mfdcr(PLB3A0_ACR);
  508. mtdcr(PLB3A0_ACR, reg | 0x80000000);
  509. /*
  510. * Set priority for all PLB4 devices to 0.
  511. */
  512. mfsdr(SDR0_AMP0, reg);
  513. mtsdr(SDR0_AMP0, (reg & 0x000000FF) | 0x0000FF00);
  514. reg = mfdcr(PLB4A0_ACR) | 0xa0000000;
  515. mtdcr(PLB4A0_ACR, reg);
  516. /*
  517. * Set Nebula PLB4 arbiter to fair mode.
  518. */
  519. /* Segment0 */
  520. reg = (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
  521. reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
  522. reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
  523. reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
  524. mtdcr(PLB4A0_ACR, reg);
  525. /* Segment1 */
  526. reg = (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
  527. reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
  528. reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
  529. reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
  530. mtdcr(PLB4A1_ACR, reg);
  531. #if defined(CONFIG_SYS_PCI_BOARD_FIXUP_IRQ)
  532. hose->fixup_irq = board_pci_fixup_irq;
  533. #endif
  534. return 1;
  535. }
  536. #else /* defined(CONFIG_440EP) ... */
  537. #if defined(CONFIG_SYS_PCI_TARGET_INIT)
  538. void __pci_target_init(struct pci_controller * hose)
  539. {
  540. /*
  541. * Disable everything
  542. */
  543. out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
  544. out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
  545. out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
  546. out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
  547. /*
  548. * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
  549. * strapping options do not support sizes such as 128/256 MB.
  550. */
  551. out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
  552. out_le32((void *)PCIL0_PIM0LAH, 0);
  553. out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
  554. out_le32((void *)PCIL0_BAR0, 0);
  555. /*
  556. * Program the board's subsystem id/vendor id
  557. */
  558. out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
  559. out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
  560. out_le16((void *)PCIL0_CMD, in_le16((void *)PCIL0_CMD) |
  561. PCI_COMMAND_MEMORY);
  562. }
  563. #endif /* CONFIG_SYS_PCI_TARGET_INIT */
  564. int __pci_pre_init(struct pci_controller *hose)
  565. {
  566. /*
  567. * This board is always configured as the host & requires the
  568. * PCI arbiter to be enabled.
  569. */
  570. if (!pci_arbiter_enabled()) {
  571. printf("PCI: PCI Arbiter disabled!\n");
  572. return 0;
  573. }
  574. return 1;
  575. }
  576. #endif /* defined(CONFIG_440EP) ... */
  577. #if defined(CONFIG_SYS_PCI_TARGET_INIT)
  578. void pci_target_init(struct pci_controller * hose)
  579. __attribute__((weak, alias("__pci_target_init")));
  580. #endif /* CONFIG_SYS_PCI_TARGET_INIT */
  581. int pci_pre_init(struct pci_controller *hose)
  582. __attribute__((weak, alias("__pci_pre_init")));
  583. #if defined(CONFIG_SYS_PCI_MASTER_INIT)
  584. void __pci_master_init(struct pci_controller *hose)
  585. {
  586. u16 reg;
  587. /*
  588. * Write the PowerPC440 EP PCI Configuration regs.
  589. * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
  590. * Enable PowerPC440 EP to act as a PCI memory target (PTM).
  591. */
  592. pci_read_config_word(0, PCI_COMMAND, &reg);
  593. pci_write_config_word(0, PCI_COMMAND, reg |
  594. PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
  595. }
  596. void pci_master_init(struct pci_controller *hose)
  597. __attribute__((weak, alias("__pci_master_init")));
  598. #endif /* CONFIG_SYS_PCI_MASTER_INIT */
  599. #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
  600. static int pci_440_init (struct pci_controller *hose)
  601. {
  602. int reg_num = 0;
  603. #ifndef CONFIG_DISABLE_PISE_TEST
  604. /*--------------------------------------------------------------------------+
  605. * The PCI initialization sequence enable bit must be set ... if not abort
  606. * pci setup since updating the bit requires chip reset.
  607. *--------------------------------------------------------------------------*/
  608. #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
  609. unsigned long strap;
  610. mfsdr(SDR0_SDSTP1,strap);
  611. if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
  612. printf("PCI: SDR0_STRP1[PISE] not set.\n");
  613. printf("PCI: Configuration aborted.\n");
  614. return -1;
  615. }
  616. #elif defined(CONFIG_440GP)
  617. unsigned long strap;
  618. strap = mfdcr(CPC0_STRP1);
  619. if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
  620. printf("PCI: CPC0_STRP1[PISE] not set.\n");
  621. printf("PCI: Configuration aborted.\n");
  622. return -1;
  623. }
  624. #endif
  625. #endif /* CONFIG_DISABLE_PISE_TEST */
  626. /*--------------------------------------------------------------------------+
  627. * PCI controller init
  628. *--------------------------------------------------------------------------*/
  629. hose->first_busno = 0;
  630. hose->last_busno = 0;
  631. /* PCI I/O space */
  632. pci_set_region(hose->regions + reg_num++,
  633. 0x00000000,
  634. PCIL0_IOBASE,
  635. 0x10000,
  636. PCI_REGION_IO);
  637. /* PCI memory space */
  638. pci_set_region(hose->regions + reg_num++,
  639. CONFIG_SYS_PCI_TARGBASE,
  640. CONFIG_SYS_PCI_MEMBASE,
  641. #ifdef CONFIG_SYS_PCI_MEMSIZE
  642. CONFIG_SYS_PCI_MEMSIZE,
  643. #else
  644. 0x10000000,
  645. #endif
  646. PCI_REGION_MEM );
  647. #if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
  648. defined(CONFIG_PCI_SYS_MEM_SIZE)
  649. /* System memory space */
  650. pci_set_region(hose->regions + reg_num++,
  651. CONFIG_PCI_SYS_MEM_BUS,
  652. CONFIG_PCI_SYS_MEM_PHYS,
  653. CONFIG_PCI_SYS_MEM_SIZE,
  654. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY );
  655. #endif
  656. hose->region_count = reg_num;
  657. pci_setup_indirect(hose, PCIL0_CFGADR, PCIL0_CFGDATA);
  658. /* Let board change/modify hose & do initial checks */
  659. if (pci_pre_init(hose) == 0) {
  660. printf("PCI: Board-specific initialization failed.\n");
  661. printf("PCI: Configuration aborted.\n");
  662. return -1;
  663. }
  664. pci_register_hose( hose );
  665. /*--------------------------------------------------------------------------+
  666. * PCI target init
  667. *--------------------------------------------------------------------------*/
  668. #if defined(CONFIG_SYS_PCI_TARGET_INIT)
  669. pci_target_init(hose); /* Let board setup pci target */
  670. #else
  671. out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
  672. out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
  673. out16r( PCIL0_CLS, 0x00060000 ); /* Bridge, host bridge */
  674. #endif
  675. #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
  676. defined(CONFIG_460EX) || defined(CONFIG_460GT)
  677. out32r( PCIL0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
  678. out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
  679. #elif defined(PCIL0_BRDGOPT1)
  680. out32r( PCIL0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
  681. out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 1 ); /* Enable host config */
  682. #endif
  683. /*--------------------------------------------------------------------------+
  684. * PCI master init: default is one 256MB region for PCI memory:
  685. * 0x3_00000000 - 0x3_0FFFFFFF ==> CONFIG_SYS_PCI_MEMBASE
  686. *--------------------------------------------------------------------------*/
  687. #if defined(CONFIG_SYS_PCI_MASTER_INIT)
  688. pci_master_init(hose); /* Let board setup pci master */
  689. #else
  690. out32r( PCIL0_POM0SA, 0 ); /* disable */
  691. out32r( PCIL0_POM1SA, 0 ); /* disable */
  692. out32r( PCIL0_POM2SA, 0 ); /* disable */
  693. #if defined(CONFIG_440SPE)
  694. out32r( PCIL0_POM0LAL, 0x10000000 );
  695. out32r( PCIL0_POM0LAH, 0x0000000c );
  696. #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
  697. out32r( PCIL0_POM0LAL, 0x20000000 );
  698. out32r( PCIL0_POM0LAH, 0x0000000c );
  699. #else
  700. out32r( PCIL0_POM0LAL, 0x00000000 );
  701. out32r( PCIL0_POM0LAH, 0x00000003 );
  702. #endif
  703. out32r( PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
  704. out32r( PCIL0_POM0PCIAH, 0x00000000 );
  705. out32r( PCIL0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
  706. out32r( PCIL0_STS, in32r( PCIL0_STS ) & ~0x0000fff8 );
  707. #endif
  708. /*--------------------------------------------------------------------------+
  709. * PCI host configuration -- we don't make any assumptions here ... the
  710. * _board_must_indicate_ what to do -- there's just too many runtime
  711. * scenarios in environments like cPCI, PPMC, etc. to make a determination
  712. * based on hard-coded values or state of arbiter enable.
  713. *--------------------------------------------------------------------------*/
  714. if (is_pci_host(hose)) {
  715. #ifdef CONFIG_PCI_SCAN_SHOW
  716. printf("PCI: Bus Dev VenId DevId Class Int\n");
  717. #endif
  718. #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
  719. !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
  720. out16r( PCIL0_CMD, in16r( PCIL0_CMD ) | PCI_COMMAND_MASTER);
  721. #endif
  722. hose->last_busno = pci_hose_scan(hose);
  723. }
  724. return hose->last_busno;
  725. }
  726. #endif
  727. void pci_init_board(void)
  728. {
  729. int busno = 0;
  730. /*
  731. * Only init PCI when either master or target functionality
  732. * is selected.
  733. */
  734. #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
  735. busno = pci_440_init(&ppc440_hose);
  736. if (busno < 0)
  737. return;
  738. #endif
  739. #if (defined(CONFIG_440SPE) || \
  740. defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
  741. !defined(CONFIG_PCI_DISABLE_PCIE)
  742. pcie_setup_hoses(busno + 1);
  743. #endif
  744. }
  745. #endif /* CONFIG_440 */
  746. #if defined(CONFIG_405EX)
  747. void pci_init_board(void)
  748. {
  749. #ifdef CONFIG_PCI_SCAN_SHOW
  750. printf("PCI: Bus Dev VenId DevId Class Int\n");
  751. #endif
  752. pcie_setup_hoses(0);
  753. }
  754. #endif /* CONFIG_405EX */
  755. #endif /* CONFIG_PCI */